| 1 | /* |
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| 2 | * VCE_2_0 Register documentation |
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| 3 | * |
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| 4 | * Copyright (C) 2014 Advanced Micro Devices, Inc. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the "Software"), |
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| 8 | * to deal in the Software without restriction, including without limitation |
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| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 11 | * Software is furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included |
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| 14 | * in all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
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| 20 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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| 21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 22 | */ |
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| 23 | |
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| 24 | #ifndef VCE_2_0_D_H |
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| 25 | #define VCE_2_0_D_H |
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| 26 | |
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| 27 | #define mmVCE_STATUS 0x8001 |
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| 28 | #define mmVCE_VCPU_CNTL 0x8005 |
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| 29 | #define mmVCE_VCPU_CACHE_OFFSET0 0x8009 |
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| 30 | #define mmVCE_VCPU_CACHE_SIZE0 0x800a |
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| 31 | #define mmVCE_VCPU_CACHE_OFFSET1 0x800b |
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| 32 | #define mmVCE_VCPU_CACHE_SIZE1 0x800c |
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| 33 | #define mmVCE_VCPU_CACHE_OFFSET2 0x800d |
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| 34 | #define mmVCE_VCPU_CACHE_SIZE2 0x800e |
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| 35 | #define mmVCE_SOFT_RESET 0x8048 |
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| 36 | #define mmVCE_RB_BASE_LO2 0x805b |
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| 37 | #define mmVCE_RB_BASE_HI2 0x805c |
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| 38 | #define mmVCE_RB_SIZE2 0x805d |
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| 39 | #define mmVCE_RB_RPTR2 0x805e |
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| 40 | #define mmVCE_RB_WPTR2 0x805f |
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| 41 | #define mmVCE_RB_BASE_LO 0x8060 |
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| 42 | #define mmVCE_RB_BASE_HI 0x8061 |
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| 43 | #define mmVCE_RB_SIZE 0x8062 |
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| 44 | #define mmVCE_RB_RPTR 0x8063 |
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| 45 | #define mmVCE_RB_WPTR 0x8064 |
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| 46 | #define mmVCE_RB_ARB_CTRL 0x809f |
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| 47 | #define mmVCE_CLOCK_GATING_A 0x80be |
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| 48 | #define mmVCE_CLOCK_GATING_B 0x80bf |
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| 49 | #define mmVCE_UENC_DMA_DCLK_CTRL 0x8390 |
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| 50 | #define mmVCE_CGTT_CLK_OVERRIDE 0x81e8 |
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| 51 | #define mmVCE_UENC_CLOCK_GATING 0x81ef |
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| 52 | #define mmVCE_UENC_REG_CLOCK_GATING 0x81f0 |
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| 53 | #define mmVCE_SYS_INT_EN 0x84c0 |
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| 54 | #define mmVCE_SYS_INT_STATUS 0x84c1 |
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| 55 | #define mmVCE_SYS_INT_ACK 0x84c1 |
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| 56 | #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR 0x8517 |
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| 57 | #define mmVCE_LMI_CTRL2 0x851d |
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| 58 | #define mmVCE_LMI_SWAP_CNTL3 0x851e |
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| 59 | #define mmVCE_LMI_CTRL 0x8526 |
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| 60 | #define mmVCE_LMI_STATUS 0x8527 |
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| 61 | #define mmVCE_LMI_VM_CTRL 0x8528 |
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| 62 | #define mmVCE_LMI_SWAP_CNTL 0x852d |
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| 63 | #define mmVCE_LMI_SWAP_CNTL1 0x852e |
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| 64 | #define mmVCE_LMI_SWAP_CNTL2 0x8533 |
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| 65 | #define mmVCE_LMI_MISC_CTRL 0x8535 |
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| 66 | #define mmVCE_LMI_CACHE_CTRL 0x853d |
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| 67 | |
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| 68 | #endif /* VCE_2_0_D_H */ |
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| 69 | |
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