1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __AMD_SHARED_H__
24#define __AMD_SHARED_H__
25
26#include <drm/amd_asic_type.h>
27#include <drm/drm_print.h>
28
29
30#define AMD_MAX_USEC_TIMEOUT 1000000 /* 1000 ms */
31struct amdgpu_ip_block;
32
33
34/*
35 * Chip flags
36 */
37enum amd_chip_flags {
38 AMD_ASIC_MASK = 0x0000ffffUL,
39 AMD_FLAGS_MASK = 0xffff0000UL,
40 AMD_IS_MOBILITY = 0x00010000UL,
41 AMD_IS_APU = 0x00020000UL,
42 AMD_IS_PX = 0x00040000UL,
43 AMD_EXP_HW_SUPPORT = 0x00080000UL,
44};
45
46enum amd_apu_flags {
47 AMD_APU_IS_RAVEN = 0x00000001UL,
48 AMD_APU_IS_RAVEN2 = 0x00000002UL,
49 AMD_APU_IS_PICASSO = 0x00000004UL,
50 AMD_APU_IS_RENOIR = 0x00000008UL,
51 AMD_APU_IS_GREEN_SARDINE = 0x00000010UL,
52 AMD_APU_IS_VANGOGH = 0x00000020UL,
53 AMD_APU_IS_CYAN_SKILLFISH2 = 0x00000040UL,
54};
55
56/**
57* DOC: IP Blocks
58*
59* GPUs are composed of IP (intellectual property) blocks. These
60* IP blocks provide various functionalities: display, graphics,
61* video decode, etc. The IP blocks that comprise a particular GPU
62* are listed in the GPU's respective SoC file. amdgpu_device.c
63* acquires the list of IP blocks for the GPU in use on initialization.
64* It can then operate on this list to perform standard driver operations
65* such as: init, fini, suspend, resume, etc.
66*
67*
68* IP block implementations are named using the following convention:
69* <functionality>_v<version> (E.g.: gfx_v6_0).
70*/
71
72/**
73* enum amd_ip_block_type - Used to classify IP blocks by functionality.
74*
75* @AMD_IP_BLOCK_TYPE_COMMON: GPU Family
76* @AMD_IP_BLOCK_TYPE_GMC: Graphics Memory Controller
77* @AMD_IP_BLOCK_TYPE_IH: Interrupt Handler
78* @AMD_IP_BLOCK_TYPE_SMC: System Management Controller
79* @AMD_IP_BLOCK_TYPE_PSP: Platform Security Processor
80* @AMD_IP_BLOCK_TYPE_DCE: Display and Compositing Engine
81* @AMD_IP_BLOCK_TYPE_GFX: Graphics and Compute Engine
82* @AMD_IP_BLOCK_TYPE_SDMA: System DMA Engine
83* @AMD_IP_BLOCK_TYPE_UVD: Unified Video Decoder
84* @AMD_IP_BLOCK_TYPE_VCE: Video Compression Engine
85* @AMD_IP_BLOCK_TYPE_ACP: Audio Co-Processor
86* @AMD_IP_BLOCK_TYPE_VCN: Video Core/Codec Next
87* @AMD_IP_BLOCK_TYPE_MES: Micro-Engine Scheduler
88* @AMD_IP_BLOCK_TYPE_JPEG: JPEG Engine
89* @AMD_IP_BLOCK_TYPE_VPE: Video Processing Engine
90* @AMD_IP_BLOCK_TYPE_UMSCH_MM: User Mode Scheduler for Multimedia
91* @AMD_IP_BLOCK_TYPE_ISP: Image Signal Processor
92* @AMD_IP_BLOCK_TYPE_NUM: Total number of IP block types
93*/
94enum amd_ip_block_type {
95 AMD_IP_BLOCK_TYPE_COMMON,
96 AMD_IP_BLOCK_TYPE_GMC,
97 AMD_IP_BLOCK_TYPE_IH,
98 AMD_IP_BLOCK_TYPE_SMC,
99 AMD_IP_BLOCK_TYPE_PSP,
100 AMD_IP_BLOCK_TYPE_DCE,
101 AMD_IP_BLOCK_TYPE_GFX,
102 AMD_IP_BLOCK_TYPE_SDMA,
103 AMD_IP_BLOCK_TYPE_UVD,
104 AMD_IP_BLOCK_TYPE_VCE,
105 AMD_IP_BLOCK_TYPE_ACP,
106 AMD_IP_BLOCK_TYPE_VCN,
107 AMD_IP_BLOCK_TYPE_MES,
108 AMD_IP_BLOCK_TYPE_JPEG,
109 AMD_IP_BLOCK_TYPE_VPE,
110 AMD_IP_BLOCK_TYPE_UMSCH_MM,
111 AMD_IP_BLOCK_TYPE_ISP,
112 AMD_IP_BLOCK_TYPE_RAS,
113 AMD_IP_BLOCK_TYPE_NUM,
114};
115
116enum amd_clockgating_state {
117 AMD_CG_STATE_GATE = 0,
118 AMD_CG_STATE_UNGATE,
119};
120
121
122enum amd_powergating_state {
123 AMD_PG_STATE_GATE = 0,
124 AMD_PG_STATE_UNGATE,
125};
126
127
128/* CG flags */
129#define AMD_CG_SUPPORT_GFX_MGCG (1ULL << 0)
130#define AMD_CG_SUPPORT_GFX_MGLS (1ULL << 1)
131#define AMD_CG_SUPPORT_GFX_CGCG (1ULL << 2)
132#define AMD_CG_SUPPORT_GFX_CGLS (1ULL << 3)
133#define AMD_CG_SUPPORT_GFX_CGTS (1ULL << 4)
134#define AMD_CG_SUPPORT_GFX_CGTS_LS (1ULL << 5)
135#define AMD_CG_SUPPORT_GFX_CP_LS (1ULL << 6)
136#define AMD_CG_SUPPORT_GFX_RLC_LS (1ULL << 7)
137#define AMD_CG_SUPPORT_MC_LS (1ULL << 8)
138#define AMD_CG_SUPPORT_MC_MGCG (1ULL << 9)
139#define AMD_CG_SUPPORT_SDMA_LS (1ULL << 10)
140#define AMD_CG_SUPPORT_SDMA_MGCG (1ULL << 11)
141#define AMD_CG_SUPPORT_BIF_LS (1ULL << 12)
142#define AMD_CG_SUPPORT_UVD_MGCG (1ULL << 13)
143#define AMD_CG_SUPPORT_VCE_MGCG (1ULL << 14)
144#define AMD_CG_SUPPORT_HDP_LS (1ULL << 15)
145#define AMD_CG_SUPPORT_HDP_MGCG (1ULL << 16)
146#define AMD_CG_SUPPORT_ROM_MGCG (1ULL << 17)
147#define AMD_CG_SUPPORT_DRM_LS (1ULL << 18)
148#define AMD_CG_SUPPORT_BIF_MGCG (1ULL << 19)
149#define AMD_CG_SUPPORT_GFX_3D_CGCG (1ULL << 20)
150#define AMD_CG_SUPPORT_GFX_3D_CGLS (1ULL << 21)
151#define AMD_CG_SUPPORT_DRM_MGCG (1ULL << 22)
152#define AMD_CG_SUPPORT_DF_MGCG (1ULL << 23)
153#define AMD_CG_SUPPORT_VCN_MGCG (1ULL << 24)
154#define AMD_CG_SUPPORT_HDP_DS (1ULL << 25)
155#define AMD_CG_SUPPORT_HDP_SD (1ULL << 26)
156#define AMD_CG_SUPPORT_IH_CG (1ULL << 27)
157#define AMD_CG_SUPPORT_ATHUB_LS (1ULL << 28)
158#define AMD_CG_SUPPORT_ATHUB_MGCG (1ULL << 29)
159#define AMD_CG_SUPPORT_JPEG_MGCG (1ULL << 30)
160#define AMD_CG_SUPPORT_GFX_FGCG (1ULL << 31)
161#define AMD_CG_SUPPORT_REPEATER_FGCG (1ULL << 32)
162#define AMD_CG_SUPPORT_GFX_PERF_CLK (1ULL << 33)
163/* PG flags */
164#define AMD_PG_SUPPORT_GFX_PG (1 << 0)
165#define AMD_PG_SUPPORT_GFX_SMG (1 << 1)
166#define AMD_PG_SUPPORT_GFX_DMG (1 << 2)
167#define AMD_PG_SUPPORT_UVD (1 << 3)
168#define AMD_PG_SUPPORT_VCE (1 << 4)
169#define AMD_PG_SUPPORT_CP (1 << 5)
170#define AMD_PG_SUPPORT_GDS (1 << 6)
171#define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7)
172#define AMD_PG_SUPPORT_SDMA (1 << 8)
173#define AMD_PG_SUPPORT_ACP (1 << 9)
174#define AMD_PG_SUPPORT_SAMU (1 << 10)
175#define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11)
176#define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12)
177#define AMD_PG_SUPPORT_MMHUB (1 << 13)
178#define AMD_PG_SUPPORT_VCN (1 << 14)
179#define AMD_PG_SUPPORT_VCN_DPG (1 << 15)
180#define AMD_PG_SUPPORT_ATHUB (1 << 16)
181#define AMD_PG_SUPPORT_JPEG (1 << 17)
182#define AMD_PG_SUPPORT_IH_SRAM_PG (1 << 18)
183#define AMD_PG_SUPPORT_JPEG_DPG (1 << 19)
184
185/**
186 * enum PP_FEATURE_MASK - Used to mask power play features.
187 *
188 * @PP_SCLK_DPM_MASK: Dynamic adjustment of the system (graphics) clock.
189 * @PP_MCLK_DPM_MASK: Dynamic adjustment of the memory clock.
190 * @PP_PCIE_DPM_MASK: Dynamic adjustment of PCIE clocks and lanes.
191 * @PP_SCLK_DEEP_SLEEP_MASK: System (graphics) clock deep sleep.
192 * @PP_POWER_CONTAINMENT_MASK: Power containment.
193 * @PP_UVD_HANDSHAKE_MASK: Unified video decoder handshake.
194 * @PP_SMC_VOLTAGE_CONTROL_MASK: Dynamic voltage control.
195 * @PP_VBI_TIME_SUPPORT_MASK: Vertical blank interval support.
196 * @PP_ULV_MASK: Ultra low voltage.
197 * @PP_ENABLE_GFX_CG_THRU_SMU: SMU control of GFX engine clockgating.
198 * @PP_CLOCK_STRETCH_MASK: Clock stretching.
199 * @PP_OD_FUZZY_FAN_CONTROL_MASK: Overdrive fuzzy fan control.
200 * @PP_SOCCLK_DPM_MASK: Dynamic adjustment of the SoC clock.
201 * @PP_DCEFCLK_DPM_MASK: Dynamic adjustment of the Display Controller Engine Fabric clock.
202 * @PP_OVERDRIVE_MASK: Over- and under-clocking support.
203 * @PP_GFXOFF_MASK: Dynamic graphics engine power control.
204 * @PP_ACG_MASK: Adaptive clock generator.
205 * @PP_STUTTER_MODE: Stutter mode.
206 * @PP_AVFS_MASK: Adaptive voltage and frequency scaling.
207 * @PP_GFX_DCS_MASK: GFX Async DCS.
208 *
209 * To override these settings on boot, append amdgpu.ppfeaturemask=<mask> to
210 * the kernel's command line parameters. This is usually done through a system's
211 * boot loader (E.g. GRUB). If manually loading the driver, pass
212 * ppfeaturemask=<mask> as a modprobe parameter.
213 */
214enum PP_FEATURE_MASK {
215 PP_SCLK_DPM_MASK = 0x1,
216 PP_MCLK_DPM_MASK = 0x2,
217 PP_PCIE_DPM_MASK = 0x4,
218 PP_SCLK_DEEP_SLEEP_MASK = 0x8,
219 PP_POWER_CONTAINMENT_MASK = 0x10,
220 PP_UVD_HANDSHAKE_MASK = 0x20,
221 PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
222 PP_VBI_TIME_SUPPORT_MASK = 0x80,
223 PP_ULV_MASK = 0x100,
224 PP_ENABLE_GFX_CG_THRU_SMU = 0x200,
225 PP_CLOCK_STRETCH_MASK = 0x400,
226 PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
227 PP_SOCCLK_DPM_MASK = 0x1000,
228 PP_DCEFCLK_DPM_MASK = 0x2000,
229 PP_OVERDRIVE_MASK = 0x4000,
230 PP_GFXOFF_MASK = 0x8000,
231 PP_ACG_MASK = 0x10000,
232 PP_STUTTER_MODE = 0x20000,
233 PP_AVFS_MASK = 0x40000,
234 PP_GFX_DCS_MASK = 0x80000,
235};
236
237enum amd_harvest_ip_mask {
238 AMD_HARVEST_IP_VCN_MASK = 0x1,
239 AMD_HARVEST_IP_JPEG_MASK = 0x2,
240 AMD_HARVEST_IP_DMU_MASK = 0x4,
241};
242
243/**
244 * enum DC_FEATURE_MASK - Bits that control DC feature defaults
245 */
246enum DC_FEATURE_MASK {
247 //Default value can be found at "uint amdgpu_dc_feature_mask"
248 /**
249 * @DC_FBC_MASK: (0x1) disabled by default
250 */
251 DC_FBC_MASK = (1 << 0),
252 /**
253 * @DC_MULTI_MON_PP_MCLK_SWITCH_MASK: (0x2) enabled by default
254 */
255 DC_MULTI_MON_PP_MCLK_SWITCH_MASK = (1 << 1),
256 /**
257 * @DC_DISABLE_FRACTIONAL_PWM_MASK: (0x4) disabled by default
258 */
259 DC_DISABLE_FRACTIONAL_PWM_MASK = (1 << 2),
260 /**
261 * @DC_PSR_MASK: (0x8) disabled by default for DCN < 3.1
262 */
263 DC_PSR_MASK = (1 << 3),
264 /**
265 * @DC_EDP_NO_POWER_SEQUENCING: (0x10) disabled by default
266 */
267 DC_EDP_NO_POWER_SEQUENCING = (1 << 4),
268 /**
269 * @DC_DISABLE_LTTPR_DP1_4A: (0x20) disabled by default
270 */
271 DC_DISABLE_LTTPR_DP1_4A = (1 << 5),
272 /**
273 * @DC_DISABLE_LTTPR_DP2_0: (0x40) disabled by default
274 */
275 DC_DISABLE_LTTPR_DP2_0 = (1 << 6),
276 /**
277 * @DC_PSR_ALLOW_SMU_OPT: (0x80) disabled by default
278 */
279 DC_PSR_ALLOW_SMU_OPT = (1 << 7),
280 /**
281 * @DC_PSR_ALLOW_MULTI_DISP_OPT: (0x100) disabled by default
282 */
283 DC_PSR_ALLOW_MULTI_DISP_OPT = (1 << 8),
284 /**
285 * @DC_REPLAY_MASK: (0x200) disabled by default for DCN < 3.1.4
286 */
287 DC_REPLAY_MASK = (1 << 9),
288};
289
290/**
291 * enum DC_DEBUG_MASK - Bits that are useful for debugging the Display Core IP
292 */
293enum DC_DEBUG_MASK {
294 /**
295 * @DC_DISABLE_PIPE_SPLIT: (0x1) If set, disable pipe-splitting
296 */
297 DC_DISABLE_PIPE_SPLIT = 0x1,
298
299 /**
300 * @DC_DISABLE_STUTTER: (0x2) If set, disable memory stutter mode
301 */
302 DC_DISABLE_STUTTER = 0x2,
303
304 /**
305 * @DC_DISABLE_DSC: (0x4) If set, disable display stream compression
306 */
307 DC_DISABLE_DSC = 0x4,
308
309 /**
310 * @DC_DISABLE_CLOCK_GATING: (0x8) If set, disable clock gating optimizations
311 */
312 DC_DISABLE_CLOCK_GATING = 0x8,
313
314 /**
315 * @DC_DISABLE_PSR: (0x10) If set, disable Panel self refresh v1 and PSR-SU
316 */
317 DC_DISABLE_PSR = 0x10,
318
319 /**
320 * @DC_FORCE_SUBVP_MCLK_SWITCH: (0x20) If set, force mclk switch in subvp, even
321 * if mclk switch in vblank is possible
322 */
323 DC_FORCE_SUBVP_MCLK_SWITCH = 0x20,
324
325 /**
326 * @DC_DISABLE_MPO: (0x40) If set, disable multi-plane offloading
327 */
328 DC_DISABLE_MPO = 0x40,
329
330 /**
331 * @DC_ENABLE_DPIA_TRACE: (0x80) If set, enable trace logging for DPIA
332 */
333 DC_ENABLE_DPIA_TRACE = 0x80,
334
335 /**
336 * @DC_ENABLE_DML2: (0x100) If set, force usage of DML2, even if the DCN version
337 * does not default to it.
338 */
339 DC_ENABLE_DML2 = 0x100,
340
341 /**
342 * @DC_DISABLE_PSR_SU: (0x200) If set, disable PSR SU
343 */
344 DC_DISABLE_PSR_SU = 0x200,
345
346 /**
347 * @DC_DISABLE_REPLAY: (0x400) If set, disable Panel Replay
348 */
349 DC_DISABLE_REPLAY = 0x400,
350
351 /**
352 * @DC_DISABLE_IPS: (0x800) If set, disable all Idle Power States, all the time.
353 * If more than one IPS debug bit is set, the lowest bit takes
354 * precedence. For example, if DC_FORCE_IPS_ENABLE and
355 * DC_DISABLE_IPS_DYNAMIC are set, then DC_DISABLE_IPS_DYNAMIC takes
356 * precedence.
357 */
358 DC_DISABLE_IPS = 0x800,
359
360 /**
361 * @DC_DISABLE_IPS_DYNAMIC: (0x1000) If set, disable all IPS, all the time,
362 * *except* when driver goes into suspend.
363 */
364 DC_DISABLE_IPS_DYNAMIC = 0x1000,
365
366 /**
367 * @DC_DISABLE_IPS2_DYNAMIC: (0x2000) If set, disable IPS2 (IPS1 allowed) if
368 * there is an enabled display. Otherwise, enable all IPS.
369 */
370 DC_DISABLE_IPS2_DYNAMIC = 0x2000,
371
372 /**
373 * @DC_FORCE_IPS_ENABLE: (0x4000) If set, force enable all IPS, all the time.
374 */
375 DC_FORCE_IPS_ENABLE = 0x4000,
376 /**
377 * @DC_DISABLE_ACPI_EDID: (0x8000) If set, don't attempt to fetch EDID for
378 * eDP display from ACPI _DDC method.
379 */
380 DC_DISABLE_ACPI_EDID = 0x8000,
381
382 /**
383 * @DC_DISABLE_HDMI_CEC: (0x10000) If set, disable HDMI-CEC feature in amdgpu driver.
384 */
385 DC_DISABLE_HDMI_CEC = 0x10000,
386
387 /**
388 * @DC_DISABLE_SUBVP_FAMS: (0x20000) If set, disable DCN Sub-Viewport & Firmware Assisted
389 * Memory Clock Switching (FAMS) feature in amdgpu driver.
390 */
391 DC_DISABLE_SUBVP_FAMS = 0x20000,
392 /**
393 * @DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE: (0x40000) If set, disable support for custom
394 * brightness curves
395 */
396 DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE = 0x40000,
397
398 /**
399 * @DC_HDCP_LC_FORCE_FW_ENABLE: (0x80000) If set, use HDCP Locality Check FW
400 * path regardless of reported HW capabilities.
401 */
402 DC_HDCP_LC_FORCE_FW_ENABLE = 0x80000,
403
404 /**
405 * @DC_HDCP_LC_ENABLE_SW_FALLBACK: (0x100000) If set, upon HDCP Locality Check FW
406 * path failure, retry using legacy SW path.
407 */
408 DC_HDCP_LC_ENABLE_SW_FALLBACK = 0x100000,
409
410 /**
411 * @DC_SKIP_DETECTION_LT: (0x200000) If set, skip detection link training
412 */
413 DC_SKIP_DETECTION_LT = 0x200000,
414};
415
416enum amd_dpm_forced_level;
417
418/**
419 * struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks
420 * @name: Name of IP block
421 * @early_init: sets up early driver state (pre sw_init),
422 * does not configure hw - Optional
423 * @late_init: sets up late driver/hw state (post hw_init) - Optional
424 * @sw_init: sets up driver state, does not configure hw
425 * @sw_fini: tears down driver state, does not configure hw
426 * @early_fini: tears down stuff before dev detached from driver
427 * @hw_init: sets up the hw state
428 * @hw_fini: tears down the hw state
429 * @late_fini: final cleanup
430 * @prepare_suspend: handle IP specific changes to prepare for suspend
431 * (such as allocating any required memory)
432 * @suspend: handles IP specific hw/sw changes for suspend
433 * @resume: handles IP specific hw/sw changes for resume
434 * @complete: handles IP specific changes after resume
435 * @is_idle: returns current IP block idle status
436 * @wait_for_idle: poll for idle
437 * @check_soft_reset: check soft reset the IP block
438 * @pre_soft_reset: pre soft reset the IP block
439 * @soft_reset: soft reset the IP block
440 * @post_soft_reset: post soft reset the IP block
441 * @set_clockgating_state: enable/disable cg for the IP block
442 * @set_powergating_state: enable/disable pg for the IP block
443 * @get_clockgating_state: get current clockgating status
444 * @dump_ip_state: dump the IP state of the ASIC during a gpu hang
445 * @print_ip_state: print the IP state in devcoredump for each IP of the ASIC
446 *
447 * These hooks provide an interface for controlling the operational state
448 * of IP blocks. After acquiring a list of IP blocks for the GPU in use,
449 * the driver can make chip-wide state changes by walking this list and
450 * making calls to hooks from each IP block. This list is ordered to ensure
451 * that the driver initializes the IP blocks in a safe sequence.
452 */
453struct amd_ip_funcs {
454 char *name;
455 int (*early_init)(struct amdgpu_ip_block *ip_block);
456 int (*late_init)(struct amdgpu_ip_block *ip_block);
457 int (*sw_init)(struct amdgpu_ip_block *ip_block);
458 int (*sw_fini)(struct amdgpu_ip_block *ip_block);
459 int (*early_fini)(struct amdgpu_ip_block *ip_block);
460 int (*hw_init)(struct amdgpu_ip_block *ip_block);
461 int (*hw_fini)(struct amdgpu_ip_block *ip_block);
462 void (*late_fini)(struct amdgpu_ip_block *ip_block);
463 int (*prepare_suspend)(struct amdgpu_ip_block *ip_block);
464 int (*suspend)(struct amdgpu_ip_block *ip_block);
465 int (*resume)(struct amdgpu_ip_block *ip_block);
466 void (*complete)(struct amdgpu_ip_block *ip_block);
467 bool (*is_idle)(struct amdgpu_ip_block *ip_block);
468 int (*wait_for_idle)(struct amdgpu_ip_block *ip_block);
469 bool (*check_soft_reset)(struct amdgpu_ip_block *ip_block);
470 int (*pre_soft_reset)(struct amdgpu_ip_block *ip_block);
471 int (*soft_reset)(struct amdgpu_ip_block *ip_block);
472 int (*post_soft_reset)(struct amdgpu_ip_block *ip_block);
473 int (*set_clockgating_state)(struct amdgpu_ip_block *ip_block,
474 enum amd_clockgating_state state);
475 int (*set_powergating_state)(struct amdgpu_ip_block *ip_block,
476 enum amd_powergating_state state);
477 void (*get_clockgating_state)(struct amdgpu_ip_block *ip_block, u64 *flags);
478 void (*dump_ip_state)(struct amdgpu_ip_block *ip_block);
479 void (*print_ip_state)(struct amdgpu_ip_block *ip_block, struct drm_printer *p);
480};
481
482
483#endif /* __AMD_SHARED_H__ */
484

source code of linux/drivers/gpu/drm/amd/include/amd_shared.h