1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef _DMUB_SRV_H_
27#define _DMUB_SRV_H_
28
29/**
30 * DOC: DMUB interface and operation
31 *
32 * DMUB is the interface to the display DMCUB microcontroller on DCN hardware.
33 * It delegates hardware initialization and command submission to the
34 * microcontroller. DMUB is the shortname for DMCUB.
35 *
36 * This interface is not thread-safe. Ensure that all access to the interface
37 * is properly synchronized by the caller.
38 *
39 * Initialization and usage of the DMUB service should be done in the
40 * steps given below:
41 *
42 * 1. dmub_srv_create()
43 * 2. dmub_srv_has_hw_support()
44 * 3. dmub_srv_calc_region_info()
45 * 4. dmub_srv_hw_init()
46 *
47 * The call to dmub_srv_create() is required to use the server.
48 *
49 * The calls to dmub_srv_has_hw_support() and dmub_srv_calc_region_info()
50 * are helpers to query cache window size and allocate framebuffer(s)
51 * for the cache windows.
52 *
53 * The call to dmub_srv_hw_init() programs the DMCUB registers to prepare
54 * for command submission. Commands can be queued via dmub_srv_fb_cmd_queue()
55 * and executed via dmub_srv_fb_cmd_execute().
56 *
57 * If the queue is full the dmub_srv_wait_for_idle() call can be used to
58 * wait until the queue has been cleared.
59 *
60 * Destroying the DMUB service can be done by calling dmub_srv_destroy().
61 * This does not clear DMUB hardware state, only software state.
62 *
63 * The interface is intended to be standalone and should not depend on any
64 * other component within DAL.
65 */
66
67#include "inc/dmub_cmd.h"
68#include "dc/dc_types.h"
69
70#define DMUB_PC_SNAPSHOT_COUNT 10
71
72/* Default tracebuffer size if meta is absent. */
73#define DMUB_TRACE_BUFFER_SIZE (64 * 1024)
74
75/* Forward declarations */
76struct dmub_srv;
77struct dmub_srv_common_regs;
78struct dmub_srv_dcn31_regs;
79
80struct dmcub_trace_buf_entry;
81
82/* enum dmub_window_memory_type - memory location type specification for windows */
83enum dmub_window_memory_type {
84 DMUB_WINDOW_MEMORY_TYPE_FB = 0,
85 DMUB_WINDOW_MEMORY_TYPE_GART
86};
87
88/* enum dmub_status - return code for dmcub functions */
89enum dmub_status {
90 DMUB_STATUS_OK = 0,
91 DMUB_STATUS_NO_CTX,
92 DMUB_STATUS_QUEUE_FULL,
93 DMUB_STATUS_TIMEOUT,
94 DMUB_STATUS_INVALID,
95 DMUB_STATUS_HW_FAILURE,
96 DMUB_STATUS_POWER_STATE_D3
97};
98
99/* enum dmub_asic - dmub asic identifier */
100enum dmub_asic {
101 DMUB_ASIC_NONE = 0,
102 DMUB_ASIC_DCN20,
103 DMUB_ASIC_DCN21,
104 DMUB_ASIC_DCN30,
105 DMUB_ASIC_DCN301,
106 DMUB_ASIC_DCN302,
107 DMUB_ASIC_DCN303,
108 DMUB_ASIC_DCN31,
109 DMUB_ASIC_DCN31B,
110 DMUB_ASIC_DCN314,
111 DMUB_ASIC_DCN315,
112 DMUB_ASIC_DCN316,
113 DMUB_ASIC_DCN32,
114 DMUB_ASIC_DCN321,
115 DMUB_ASIC_DCN35,
116 DMUB_ASIC_DCN351,
117 DMUB_ASIC_DCN36,
118 DMUB_ASIC_DCN401,
119 DMUB_ASIC_MAX,
120};
121
122/* enum dmub_window_id - dmub window identifier */
123enum dmub_window_id {
124 DMUB_WINDOW_0_INST_CONST = 0,
125 DMUB_WINDOW_1_STACK,
126 DMUB_WINDOW_2_BSS_DATA,
127 DMUB_WINDOW_3_VBIOS,
128 DMUB_WINDOW_4_MAILBOX,
129 DMUB_WINDOW_5_TRACEBUFF,
130 DMUB_WINDOW_6_FW_STATE,
131 DMUB_WINDOW_7_SCRATCH_MEM,
132 DMUB_WINDOW_IB_MEM,
133 DMUB_WINDOW_SHARED_STATE,
134 DMUB_WINDOW_LSDMA_BUFFER,
135 DMUB_WINDOW_CURSOR_OFFLOAD,
136 DMUB_WINDOW_TOTAL,
137};
138
139/* enum dmub_notification_type - dmub outbox notification identifier */
140enum dmub_notification_type {
141 DMUB_NOTIFICATION_NO_DATA = 0,
142 DMUB_NOTIFICATION_AUX_REPLY,
143 DMUB_NOTIFICATION_HPD,
144 DMUB_NOTIFICATION_HPD_IRQ,
145 DMUB_NOTIFICATION_SET_CONFIG_REPLY,
146 DMUB_NOTIFICATION_DPIA_NOTIFICATION,
147 DMUB_NOTIFICATION_HPD_SENSE_NOTIFY,
148 DMUB_NOTIFICATION_FUSED_IO,
149 DMUB_NOTIFICATION_MAX
150};
151
152/**
153 * DPIA NOTIFICATION Response Type
154 */
155enum dpia_notify_bw_alloc_status {
156
157 DPIA_BW_REQ_FAILED = 0,
158 DPIA_BW_REQ_SUCCESS,
159 DPIA_EST_BW_CHANGED,
160 DPIA_BW_ALLOC_CAPS_CHANGED
161};
162
163/* enum dmub_memory_access_type - memory access method */
164enum dmub_memory_access_type {
165 DMUB_MEMORY_ACCESS_DEFAULT,
166 DMUB_MEMORY_ACCESS_CPU = DMUB_MEMORY_ACCESS_DEFAULT,
167 DMUB_MEMORY_ACCESS_DMA
168};
169
170/* enum dmub_power_state type - to track DC power state in dmub_srv */
171enum dmub_srv_power_state_type {
172 DMUB_POWER_STATE_UNDEFINED = 0,
173 DMUB_POWER_STATE_D0 = 1,
174 DMUB_POWER_STATE_D3 = 8
175};
176
177/* enum dmub_inbox_cmd_interface type - defines default interface for host->dmub commands */
178enum dmub_inbox_cmd_interface_type {
179 DMUB_CMD_INTERFACE_DEFAULT = 0,
180 DMUB_CMD_INTERFACE_FB = 1,
181 DMUB_CMD_INTERFACE_REG = 2,
182};
183
184/**
185 * struct dmub_region - dmub hw memory region
186 * @base: base address for region, must be 256 byte aligned
187 * @top: top address for region
188 */
189struct dmub_region {
190 uint32_t base;
191 uint32_t top;
192};
193
194/**
195 * struct dmub_window - dmub hw cache window
196 * @off: offset to the fb memory in gpu address space
197 * @r: region in uc address space for cache window
198 */
199struct dmub_window {
200 union dmub_addr offset;
201 struct dmub_region region;
202};
203
204/**
205 * struct dmub_fb - defines a dmub framebuffer memory region
206 * @cpu_addr: cpu virtual address for the region, NULL if invalid
207 * @gpu_addr: gpu virtual address for the region, NULL if invalid
208 * @size: size of the region in bytes, zero if invalid
209 */
210struct dmub_fb {
211 void *cpu_addr;
212 uint64_t gpu_addr;
213 uint32_t size;
214};
215
216/**
217 * struct dmub_srv_region_params - params used for calculating dmub regions
218 * @inst_const_size: size of the fw inst const section
219 * @bss_data_size: size of the fw bss data section
220 * @vbios_size: size of the vbios data
221 * @fw_bss_data: raw firmware bss data section
222 */
223struct dmub_srv_region_params {
224 uint32_t inst_const_size;
225 uint32_t bss_data_size;
226 uint32_t vbios_size;
227 const uint8_t *fw_inst_const;
228 const uint8_t *fw_bss_data;
229 const enum dmub_window_memory_type *window_memory_type;
230};
231
232/**
233 * struct dmub_srv_region_info - output region info from the dmub service
234 * @fb_size: required minimum fb size for all regions, aligned to 4096 bytes
235 * @num_regions: number of regions used by the dmub service
236 * @regions: region info
237 *
238 * The regions are aligned such that they can be all placed within the
239 * same framebuffer but they can also be placed into different framebuffers.
240 *
241 * The size of each region can be calculated by the caller:
242 * size = reg.top - reg.base
243 *
244 * Care must be taken when performing custom allocations to ensure that each
245 * region base address is 256 byte aligned.
246 */
247struct dmub_srv_region_info {
248 uint32_t fb_size;
249 uint32_t gart_size;
250 uint8_t num_regions;
251 struct dmub_region regions[DMUB_WINDOW_TOTAL];
252};
253
254/**
255 * struct dmub_srv_memory_params - parameters used for driver fb setup
256 * @region_info: region info calculated by dmub service
257 * @cpu_fb_addr: base cpu address for the framebuffer
258 * @cpu_inbox_addr: base cpu address for the gart
259 * @gpu_fb_addr: base gpu virtual address for the framebuffer
260 * @gpu_inbox_addr: base gpu virtual address for the gart
261 */
262struct dmub_srv_memory_params {
263 const struct dmub_srv_region_info *region_info;
264 void *cpu_fb_addr;
265 void *cpu_gart_addr;
266 uint64_t gpu_fb_addr;
267 uint64_t gpu_gart_addr;
268 const enum dmub_window_memory_type *window_memory_type;
269};
270
271/**
272 * struct dmub_srv_fb_info - output fb info from the dmub service
273 * @num_fbs: number of required dmub framebuffers
274 * @fbs: fb data for each region
275 *
276 * Output from the dmub service helper that can be used by the
277 * driver to prepare dmub_fb that can be passed into the dmub
278 * hw init service.
279 *
280 * Assumes that all regions are within the same framebuffer
281 * and have been setup according to the region_info generated
282 * by the dmub service.
283 */
284struct dmub_srv_fb_info {
285 uint8_t num_fb;
286 struct dmub_fb fb[DMUB_WINDOW_TOTAL];
287};
288
289/*
290 * struct dmub_srv_hw_params - params for dmub hardware initialization
291 * @fb: framebuffer info for each region
292 * @fb_base: base of the framebuffer aperture
293 * @fb_offset: offset of the framebuffer aperture
294 * @psp_version: psp version to pass for DMCU init
295 * @load_inst_const: true if DMUB should load inst const fw
296 */
297struct dmub_srv_hw_params {
298 struct dmub_fb *fb[DMUB_WINDOW_TOTAL];
299 uint64_t fb_base;
300 uint64_t fb_offset;
301 uint32_t psp_version;
302 bool load_inst_const;
303 bool skip_panel_power_sequence;
304 bool disable_z10;
305 bool power_optimization;
306 bool dpia_supported;
307 bool disable_dpia;
308 bool usb4_cm_version;
309 bool fw_in_system_memory;
310 bool dpia_hpd_int_enable_supported;
311 bool disable_clock_gate;
312 bool disallow_dispclk_dppclk_ds;
313 bool ips_sequential_ono;
314 enum dmub_memory_access_type mem_access_type;
315 enum dmub_ips_disable_type disable_ips;
316 bool disallow_phy_access;
317 bool disable_sldo_opt;
318 bool enable_non_transparent_setconfig;
319 bool lower_hbr3_phy_ssc;
320 bool override_hbr3_pll_vco;
321 bool disable_dpia_bw_allocation;
322};
323
324/**
325 * struct dmub_srv_debug - Debug info for dmub_srv
326 * @timeout_occured: Indicates a timeout occured on any message from driver to dmub
327 * @timeout_cmd: first cmd sent from driver that timed out - subsequent timeouts are not stored
328 */
329struct dmub_timeout_info {
330 bool timeout_occured;
331 union dmub_rb_cmd timeout_cmd;
332 unsigned long long timestamp;
333};
334
335/**
336 * struct dmub_diagnostic_data - Diagnostic data retrieved from DMCUB for
337 * debugging purposes, including logging, crash analysis, etc.
338 */
339struct dmub_diagnostic_data {
340 uint32_t dmcub_version;
341 uint32_t scratch[17];
342 uint32_t pc[DMUB_PC_SNAPSHOT_COUNT];
343 uint32_t undefined_address_fault_addr;
344 uint32_t inst_fetch_fault_addr;
345 uint32_t data_write_fault_addr;
346 uint32_t inbox1_rptr;
347 uint32_t inbox1_wptr;
348 uint32_t inbox1_size;
349 uint32_t inbox0_rptr;
350 uint32_t inbox0_wptr;
351 uint32_t inbox0_size;
352 uint32_t outbox1_rptr;
353 uint32_t outbox1_wptr;
354 uint32_t outbox1_size;
355 uint32_t gpint_datain0;
356 struct dmub_timeout_info timeout_info;
357 uint8_t is_dmcub_enabled : 1;
358 uint8_t is_dmcub_soft_reset : 1;
359 uint8_t is_dmcub_secure_reset : 1;
360 uint8_t is_traceport_en : 1;
361 uint8_t is_cw0_enabled : 1;
362 uint8_t is_cw6_enabled : 1;
363 uint8_t is_pwait : 1;
364};
365
366/**
367 * struct dmub_preos_info - preos fw info before loading post os fw.
368 */
369struct dmub_preos_info {
370 uint64_t fb_base;
371 uint64_t fb_offset;
372 uint64_t trace_buffer_phy_addr;
373 uint32_t trace_buffer_size;
374 uint32_t fw_version;
375 uint32_t boot_status;
376 uint32_t boot_options;
377};
378
379struct dmub_srv_inbox {
380 /* generic status */
381 uint64_t num_submitted;
382 uint64_t num_reported;
383 union {
384 /* frame buffer mailbox status */
385 struct dmub_rb rb;
386 /* register mailbox status */
387 struct {
388 bool is_pending;
389 bool is_multi_pending;
390 };
391 };
392};
393
394/**
395 * struct dmub_srv_base_funcs - Driver specific base callbacks
396 */
397struct dmub_srv_base_funcs {
398 /**
399 * @reg_read:
400 *
401 * Hook for reading a register.
402 *
403 * Return: The 32-bit register value from the given address.
404 */
405 uint32_t (*reg_read)(void *ctx, uint32_t address);
406
407 /**
408 * @reg_write:
409 *
410 * Hook for writing a value to the register specified by address.
411 */
412 void (*reg_write)(void *ctx, uint32_t address, uint32_t value);
413};
414
415/**
416 * struct dmub_srv_hw_funcs - hardware sequencer funcs for dmub
417 */
418struct dmub_srv_hw_funcs {
419 /* private: internal use only */
420
421 void (*init)(struct dmub_srv *dmub);
422
423 void (*reset)(struct dmub_srv *dmub);
424
425 void (*reset_release)(struct dmub_srv *dmub);
426
427 void (*backdoor_load)(struct dmub_srv *dmub,
428 const struct dmub_window *cw0,
429 const struct dmub_window *cw1);
430
431 void (*backdoor_load_zfb_mode)(struct dmub_srv *dmub,
432 const struct dmub_window *cw0,
433 const struct dmub_window *cw1);
434 void (*setup_windows)(struct dmub_srv *dmub,
435 const struct dmub_window *cw2,
436 const struct dmub_window *cw3,
437 const struct dmub_window *cw4,
438 const struct dmub_window *cw5,
439 const struct dmub_window *cw6,
440 const struct dmub_window *region6);
441
442 void (*setup_mailbox)(struct dmub_srv *dmub,
443 const struct dmub_region *inbox1);
444
445 uint32_t (*get_inbox1_wptr)(struct dmub_srv *dmub);
446
447 uint32_t (*get_inbox1_rptr)(struct dmub_srv *dmub);
448
449 void (*set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset);
450
451 void (*setup_out_mailbox)(struct dmub_srv *dmub,
452 const struct dmub_region *outbox1);
453
454 uint32_t (*get_outbox1_wptr)(struct dmub_srv *dmub);
455
456 void (*set_outbox1_rptr)(struct dmub_srv *dmub, uint32_t rptr_offset);
457
458 void (*setup_outbox0)(struct dmub_srv *dmub,
459 const struct dmub_region *outbox0);
460
461 uint32_t (*get_outbox0_wptr)(struct dmub_srv *dmub);
462
463 void (*set_outbox0_rptr)(struct dmub_srv *dmub, uint32_t rptr_offset);
464
465 uint32_t (*emul_get_inbox1_rptr)(struct dmub_srv *dmub);
466
467 uint32_t (*emul_get_inbox1_wptr)(struct dmub_srv *dmub);
468
469 void (*emul_set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset);
470
471 bool (*is_supported)(struct dmub_srv *dmub);
472
473 bool (*is_psrsu_supported)(struct dmub_srv *dmub);
474
475 bool (*is_hw_init)(struct dmub_srv *dmub);
476 bool (*is_hw_powered_up)(struct dmub_srv *dmub);
477
478 void (*enable_dmub_boot_options)(struct dmub_srv *dmub,
479 const struct dmub_srv_hw_params *params);
480
481 void (*skip_dmub_panel_power_sequence)(struct dmub_srv *dmub, bool skip);
482
483 union dmub_fw_boot_status (*get_fw_status)(struct dmub_srv *dmub);
484
485 union dmub_fw_boot_options (*get_fw_boot_option)(struct dmub_srv *dmub);
486
487 void (*set_gpint)(struct dmub_srv *dmub,
488 union dmub_gpint_data_register reg);
489
490 bool (*is_gpint_acked)(struct dmub_srv *dmub,
491 union dmub_gpint_data_register reg);
492
493 uint32_t (*get_gpint_response)(struct dmub_srv *dmub);
494
495 uint32_t (*get_gpint_dataout)(struct dmub_srv *dmub);
496
497 void (*configure_dmub_in_system_memory)(struct dmub_srv *dmub);
498 void (*clear_inbox0_ack_register)(struct dmub_srv *dmub);
499 uint32_t (*read_inbox0_ack_register)(struct dmub_srv *dmub);
500 void (*send_inbox0_cmd)(struct dmub_srv *dmub, union dmub_inbox0_data_register data);
501 uint32_t (*get_current_time)(struct dmub_srv *dmub);
502
503 void (*get_diagnostic_data)(struct dmub_srv *dmub);
504 bool (*get_preos_fw_info)(struct dmub_srv *dmub);
505
506 bool (*should_detect)(struct dmub_srv *dmub);
507 void (*init_reg_offsets)(struct dmub_srv *dmub, struct dc_context *ctx);
508
509 void (*subvp_save_surf_addr)(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index);
510
511 void (*send_reg_inbox0_cmd_msg)(struct dmub_srv *dmub,
512 union dmub_rb_cmd *cmd);
513 uint32_t (*read_reg_inbox0_rsp_int_status)(struct dmub_srv *dmub);
514 void (*read_reg_inbox0_cmd_rsp)(struct dmub_srv *dmub,
515 union dmub_rb_cmd *cmd);
516 void (*write_reg_inbox0_rsp_int_ack)(struct dmub_srv *dmub);
517 void (*clear_reg_inbox0_rsp_int_ack)(struct dmub_srv *dmub);
518 void (*enable_reg_inbox0_rsp_int)(struct dmub_srv *dmub, bool enable);
519
520 uint32_t (*read_reg_outbox0_rdy_int_status)(struct dmub_srv *dmub);
521 void (*write_reg_outbox0_rdy_int_ack)(struct dmub_srv *dmub);
522 void (*read_reg_outbox0_msg)(struct dmub_srv *dmub, uint32_t *msg);
523 void (*write_reg_outbox0_rsp)(struct dmub_srv *dmub, uint32_t *rsp);
524 uint32_t (*read_reg_outbox0_rsp_int_status)(struct dmub_srv *dmub);
525 void (*enable_reg_outbox0_rdy_int)(struct dmub_srv *dmub, bool enable);
526};
527
528/**
529 * struct dmub_srv_create_params - params for dmub service creation
530 * @base_funcs: driver supplied base routines
531 * @hw_funcs: optional overrides for hw funcs
532 * @user_ctx: context data for callback funcs
533 * @asic: driver supplied asic
534 * @fw_version: the current firmware version, if any
535 * @is_virtual: false for hw support only
536 */
537struct dmub_srv_create_params {
538 struct dmub_srv_base_funcs funcs;
539 struct dmub_srv_hw_funcs *hw_funcs;
540 void *user_ctx;
541 enum dmub_asic asic;
542 uint32_t fw_version;
543 bool is_virtual;
544 enum dmub_inbox_cmd_interface_type inbox_type;
545};
546
547/**
548 * struct dmub_srv - software state for dmcub
549 * @asic: dmub asic identifier
550 * @user_ctx: user provided context for the dmub_srv
551 * @fw_version: the current firmware version, if any
552 * @is_virtual: false if hardware support only
553 * @shared_state: dmub shared state between firmware and driver
554 * @cursor_offload_v1: Cursor offload state
555 * @fw_state: dmub firmware state pointer (debug purpose only)
556 */
557struct dmub_srv {
558 enum dmub_asic asic;
559 void *user_ctx;
560 uint32_t fw_version;
561 bool is_virtual;
562 struct dmub_fb scratch_mem_fb;
563 struct dmub_fb ib_mem_gart;
564 struct dmub_fb cursor_offload_fb;
565 volatile struct dmub_shared_state_feature_block *shared_state;
566 volatile struct dmub_cursor_offload_v1 *cursor_offload_v1;
567 volatile const struct dmub_fw_state *fw_state;
568
569 /* private: internal use only */
570 const struct dmub_srv_common_regs *regs;
571 const struct dmub_srv_dcn31_regs *regs_dcn31;
572 struct dmub_srv_dcn32_regs *regs_dcn32;
573 struct dmub_srv_dcn35_regs *regs_dcn35;
574 const struct dmub_srv_dcn401_regs *regs_dcn401;
575 struct dmub_srv_base_funcs funcs;
576 struct dmub_srv_hw_funcs hw_funcs;
577 struct dmub_srv_inbox inbox1;
578 uint32_t inbox1_last_wptr;
579 struct dmub_srv_inbox reg_inbox0;
580 /**
581 * outbox1_rb is accessed without locks (dal & dc)
582 * and to be used only in dmub_srv_stat_get_notification()
583 */
584 struct dmub_rb outbox1_rb;
585
586 struct dmub_rb outbox0_rb;
587
588 bool sw_init;
589 bool hw_init;
590 bool dpia_supported;
591
592 uint64_t fb_base;
593 uint64_t fb_offset;
594 uint32_t psp_version;
595
596 /* Feature capabilities reported by fw */
597 struct dmub_fw_meta_info meta_info;
598 struct dmub_feature_caps feature_caps;
599 struct dmub_visual_confirm_color visual_confirm_color;
600 enum dmub_inbox_cmd_interface_type inbox_type;
601
602 enum dmub_srv_power_state_type power_state;
603 struct dmub_diagnostic_data debug;
604 struct dmub_fb lsdma_rb_fb;
605 struct dmub_preos_info preos_info;
606};
607
608/**
609 * struct dmub_notification - dmub notification data
610 * @type: dmub notification type
611 * @link_index: link index to identify aux connection
612 * @result: USB4 status returned from dmub
613 * @pending_notification: Indicates there are other pending notifications
614 * @aux_reply: aux reply
615 * @hpd_status: hpd status
616 * @bw_alloc_reply: BW Allocation reply from CM/DPIA
617 */
618struct dmub_notification {
619 enum dmub_notification_type type;
620 uint8_t link_index;
621 uint8_t result;
622 /* notify instance from DMUB */
623 uint8_t instance;
624 bool pending_notification;
625 union {
626 struct aux_reply_data aux_reply;
627 enum dp_hpd_status hpd_status;
628 enum set_config_status sc_status;
629 struct dmub_rb_cmd_hpd_sense_notify_data hpd_sense_notify;
630 struct dmub_cmd_fused_request fused_request;
631 };
632};
633
634/**
635 * DMUB firmware version helper macro - useful for checking if the version
636 * of a firmware to know if feature or functionality is supported or present.
637 */
638#define DMUB_FW_VERSION(major, minor, revision) \
639 ((((major) & 0xFF) << 24) | (((minor) & 0xFF) << 16) | (((revision) & 0xFF) << 8))
640
641/**
642 * dmub_srv_create() - creates the DMUB service.
643 * @dmub: the dmub service
644 * @params: creation parameters for the service
645 *
646 * Return:
647 * DMUB_STATUS_OK - success
648 * DMUB_STATUS_INVALID - unspecified error
649 */
650enum dmub_status dmub_srv_create(struct dmub_srv *dmub,
651 const struct dmub_srv_create_params *params);
652
653/**
654 * dmub_srv_destroy() - destroys the DMUB service.
655 * @dmub: the dmub service
656 */
657void dmub_srv_destroy(struct dmub_srv *dmub);
658
659/**
660 * dmub_srv_calc_region_info() - retreives region info from the dmub service
661 * @dmub: the dmub service
662 * @params: parameters used to calculate region locations
663 * @info_out: the output region info from dmub
664 *
665 * Calculates the base and top address for all relevant dmub regions
666 * using the parameters given (if any).
667 *
668 * Return:
669 * DMUB_STATUS_OK - success
670 * DMUB_STATUS_INVALID - unspecified error
671 */
672enum dmub_status
673dmub_srv_calc_region_info(struct dmub_srv *dmub,
674 const struct dmub_srv_region_params *params,
675 struct dmub_srv_region_info *out);
676
677/**
678 * dmub_srv_calc_region_info() - retreives fb info from the dmub service
679 * @dmub: the dmub service
680 * @params: parameters used to calculate fb locations
681 * @info_out: the output fb info from dmub
682 *
683 * Calculates the base and top address for all relevant dmub regions
684 * using the parameters given (if any).
685 *
686 * Return:
687 * DMUB_STATUS_OK - success
688 * DMUB_STATUS_INVALID - unspecified error
689 */
690enum dmub_status dmub_srv_calc_mem_info(struct dmub_srv *dmub,
691 const struct dmub_srv_memory_params *params,
692 struct dmub_srv_fb_info *out);
693
694/**
695 * dmub_srv_has_hw_support() - returns hw support state for dmcub
696 * @dmub: the dmub service
697 * @is_supported: hw support state
698 *
699 * Queries the hardware for DMCUB support and returns the result.
700 *
701 * Can be called before dmub_srv_hw_init().
702 *
703 * Return:
704 * DMUB_STATUS_OK - success
705 * DMUB_STATUS_INVALID - unspecified error
706 */
707enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub,
708 bool *is_supported);
709
710/**
711 * dmub_srv_is_hw_init() - returns hardware init state
712 *
713 * Return:
714 * DMUB_STATUS_OK - success
715 * DMUB_STATUS_INVALID - unspecified error
716 */
717enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init);
718
719/**
720 * dmub_srv_hw_init() - initializes the underlying DMUB hardware
721 * @dmub: the dmub service
722 * @params: params for hardware initialization
723 *
724 * Resets the DMUB hardware and performs backdoor loading of the
725 * required cache regions based on the input framebuffer regions.
726 *
727 * Return:
728 * DMUB_STATUS_OK - success
729 * DMUB_STATUS_NO_CTX - dmcub context not initialized
730 * DMUB_STATUS_INVALID - unspecified error
731 */
732enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
733 const struct dmub_srv_hw_params *params);
734
735/**
736 * dmub_srv_hw_reset() - puts the DMUB hardware in reset state if initialized
737 * @dmub: the dmub service
738 *
739 * Before destroying the DMUB service or releasing the backing framebuffer
740 * memory we'll need to put the DMCUB into reset first.
741 *
742 * A subsequent call to dmub_srv_hw_init() will re-enable the DMCUB.
743 *
744 * Return:
745 * DMUB_STATUS_OK - success
746 * DMUB_STATUS_INVALID - unspecified error
747 */
748enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub);
749
750/**
751 * dmub_srv_fb_cmd_queue() - queues a command to the DMUB
752 * @dmub: the dmub service
753 * @cmd: the command to queue
754 *
755 * Queues a command to the DMUB service but does not begin execution
756 * immediately.
757 *
758 * Return:
759 * DMUB_STATUS_OK - success
760 * DMUB_STATUS_QUEUE_FULL - no remaining room in queue
761 * DMUB_STATUS_INVALID - unspecified error
762 */
763enum dmub_status dmub_srv_fb_cmd_queue(struct dmub_srv *dmub,
764 const union dmub_rb_cmd *cmd);
765
766/**
767 * dmub_srv_fb_cmd_execute() - Executes a queued sequence to the dmub
768 * @dmub: the dmub service
769 *
770 * Begins execution of queued commands on the dmub.
771 *
772 * Return:
773 * DMUB_STATUS_OK - success
774 * DMUB_STATUS_INVALID - unspecified error
775 */
776enum dmub_status dmub_srv_fb_cmd_execute(struct dmub_srv *dmub);
777
778/**
779 * dmub_srv_wait_for_hw_pwr_up() - Waits for firmware hardware power up is completed
780 * @dmub: the dmub service
781 * @timeout_us: the maximum number of microseconds to wait
782 *
783 * Waits until firmware hardware is powered up. The maximum
784 * wait time is given in microseconds to prevent spinning forever.
785 *
786 * Return:
787 * DMUB_STATUS_OK - success
788 * DMUB_STATUS_TIMEOUT - timed out
789 * DMUB_STATUS_INVALID - unspecified error
790 */
791enum dmub_status dmub_srv_wait_for_hw_pwr_up(struct dmub_srv *dmub,
792 uint32_t timeout_us);
793
794bool dmub_srv_is_hw_pwr_up(struct dmub_srv *dmub);
795
796/**
797 * dmub_srv_wait_for_auto_load() - Waits for firmware auto load to complete
798 * @dmub: the dmub service
799 * @timeout_us: the maximum number of microseconds to wait
800 *
801 * Waits until firmware has been autoloaded by the DMCUB. The maximum
802 * wait time is given in microseconds to prevent spinning forever.
803 *
804 * On ASICs without firmware autoload support this function will return
805 * immediately.
806 *
807 * Return:
808 * DMUB_STATUS_OK - success
809 * DMUB_STATUS_TIMEOUT - wait for phy init timed out
810 * DMUB_STATUS_INVALID - unspecified error
811 */
812enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,
813 uint32_t timeout_us);
814
815/**
816 * dmub_srv_wait_for_phy_init() - Waits for DMUB PHY init to complete
817 * @dmub: the dmub service
818 * @timeout_us: the maximum number of microseconds to wait
819 *
820 * Waits until the PHY has been initialized by the DMUB. The maximum
821 * wait time is given in microseconds to prevent spinning forever.
822 *
823 * On ASICs without PHY init support this function will return
824 * immediately.
825 *
826 * Return:
827 * DMUB_STATUS_OK - success
828 * DMUB_STATUS_TIMEOUT - wait for phy init timed out
829 * DMUB_STATUS_INVALID - unspecified error
830 */
831enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub,
832 uint32_t timeout_us);
833
834/**
835 * dmub_srv_wait_for_pending() - Re-entrant wait for messages currently pending
836 * @dmub: the dmub service
837 * @timeout_us: the maximum number of microseconds to wait
838 *
839 * Waits until the commands queued prior to this call are complete.
840 * If interfaces remain busy due to additional work being submitted
841 * concurrently, this function will not continue to wait.
842 *
843 * Return:
844 * DMUB_STATUS_OK - success
845 * DMUB_STATUS_TIMEOUT - wait for buffer to flush timed out
846 * DMUB_STATUS_INVALID - unspecified error
847 */
848enum dmub_status dmub_srv_wait_for_pending(struct dmub_srv *dmub,
849 uint32_t timeout_us);
850
851/**
852 * dmub_srv_wait_for_idle() - Waits for the DMUB to be idle
853 * @dmub: the dmub service
854 * @timeout_us: the maximum number of microseconds to wait
855 *
856 * Waits until the DMUB buffer is empty and all commands have
857 * finished processing. The maximum wait time is given in
858 * microseconds to prevent spinning forever.
859 *
860 * Return:
861 * DMUB_STATUS_OK - success
862 * DMUB_STATUS_TIMEOUT - wait for buffer to flush timed out
863 * DMUB_STATUS_INVALID - unspecified error
864 */
865enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,
866 uint32_t timeout_us);
867
868/**
869 * dmub_srv_send_gpint_command() - Sends a GPINT based command.
870 * @dmub: the dmub service
871 * @command_code: the command code to send
872 * @param: the command parameter to send
873 * @timeout_us: the maximum number of microseconds to wait
874 *
875 * Sends a command via the general purpose interrupt (GPINT).
876 * Waits for the number of microseconds specified by timeout_us
877 * for the command ACK before returning.
878 *
879 * Can be called after software initialization.
880 *
881 * Return:
882 * DMUB_STATUS_OK - success
883 * DMUB_STATUS_TIMEOUT - wait for ACK timed out
884 * DMUB_STATUS_INVALID - unspecified error
885 */
886enum dmub_status
887dmub_srv_send_gpint_command(struct dmub_srv *dmub,
888 enum dmub_gpint_command command_code,
889 uint16_t param, uint32_t timeout_us);
890
891/**
892 * dmub_srv_get_gpint_response() - Queries the GPINT response.
893 * @dmub: the dmub service
894 * @response: the response for the last GPINT
895 *
896 * Returns the response code for the last GPINT interrupt.
897 *
898 * Can be called after software initialization.
899 *
900 * Return:
901 * DMUB_STATUS_OK - success
902 * DMUB_STATUS_INVALID - unspecified error
903 */
904enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub,
905 uint32_t *response);
906
907/**
908 * dmub_srv_get_gpint_dataout() - Queries the GPINT DATAOUT.
909 * @dmub: the dmub service
910 * @dataout: the data for the GPINT DATAOUT
911 *
912 * Returns the response code for the last GPINT DATAOUT interrupt.
913 *
914 * Can be called after software initialization.
915 *
916 * Return:
917 * DMUB_STATUS_OK - success
918 * DMUB_STATUS_INVALID - unspecified error
919 */
920enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub,
921 uint32_t *dataout);
922
923/**
924 * dmub_flush_buffer_mem() - Read back entire frame buffer region.
925 * This ensures that the write from x86 has been flushed and will not
926 * hang the DMCUB.
927 * @fb: frame buffer to flush
928 *
929 * Can be called after software initialization.
930 */
931void dmub_flush_buffer_mem(const struct dmub_fb *fb);
932
933/**
934 * dmub_srv_get_fw_boot_status() - Returns the DMUB boot status bits.
935 *
936 * @dmub: the dmub service
937 * @status: out pointer for firmware status
938 *
939 * Return:
940 * DMUB_STATUS_OK - success
941 * DMUB_STATUS_INVALID - unspecified error, unsupported
942 */
943enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub,
944 union dmub_fw_boot_status *status);
945
946enum dmub_status dmub_srv_get_fw_boot_option(struct dmub_srv *dmub,
947 union dmub_fw_boot_options *option);
948
949enum dmub_status dmub_srv_set_skip_panel_power_sequence(struct dmub_srv *dmub,
950 bool skip);
951
952bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry);
953
954bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub);
955
956bool dmub_srv_should_detect(struct dmub_srv *dmub);
957
958/**
959 * dmub_srv_send_inbox0_cmd() - Send command to DMUB using INBOX0
960 * @dmub: the dmub service
961 * @data: the data to be sent in the INBOX0 command
962 *
963 * Send command by writing directly to INBOX0 WPTR
964 *
965 * Return:
966 * DMUB_STATUS_OK - success
967 * DMUB_STATUS_INVALID - hw_init false or hw function does not exist
968 */
969enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data);
970
971/**
972 * dmub_srv_wait_for_inbox0_ack() - wait for DMUB to ACK INBOX0 command
973 * @dmub: the dmub service
974 * @timeout_us: the maximum number of microseconds to wait
975 *
976 * Wait for DMUB to ACK the INBOX0 message
977 *
978 * Return:
979 * DMUB_STATUS_OK - success
980 * DMUB_STATUS_INVALID - hw_init false or hw function does not exist
981 * DMUB_STATUS_TIMEOUT - wait for ack timed out
982 */
983enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us);
984
985/**
986 * dmub_srv_wait_for_inbox0_ack() - clear ACK register for INBOX0
987 * @dmub: the dmub service
988 *
989 * Clear ACK register for INBOX0
990 *
991 * Return:
992 * DMUB_STATUS_OK - success
993 * DMUB_STATUS_INVALID - hw_init false or hw function does not exist
994 */
995enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub);
996
997/**
998 * dmub_srv_subvp_save_surf_addr() - Save primary and meta address for subvp on each flip
999 * @dmub: The dmub service
1000 * @addr: The surface address to be programmed on the current flip
1001 * @subvp_index: Index of subvp pipe, indicates which subvp pipe the address should be saved for
1002 *
1003 * Function to save the surface flip addr into scratch registers. This is to fix a race condition
1004 * between FW and driver reading / writing to the surface address at the same time. This is
1005 * required because there is no EARLIEST_IN_USE_META.
1006 *
1007 * Return:
1008 * void
1009 */
1010void dmub_srv_subvp_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index);
1011
1012/**
1013 * dmub_srv_set_power_state() - Track DC power state in dmub_srv
1014 * @dmub: The dmub service
1015 * @power_state: DC power state setting
1016 *
1017 * Store DC power state in dmub_srv. If dmub_srv is in D3, then don't send messages to DMUB
1018 *
1019 * Return:
1020 * void
1021 */
1022void dmub_srv_set_power_state(struct dmub_srv *dmub, enum dmub_srv_power_state_type dmub_srv_power_state);
1023
1024/**
1025 * dmub_srv_reg_cmd_execute() - Executes provided command to the dmub
1026 * @dmub: the dmub service
1027 * @cmd: the command packet to be executed
1028 *
1029 * Executes a single command for the dmub.
1030 *
1031 * Return:
1032 * DMUB_STATUS_OK - success
1033 * DMUB_STATUS_INVALID - unspecified error
1034 */
1035enum dmub_status dmub_srv_reg_cmd_execute(struct dmub_srv *dmub, union dmub_rb_cmd *cmd);
1036
1037
1038/**
1039 * dmub_srv_cmd_get_response() - Copies return data for command into buffer
1040 * @dmub: the dmub service
1041 * @cmd_rsp: response buffer
1042 *
1043 * Copies return data for command into buffer
1044 */
1045void dmub_srv_cmd_get_response(struct dmub_srv *dmub,
1046 union dmub_rb_cmd *cmd_rsp);
1047
1048/**
1049 * dmub_srv_sync_inboxes() - Sync inbox state
1050 * @dmub: the dmub service
1051 *
1052 * Sync inbox state
1053 *
1054 * Return:
1055 * DMUB_STATUS_OK - success
1056 * DMUB_STATUS_INVALID - unspecified error
1057 */
1058enum dmub_status dmub_srv_sync_inboxes(struct dmub_srv *dmub);
1059
1060/**
1061 * dmub_srv_wait_for_inbox_free() - Waits for space in the DMUB inbox to free up
1062 * @dmub: the dmub service
1063 * @timeout_us: the maximum number of microseconds to wait
1064 * @num_free_required: number of free entries required
1065 *
1066 * Waits until the DMUB buffer is freed to the specified number.
1067 * The maximum wait time is given in microseconds to prevent spinning
1068 * forever.
1069 *
1070 * Return:
1071 * DMUB_STATUS_OK - success
1072 * DMUB_STATUS_TIMEOUT - wait for buffer to flush timed out
1073 * DMUB_STATUS_INVALID - unspecified error
1074 */
1075enum dmub_status dmub_srv_wait_for_inbox_free(struct dmub_srv *dmub,
1076 uint32_t timeout_us,
1077 uint32_t num_free_required);
1078
1079/**
1080 * dmub_srv_update_inbox_status() - Updates pending status for inbox & reg inbox0
1081 * @dmub: the dmub service
1082 *
1083 * Return:
1084 * DMUB_STATUS_OK - success
1085 * DMUB_STATUS_TIMEOUT - wait for buffer to flush timed out
1086 * DMUB_STATUS_HW_FAILURE - issue with HW programming
1087 * DMUB_STATUS_INVALID - unspecified error
1088 */
1089enum dmub_status dmub_srv_update_inbox_status(struct dmub_srv *dmub);
1090
1091/**
1092 * dmub_srv_get_preos_info() - retrieves preos fw info
1093 * @dmub: the dmub service
1094 *
1095 * Return:
1096 * true - preos fw info retrieved successfully
1097 * false - preos fw info not retrieved successfully
1098 */
1099bool dmub_srv_get_preos_info(struct dmub_srv *dmub);
1100
1101#endif /* _DMUB_SRV_H_ */
1102

source code of linux/drivers/gpu/drm/amd/display/dmub/dmub_srv.h