1// SPDX-License-Identifier: MIT
2//
3// Copyright 2024 Advanced Micro Devices, Inc.
4
5#ifndef __DC_SPL_TYPES_H__
6#define __DC_SPL_TYPES_H__
7
8#include "spl_debug.h"
9#include "spl_os_types.h" // swap
10#include "spl_fixpt31_32.h" // fixed31_32 and related functions
11#include "spl_custom_float.h" // custom float and related functions
12
13struct spl_size {
14 uint32_t width;
15 uint32_t height;
16};
17struct spl_rect {
18 int x;
19 int y;
20 int width;
21 int height;
22};
23
24struct spl_ratios {
25 struct spl_fixed31_32 horz;
26 struct spl_fixed31_32 vert;
27 struct spl_fixed31_32 horz_c;
28 struct spl_fixed31_32 vert_c;
29};
30struct spl_inits {
31 struct spl_fixed31_32 h;
32 struct spl_fixed31_32 h_c;
33 struct spl_fixed31_32 v;
34 struct spl_fixed31_32 v_c;
35};
36
37struct spl_taps {
38 uint32_t v_taps;
39 uint32_t h_taps;
40 uint32_t v_taps_c;
41 uint32_t h_taps_c;
42 bool integer_scaling;
43};
44enum spl_view_3d {
45 SPL_VIEW_3D_NONE = 0,
46 SPL_VIEW_3D_FRAME_SEQUENTIAL,
47 SPL_VIEW_3D_SIDE_BY_SIDE,
48 SPL_VIEW_3D_TOP_AND_BOTTOM,
49 SPL_VIEW_3D_COUNT,
50 SPL_VIEW_3D_FIRST = SPL_VIEW_3D_FRAME_SEQUENTIAL
51};
52/* Pixel format */
53enum spl_pixel_format {
54 /*graph*/
55 SPL_PIXEL_FORMAT_UNINITIALIZED,
56 SPL_PIXEL_FORMAT_INDEX8,
57 SPL_PIXEL_FORMAT_RGB565,
58 SPL_PIXEL_FORMAT_ARGB8888,
59 SPL_PIXEL_FORMAT_ARGB2101010,
60 SPL_PIXEL_FORMAT_ARGB2101010_XRBIAS,
61 SPL_PIXEL_FORMAT_FP16,
62 /*video*/
63 SPL_PIXEL_FORMAT_420BPP8,
64 SPL_PIXEL_FORMAT_420BPP10,
65 /*end of pixel format definition*/
66 SPL_PIXEL_FORMAT_GRPH_BEGIN = SPL_PIXEL_FORMAT_INDEX8,
67 SPL_PIXEL_FORMAT_GRPH_END = SPL_PIXEL_FORMAT_FP16,
68 SPL_PIXEL_FORMAT_SUBSAMPLED_BEGIN = SPL_PIXEL_FORMAT_420BPP8,
69 SPL_PIXEL_FORMAT_SUBSAMPLED_END = SPL_PIXEL_FORMAT_420BPP10,
70 SPL_PIXEL_FORMAT_VIDEO_BEGIN = SPL_PIXEL_FORMAT_420BPP8,
71 SPL_PIXEL_FORMAT_VIDEO_END = SPL_PIXEL_FORMAT_420BPP10,
72 SPL_PIXEL_FORMAT_INVALID,
73 SPL_PIXEL_FORMAT_UNKNOWN
74};
75
76enum lb_memory_config {
77 /* Enable all 3 pieces of memory */
78 LB_MEMORY_CONFIG_0 = 0,
79
80 /* Enable only the first piece of memory */
81 LB_MEMORY_CONFIG_1 = 1,
82
83 /* Enable only the second piece of memory */
84 LB_MEMORY_CONFIG_2 = 2,
85
86 /* Only applicable in 4:2:0 mode, enable all 3 pieces of memory and the
87 * last piece of chroma memory used for the luma storage
88 */
89 LB_MEMORY_CONFIG_3 = 3
90};
91
92/* Rotation angle */
93enum spl_rotation_angle {
94 SPL_ROTATION_ANGLE_0 = 0,
95 SPL_ROTATION_ANGLE_90,
96 SPL_ROTATION_ANGLE_180,
97 SPL_ROTATION_ANGLE_270,
98 SPL_ROTATION_ANGLE_COUNT
99};
100enum spl_color_space {
101 SPL_COLOR_SPACE_UNKNOWN,
102 SPL_COLOR_SPACE_SRGB,
103 SPL_COLOR_SPACE_XR_RGB,
104 SPL_COLOR_SPACE_SRGB_LIMITED,
105 SPL_COLOR_SPACE_MSREF_SCRGB,
106 SPL_COLOR_SPACE_YCBCR601,
107 SPL_COLOR_SPACE_YCBCR709,
108 SPL_COLOR_SPACE_XV_YCC_709,
109 SPL_COLOR_SPACE_XV_YCC_601,
110 SPL_COLOR_SPACE_YCBCR601_LIMITED,
111 SPL_COLOR_SPACE_YCBCR709_LIMITED,
112 SPL_COLOR_SPACE_2020_RGB_FULLRANGE,
113 SPL_COLOR_SPACE_2020_RGB_LIMITEDRANGE,
114 SPL_COLOR_SPACE_2020_YCBCR,
115 SPL_COLOR_SPACE_ADOBERGB,
116 SPL_COLOR_SPACE_DCIP3,
117 SPL_COLOR_SPACE_DISPLAYNATIVE,
118 SPL_COLOR_SPACE_DOLBYVISION,
119 SPL_COLOR_SPACE_APPCTRL,
120 SPL_COLOR_SPACE_CUSTOMPOINTS,
121 SPL_COLOR_SPACE_YCBCR709_BLACK,
122};
123
124enum chroma_cositing {
125 CHROMA_COSITING_NONE,
126 CHROMA_COSITING_LEFT,
127 CHROMA_COSITING_TOPLEFT,
128 CHROMA_COSITING_COUNT
129};
130
131// Scratch space for calculating scaler params
132struct spl_scaler_data {
133 int h_active;
134 int v_active;
135 struct spl_taps taps;
136 struct spl_rect viewport;
137 struct spl_rect viewport_c;
138 struct spl_rect recout;
139 struct spl_ratios ratios;
140 struct spl_ratios recip_ratios;
141 struct spl_inits inits;
142};
143
144enum spl_transfer_func_type {
145 SPL_TF_TYPE_PREDEFINED,
146 SPL_TF_TYPE_DISTRIBUTED_POINTS,
147 SPL_TF_TYPE_BYPASS,
148 SPL_TF_TYPE_HWPWL
149};
150
151enum spl_transfer_func_predefined {
152 SPL_TRANSFER_FUNCTION_SRGB,
153 SPL_TRANSFER_FUNCTION_BT709,
154 SPL_TRANSFER_FUNCTION_PQ,
155 SPL_TRANSFER_FUNCTION_LINEAR,
156 SPL_TRANSFER_FUNCTION_UNITY,
157 SPL_TRANSFER_FUNCTION_HLG,
158 SPL_TRANSFER_FUNCTION_HLG12,
159 SPL_TRANSFER_FUNCTION_GAMMA22,
160 SPL_TRANSFER_FUNCTION_GAMMA24,
161 SPL_TRANSFER_FUNCTION_GAMMA26
162};
163
164/*==============================================================*/
165/* Below structs are defined to hold hw register data */
166
167// SPL output is used to set below registers
168
169// MPC_SIZE - set based on scl_data h_active and v_active
170struct mpc_size {
171 uint32_t width;
172 uint32_t height;
173};
174// SCL_MODE - set based on scl_data.ratios and always_scale
175enum scl_mode {
176 SCL_MODE_SCALING_444_BYPASS = 0,
177 SCL_MODE_SCALING_444_RGB_ENABLE = 1,
178 SCL_MODE_SCALING_444_YCBCR_ENABLE = 2,
179 SCL_MODE_SCALING_420_YCBCR_ENABLE = 3,
180 SCL_MODE_SCALING_420_LUMA_BYPASS = 4,
181 SCL_MODE_SCALING_420_CHROMA_BYPASS = 5,
182 SCL_MODE_DSCL_BYPASS = 6
183};
184// SCL_BLACK_COLOR - set based on scl_data.format
185struct scl_black_color {
186 uint32_t offset_rgb_y;
187 uint32_t offset_rgb_cbcr;
188};
189// RATIO - set based on scl_data.ratios
190struct ratio {
191 uint32_t h_scale_ratio;
192 uint32_t v_scale_ratio;
193 uint32_t h_scale_ratio_c;
194 uint32_t v_scale_ratio_c;
195};
196
197// INIT - set based on scl_data.init
198struct init {
199 // SCL_HORZ_FILTER_INIT
200 uint32_t h_filter_init_frac; // SCL_H_INIT_FRAC
201 uint32_t h_filter_init_int; // SCL_H_INIT_INT
202 // SCL_HORZ_FILTER_INIT_C
203 uint32_t h_filter_init_frac_c; // SCL_H_INIT_FRAC_C
204 uint32_t h_filter_init_int_c; // SCL_H_INIT_INT_C
205 // SCL_VERT_FILTER_INIT
206 uint32_t v_filter_init_frac; // SCL_V_INIT_FRAC
207 uint32_t v_filter_init_int; // SCL_V_INIT_INT
208 // SCL_VERT_FILTER_INIT_C
209 uint32_t v_filter_init_frac_c; // SCL_V_INIT_FRAC_C
210 uint32_t v_filter_init_int_c; // SCL_V_INIT_INT_C
211 // SCL_VERT_FILTER_INIT_BOT
212 uint32_t v_filter_init_bot_frac; // SCL_V_INIT_FRAC_BOT
213 uint32_t v_filter_init_bot_int; // SCL_V_INIT_INT_BOT
214 // SCL_VERT_FILTER_INIT_BOT_C
215 uint32_t v_filter_init_bot_frac_c; // SCL_V_INIT_FRAC_BOT_C
216 uint32_t v_filter_init_bot_int_c; // SCL_V_INIT_INT_BOT_C
217};
218
219// FILTER - calculated based on scl_data ratios and taps
220
221// iSHARP
222struct isharp_noise_det {
223 uint32_t enable; // ISHARP_NOISEDET_EN
224 uint32_t mode; // ISHARP_NOISEDET_MODE
225 uint32_t uthreshold; // ISHARP_NOISEDET_UTHRE
226 uint32_t dthreshold; // ISHARP_NOISEDET_DTHRE
227 uint32_t pwl_start_in; // ISHARP_NOISEDET_PWL_START_IN
228 uint32_t pwl_end_in; // ISHARP_NOISEDET_PWL_END_IN
229 uint32_t pwl_slope; // ISHARP_NOISEDET_PWL_SLOPE
230};
231struct isharp_lba {
232 uint32_t mode; // ISHARP_LBA_MODE
233 uint32_t in_seg[6];
234 uint32_t base_seg[6];
235 uint32_t slope_seg[6];
236};
237struct isharp_fmt {
238 uint32_t mode; // ISHARP_FMT_MODE
239 uint32_t norm; // ISHARP_FMT_NORM
240};
241struct isharp_nldelta_sclip {
242 uint32_t enable_p; // ISHARP_NLDELTA_SCLIP_EN_P
243 uint32_t pivot_p; // ISHARP_NLDELTA_SCLIP_PIVOT_P
244 uint32_t slope_p; // ISHARP_NLDELTA_SCLIP_SLOPE_P
245 uint32_t enable_n; // ISHARP_NLDELTA_SCLIP_EN_N
246 uint32_t pivot_n; // ISHARP_NLDELTA_SCLIP_PIVOT_N
247 uint32_t slope_n; // ISHARP_NLDELTA_SCLIP_SLOPE_N
248};
249enum isharp_en {
250 ISHARP_DISABLE,
251 ISHARP_ENABLE
252};
253#define ISHARP_LUT_TABLE_SIZE 32
254// Below struct holds values that can be directly used to program
255// hardware registers. No conversion/clamping is required
256struct dscl_prog_data {
257 struct spl_rect recout; // RECOUT - set based on scl_data.recout
258 struct mpc_size mpc_size;
259 uint32_t dscl_mode;
260 struct scl_black_color scl_black_color;
261 struct ratio ratios;
262 struct init init;
263 struct spl_taps taps; // TAPS - set based on scl_data.taps
264 struct spl_rect viewport;
265 struct spl_rect viewport_c;
266 // raw filter
267 const uint16_t *filter_h;
268 const uint16_t *filter_v;
269 const uint16_t *filter_h_c;
270 const uint16_t *filter_v_c;
271 // EASF registers
272 uint32_t easf_matrix_mode;
273 uint32_t easf_ltonl_en;
274 uint32_t easf_v_en;
275 uint32_t easf_v_sharp_factor;
276 uint32_t easf_v_ring;
277 uint32_t easf_v_bf1_en;
278 uint32_t easf_v_bf2_mode;
279 uint32_t easf_v_bf3_mode;
280 uint32_t easf_v_bf2_flat1_gain;
281 uint32_t easf_v_bf2_flat2_gain;
282 uint32_t easf_v_bf2_roc_gain;
283 uint32_t easf_v_ringest_3tap_dntilt_uptilt;
284 uint32_t easf_v_ringest_3tap_uptilt_max;
285 uint32_t easf_v_ringest_3tap_dntilt_slope;
286 uint32_t easf_v_ringest_3tap_uptilt1_slope;
287 uint32_t easf_v_ringest_3tap_uptilt2_slope;
288 uint32_t easf_v_ringest_3tap_uptilt2_offset;
289 uint32_t easf_v_ringest_eventap_reduceg1;
290 uint32_t easf_v_ringest_eventap_reduceg2;
291 uint32_t easf_v_ringest_eventap_gain1;
292 uint32_t easf_v_ringest_eventap_gain2;
293 uint32_t easf_v_bf_maxa;
294 uint32_t easf_v_bf_maxb;
295 uint32_t easf_v_bf_mina;
296 uint32_t easf_v_bf_minb;
297 uint32_t easf_v_bf1_pwl_in_seg0;
298 uint32_t easf_v_bf1_pwl_base_seg0;
299 uint32_t easf_v_bf1_pwl_slope_seg0;
300 uint32_t easf_v_bf1_pwl_in_seg1;
301 uint32_t easf_v_bf1_pwl_base_seg1;
302 uint32_t easf_v_bf1_pwl_slope_seg1;
303 uint32_t easf_v_bf1_pwl_in_seg2;
304 uint32_t easf_v_bf1_pwl_base_seg2;
305 uint32_t easf_v_bf1_pwl_slope_seg2;
306 uint32_t easf_v_bf1_pwl_in_seg3;
307 uint32_t easf_v_bf1_pwl_base_seg3;
308 uint32_t easf_v_bf1_pwl_slope_seg3;
309 uint32_t easf_v_bf1_pwl_in_seg4;
310 uint32_t easf_v_bf1_pwl_base_seg4;
311 uint32_t easf_v_bf1_pwl_slope_seg4;
312 uint32_t easf_v_bf1_pwl_in_seg5;
313 uint32_t easf_v_bf1_pwl_base_seg5;
314 uint32_t easf_v_bf1_pwl_slope_seg5;
315 uint32_t easf_v_bf1_pwl_in_seg6;
316 uint32_t easf_v_bf1_pwl_base_seg6;
317 uint32_t easf_v_bf1_pwl_slope_seg6;
318 uint32_t easf_v_bf1_pwl_in_seg7;
319 uint32_t easf_v_bf1_pwl_base_seg7;
320 uint32_t easf_v_bf3_pwl_in_set0;
321 uint32_t easf_v_bf3_pwl_base_set0;
322 uint32_t easf_v_bf3_pwl_slope_set0;
323 uint32_t easf_v_bf3_pwl_in_set1;
324 uint32_t easf_v_bf3_pwl_base_set1;
325 uint32_t easf_v_bf3_pwl_slope_set1;
326 uint32_t easf_v_bf3_pwl_in_set2;
327 uint32_t easf_v_bf3_pwl_base_set2;
328 uint32_t easf_v_bf3_pwl_slope_set2;
329 uint32_t easf_v_bf3_pwl_in_set3;
330 uint32_t easf_v_bf3_pwl_base_set3;
331 uint32_t easf_v_bf3_pwl_slope_set3;
332 uint32_t easf_v_bf3_pwl_in_set4;
333 uint32_t easf_v_bf3_pwl_base_set4;
334 uint32_t easf_v_bf3_pwl_slope_set4;
335 uint32_t easf_v_bf3_pwl_in_set5;
336 uint32_t easf_v_bf3_pwl_base_set5;
337 uint32_t easf_h_en;
338 uint32_t easf_h_sharp_factor;
339 uint32_t easf_h_ring;
340 uint32_t easf_h_bf1_en;
341 uint32_t easf_h_bf2_mode;
342 uint32_t easf_h_bf3_mode;
343 uint32_t easf_h_bf2_flat1_gain;
344 uint32_t easf_h_bf2_flat2_gain;
345 uint32_t easf_h_bf2_roc_gain;
346 uint32_t easf_h_ringest_eventap_reduceg1;
347 uint32_t easf_h_ringest_eventap_reduceg2;
348 uint32_t easf_h_ringest_eventap_gain1;
349 uint32_t easf_h_ringest_eventap_gain2;
350 uint32_t easf_h_bf_maxa;
351 uint32_t easf_h_bf_maxb;
352 uint32_t easf_h_bf_mina;
353 uint32_t easf_h_bf_minb;
354 uint32_t easf_h_bf1_pwl_in_seg0;
355 uint32_t easf_h_bf1_pwl_base_seg0;
356 uint32_t easf_h_bf1_pwl_slope_seg0;
357 uint32_t easf_h_bf1_pwl_in_seg1;
358 uint32_t easf_h_bf1_pwl_base_seg1;
359 uint32_t easf_h_bf1_pwl_slope_seg1;
360 uint32_t easf_h_bf1_pwl_in_seg2;
361 uint32_t easf_h_bf1_pwl_base_seg2;
362 uint32_t easf_h_bf1_pwl_slope_seg2;
363 uint32_t easf_h_bf1_pwl_in_seg3;
364 uint32_t easf_h_bf1_pwl_base_seg3;
365 uint32_t easf_h_bf1_pwl_slope_seg3;
366 uint32_t easf_h_bf1_pwl_in_seg4;
367 uint32_t easf_h_bf1_pwl_base_seg4;
368 uint32_t easf_h_bf1_pwl_slope_seg4;
369 uint32_t easf_h_bf1_pwl_in_seg5;
370 uint32_t easf_h_bf1_pwl_base_seg5;
371 uint32_t easf_h_bf1_pwl_slope_seg5;
372 uint32_t easf_h_bf1_pwl_in_seg6;
373 uint32_t easf_h_bf1_pwl_base_seg6;
374 uint32_t easf_h_bf1_pwl_slope_seg6;
375 uint32_t easf_h_bf1_pwl_in_seg7;
376 uint32_t easf_h_bf1_pwl_base_seg7;
377 uint32_t easf_h_bf3_pwl_in_set0;
378 uint32_t easf_h_bf3_pwl_base_set0;
379 uint32_t easf_h_bf3_pwl_slope_set0;
380 uint32_t easf_h_bf3_pwl_in_set1;
381 uint32_t easf_h_bf3_pwl_base_set1;
382 uint32_t easf_h_bf3_pwl_slope_set1;
383 uint32_t easf_h_bf3_pwl_in_set2;
384 uint32_t easf_h_bf3_pwl_base_set2;
385 uint32_t easf_h_bf3_pwl_slope_set2;
386 uint32_t easf_h_bf3_pwl_in_set3;
387 uint32_t easf_h_bf3_pwl_base_set3;
388 uint32_t easf_h_bf3_pwl_slope_set3;
389 uint32_t easf_h_bf3_pwl_in_set4;
390 uint32_t easf_h_bf3_pwl_base_set4;
391 uint32_t easf_h_bf3_pwl_slope_set4;
392 uint32_t easf_h_bf3_pwl_in_set5;
393 uint32_t easf_h_bf3_pwl_base_set5;
394 uint32_t easf_matrix_c0;
395 uint32_t easf_matrix_c1;
396 uint32_t easf_matrix_c2;
397 uint32_t easf_matrix_c3;
398 // iSharp
399 uint32_t isharp_en; // ISHARP_EN
400 struct isharp_noise_det isharp_noise_det; // ISHARP_NOISEDET
401 uint32_t isharp_nl_en; // ISHARP_NL_EN ? TODO:check this
402 struct isharp_lba isharp_lba; // ISHARP_LBA
403 struct isharp_fmt isharp_fmt; // ISHARP_FMT
404 uint32_t isharp_delta[ISHARP_LUT_TABLE_SIZE];
405 struct isharp_nldelta_sclip isharp_nldelta_sclip; // ISHARP_NLDELTA_SCLIP
406 /* blur and scale filter */
407 const uint16_t *filter_blur_scale_v;
408 const uint16_t *filter_blur_scale_h;
409 int sharpness_level; /* Track sharpness level */
410};
411
412/* SPL input and output definitions */
413// SPL scratch struct
414struct spl_scratch {
415 // Pack all SPL outputs in scl_data
416 struct spl_scaler_data scl_data;
417};
418
419/* SPL input and output definitions */
420// SPL outputs struct
421struct spl_out {
422 // Pack all output need to program hw registers
423 struct dscl_prog_data *dscl_prog_data;
424};
425
426// end of SPL outputs
427
428// SPL inputs
429
430// opp extra adjustment for rect
431struct spl_opp_adjust {
432 int x;
433 int y;
434 int width;
435 int height;
436};
437
438// Basic input information
439struct basic_in {
440 enum spl_pixel_format format; // Pixel Format
441 enum chroma_cositing cositing; /* Chroma Subsampling Offset */
442 struct spl_rect src_rect; // Source rect
443 struct spl_rect dst_rect; // Destination Rect
444 struct spl_rect clip_rect; // Clip rect
445 enum spl_rotation_angle rotation; // Rotation
446 bool horizontal_mirror; // Horizontal mirror
447 struct { // previous mpc_combine_h - split count
448 bool use_recout_width_aligned;
449 union {
450 int mpc_num_h_slices;
451 int mpc_recout_width_align;
452 } num_slices_recout_width;
453 } num_h_slices_recout_width_align;
454 int mpc_h_slice_index; // previous mpc_combine_v - split_idx
455 struct spl_opp_adjust opp_recout_adjust;
456 // Inputs for adaptive scaler - TODO
457 enum spl_transfer_func_type tf_type; /* Transfer function type */
458 enum spl_transfer_func_predefined tf_predefined_type; /* Transfer function predefined type */
459 // enum dc_transfer_func_predefined tf;
460 enum spl_color_space color_space; // Color Space
461 unsigned int max_luminance; // Max Luminance TODO: Is determined in dc_hw_sequencer.c is_sdr
462 bool film_grain_applied; // Film Grain Applied // TODO: To check from where to get this?
463 int custom_width; // Width for non-standard segmentation - used when != 0
464 int custom_x; // Start x for non-standard segmentation - used when custom_width != 0
465};
466
467// Basic output information
468struct basic_out {
469 struct spl_size output_size; // Output Size
470 struct spl_rect dst_rect; // Destination Rect
471 struct spl_rect src_rect; // Source rect
472 int odm_combine_factor; // deprecated
473 struct spl_rect odm_slice_rect; // OPP input rect in timing active
474 enum spl_view_3d view_format; // TODO: View format Check if it is chroma subsampling
475 bool always_scale; // Is always scale enabled? Required for getting SCL_MODE
476 int max_downscale_src_width; // Required to get optimal no of taps
477 bool alpha_en;
478 bool use_two_pixels_per_container;
479};
480enum sharpness_setting {
481 SHARPNESS_HW_OFF = 0,
482 SHARPNESS_ZERO,
483 SHARPNESS_CUSTOM
484};
485enum sharpness_range_source {
486 SHARPNESS_RANGE_DCN = 0,
487 SHARPNESS_RANGE_DCN_OVERRIDE
488};
489struct spl_sharpness_range {
490 int sdr_rgb_min;
491 int sdr_rgb_max;
492 int sdr_rgb_mid;
493 int sdr_yuv_min;
494 int sdr_yuv_max;
495 int sdr_yuv_mid;
496 int hdr_rgb_min;
497 int hdr_rgb_max;
498 int hdr_rgb_mid;
499};
500struct adaptive_sharpness {
501 bool enable;
502 unsigned int sharpness_level;
503 struct spl_sharpness_range sharpness_range;
504};
505enum linear_light_scaling { // convert it in translation logic
506 LLS_PREF_DONT_CARE = 0,
507 LLS_PREF_YES,
508 LLS_PREF_NO
509};
510enum sharpen_policy {
511 SHARPEN_ALWAYS = 0,
512 SHARPEN_YUV = 1,
513 SHARPEN_RGB_FULLSCREEN_YUV = 2,
514 SHARPEN_FULLSCREEN_ALL = 3
515};
516enum scale_to_sharpness_policy {
517 NO_SCALE_TO_SHARPNESS_ADJ = 0,
518 SCALE_TO_SHARPNESS_ADJ_YUV = 1,
519 SCALE_TO_SHARPNESS_ADJ_ALL = 2
520};
521struct spl_callbacks {
522 void (*spl_calc_lb_num_partitions)
523 (bool alpha_en,
524 const struct spl_scaler_data *scl_data,
525 enum lb_memory_config lb_config,
526 int *num_part_y,
527 int *num_part_c);
528};
529
530struct spl_debug {
531 int visual_confirm_base_offset;
532 int visual_confirm_dpp_offset;
533 enum scale_to_sharpness_policy scale_to_sharpness_policy;
534};
535
536struct spl_in {
537 struct basic_out basic_out;
538 struct basic_in basic_in;
539 // Basic slice information
540 int odm_slice_index; // ODM Slice Index using get_odm_split_index
541 struct spl_taps scaling_quality; // Explicit Scaling Quality
542 struct spl_callbacks callbacks;
543 // Inputs for isharp and EASF
544 struct adaptive_sharpness adaptive_sharpness; // Adaptive Sharpness
545 enum linear_light_scaling lls_pref; // Linear Light Scaling
546 bool prefer_easf;
547 bool disable_easf;
548 bool override_easf; /* If true, keep EASF enabled but use provided in_taps */
549 struct spl_debug debug;
550 bool is_fullscreen;
551 bool is_hdr_on;
552 int h_active;
553 int v_active;
554 int min_viewport_size;
555 int sdr_white_level_nits;
556 enum sharpen_policy sharpen_policy;
557};
558// end of SPL inputs
559
560#endif /* __DC_SPL_TYPES_H__ */
561

source code of linux/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_types.h