1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DAL_DCCG_H__
27#define __DAL_DCCG_H__
28
29#include "dc_types.h"
30#include "hw_shared.h"
31
32enum phyd32clk_clock_source {
33 PHYD32CLKA,
34 PHYD32CLKB,
35 PHYD32CLKC,
36 PHYD32CLKD,
37 PHYD32CLKE,
38 PHYD32CLKF,
39 PHYD32CLKG,
40};
41
42enum physymclk_clock_source {
43 PHYSYMCLK_FORCE_SRC_SYMCLK, // Select symclk as source of clock which is output to PHY through DCIO.
44 PHYSYMCLK_FORCE_SRC_PHYD18CLK, // Select phyd18clk as the source of clock which is output to PHY through DCIO.
45 PHYSYMCLK_FORCE_SRC_PHYD32CLK, // Select phyd32clk as the source of clock which is output to PHY through DCIO.
46};
47
48enum streamclk_source {
49 REFCLK, // Selects REFCLK as source for hdmistreamclk.
50 DTBCLK0, // Selects DTBCLK0 as source for hdmistreamclk.
51 DPREFCLK, // Selects DPREFCLK as source for hdmistreamclk
52};
53
54enum dentist_dispclk_change_mode {
55 DISPCLK_CHANGE_MODE_IMMEDIATE,
56 DISPCLK_CHANGE_MODE_RAMPING,
57};
58
59struct dp_dto_params {
60 int otg_inst;
61 enum signal_type signal;
62 enum streamclk_source clk_src;
63 uint64_t pixclk_hz;
64 uint64_t refclk_hz;
65};
66
67enum pixel_rate_div {
68 PIXEL_RATE_DIV_BY_1 = 0,
69 PIXEL_RATE_DIV_BY_2 = 1,
70 PIXEL_RATE_DIV_BY_4 = 3,
71 PIXEL_RATE_DIV_NA = 0xF
72};
73
74struct dcn_dccg_reg_state {
75 uint32_t dc_mem_global_pwr_req_cntl;
76 uint32_t dccg_audio_dtbclk_dto_modulo;
77 uint32_t dccg_audio_dtbclk_dto_phase;
78 uint32_t dccg_audio_dto_source;
79 uint32_t dccg_audio_dto0_module;
80 uint32_t dccg_audio_dto0_phase;
81 uint32_t dccg_audio_dto1_module;
82 uint32_t dccg_audio_dto1_phase;
83 uint32_t dccg_cac_status;
84 uint32_t dccg_cac_status2;
85 uint32_t dccg_disp_cntl_reg;
86 uint32_t dccg_ds_cntl;
87 uint32_t dccg_ds_dto_incr;
88 uint32_t dccg_ds_dto_modulo;
89 uint32_t dccg_ds_hw_cal_interval;
90 uint32_t dccg_gate_disable_cntl;
91 uint32_t dccg_gate_disable_cntl2;
92 uint32_t dccg_gate_disable_cntl3;
93 uint32_t dccg_gate_disable_cntl4;
94 uint32_t dccg_gate_disable_cntl5;
95 uint32_t dccg_gate_disable_cntl6;
96 uint32_t dccg_global_fgcg_rep_cntl;
97 uint32_t dccg_gtc_cntl;
98 uint32_t dccg_gtc_current;
99 uint32_t dccg_gtc_dto_incr;
100 uint32_t dccg_gtc_dto_modulo;
101 uint32_t dccg_perfmon_cntl;
102 uint32_t dccg_perfmon_cntl2;
103 uint32_t dccg_soft_reset;
104 uint32_t dccg_test_clk_sel;
105 uint32_t dccg_vsync_cnt_ctrl;
106 uint32_t dccg_vsync_cnt_int_ctrl;
107 uint32_t dccg_vsync_otg0_latch_value;
108 uint32_t dccg_vsync_otg1_latch_value;
109 uint32_t dccg_vsync_otg2_latch_value;
110 uint32_t dccg_vsync_otg3_latch_value;
111 uint32_t dccg_vsync_otg4_latch_value;
112 uint32_t dccg_vsync_otg5_latch_value;
113 uint32_t dispclk_cgtt_blk_ctrl_reg;
114 uint32_t dispclk_freq_change_cntl;
115 uint32_t dp_dto_dbuf_en;
116 uint32_t dp_dto0_modulo;
117 uint32_t dp_dto0_phase;
118 uint32_t dp_dto1_modulo;
119 uint32_t dp_dto1_phase;
120 uint32_t dp_dto2_modulo;
121 uint32_t dp_dto2_phase;
122 uint32_t dp_dto3_modulo;
123 uint32_t dp_dto3_phase;
124 uint32_t dpiaclk_540m_dto_modulo;
125 uint32_t dpiaclk_540m_dto_phase;
126 uint32_t dpiaclk_810m_dto_modulo;
127 uint32_t dpiaclk_810m_dto_phase;
128 uint32_t dpiaclk_dto_cntl;
129 uint32_t dpiasymclk_cntl;
130 uint32_t dppclk_cgtt_blk_ctrl_reg;
131 uint32_t dppclk_ctrl;
132 uint32_t dppclk_dto_ctrl;
133 uint32_t dppclk0_dto_param;
134 uint32_t dppclk1_dto_param;
135 uint32_t dppclk2_dto_param;
136 uint32_t dppclk3_dto_param;
137 uint32_t dprefclk_cgtt_blk_ctrl_reg;
138 uint32_t dprefclk_cntl;
139 uint32_t dpstreamclk_cntl;
140 uint32_t dscclk_dto_ctrl;
141 uint32_t dscclk0_dto_param;
142 uint32_t dscclk1_dto_param;
143 uint32_t dscclk2_dto_param;
144 uint32_t dscclk3_dto_param;
145 uint32_t dtbclk_dto_dbuf_en;
146 uint32_t dtbclk_dto0_modulo;
147 uint32_t dtbclk_dto0_phase;
148 uint32_t dtbclk_dto1_modulo;
149 uint32_t dtbclk_dto1_phase;
150 uint32_t dtbclk_dto2_modulo;
151 uint32_t dtbclk_dto2_phase;
152 uint32_t dtbclk_dto3_modulo;
153 uint32_t dtbclk_dto3_phase;
154 uint32_t dtbclk_p_cntl;
155 uint32_t force_symclk_disable;
156 uint32_t hdmicharclk0_clock_cntl;
157 uint32_t hdmistreamclk_cntl;
158 uint32_t hdmistreamclk0_dto_param;
159 uint32_t microsecond_time_base_div;
160 uint32_t millisecond_time_base_div;
161 uint32_t otg_pixel_rate_div;
162 uint32_t otg0_phypll_pixel_rate_cntl;
163 uint32_t otg0_pixel_rate_cntl;
164 uint32_t otg1_phypll_pixel_rate_cntl;
165 uint32_t otg1_pixel_rate_cntl;
166 uint32_t otg2_phypll_pixel_rate_cntl;
167 uint32_t otg2_pixel_rate_cntl;
168 uint32_t otg3_phypll_pixel_rate_cntl;
169 uint32_t otg3_pixel_rate_cntl;
170 uint32_t phyasymclk_clock_cntl;
171 uint32_t phybsymclk_clock_cntl;
172 uint32_t phycsymclk_clock_cntl;
173 uint32_t phydsymclk_clock_cntl;
174 uint32_t phyesymclk_clock_cntl;
175 uint32_t phyplla_pixclk_resync_cntl;
176 uint32_t phypllb_pixclk_resync_cntl;
177 uint32_t phypllc_pixclk_resync_cntl;
178 uint32_t phyplld_pixclk_resync_cntl;
179 uint32_t phyplle_pixclk_resync_cntl;
180 uint32_t refclk_cgtt_blk_ctrl_reg;
181 uint32_t socclk_cgtt_blk_ctrl_reg;
182 uint32_t symclk_cgtt_blk_ctrl_reg;
183 uint32_t symclk_psp_cntl;
184 uint32_t symclk32_le_cntl;
185 uint32_t symclk32_se_cntl;
186 uint32_t symclka_clock_enable;
187 uint32_t symclkb_clock_enable;
188 uint32_t symclkc_clock_enable;
189 uint32_t symclkd_clock_enable;
190 uint32_t symclke_clock_enable;
191};
192
193struct dccg {
194 struct dc_context *ctx;
195 const struct dccg_funcs *funcs;
196 int pipe_dppclk_khz[MAX_PIPES];
197 int ref_dppclk;
198 bool dpp_clock_gated[MAX_PIPES];
199 //int dtbclk_khz[MAX_PIPES];/* TODO needs to be removed */
200 //int audio_dtbclk_khz;/* TODO needs to be removed */
201 //int ref_dtbclk_khz;/* TODO needs to be removed */
202};
203struct dtbclk_dto_params {
204 const struct dc_crtc_timing *timing;
205 int otg_inst;
206 int pixclk_khz;
207 int req_audio_dtbclk_khz;
208 int num_odm_segments;
209 int ref_dtbclk_khz;
210 bool is_hdmi;
211};
212
213struct dccg_funcs {
214 void (*update_dpp_dto)(struct dccg *dccg,
215 int dpp_inst,
216 int req_dppclk);
217 void (*get_dccg_ref_freq)(struct dccg *dccg,
218 unsigned int xtalin_freq_inKhz,
219 unsigned int *dccg_ref_freq_inKhz);
220 void (*set_fifo_errdet_ovr_en)(struct dccg *dccg,
221 bool en);
222 void (*otg_add_pixel)(struct dccg *dccg,
223 uint32_t otg_inst);
224 void (*otg_drop_pixel)(struct dccg *dccg,
225 uint32_t otg_inst);
226 void (*dccg_init)(struct dccg *dccg);
227 void (*set_dpstreamclk_root_clock_gating)(
228 struct dccg *dccg,
229 int dp_hpo_inst,
230 bool enable);
231
232 void (*set_dpstreamclk)(
233 struct dccg *dccg,
234 enum streamclk_source src,
235 int otg_inst,
236 int dp_hpo_inst);
237
238 void (*enable_symclk32_se)(
239 struct dccg *dccg,
240 int hpo_se_inst,
241 enum phyd32clk_clock_source phyd32clk);
242
243 void (*disable_symclk32_se)(
244 struct dccg *dccg,
245 int hpo_se_inst);
246
247 void (*enable_symclk32_le)(
248 struct dccg *dccg,
249 int hpo_le_inst,
250 enum phyd32clk_clock_source phyd32clk);
251
252 void (*disable_symclk32_le)(
253 struct dccg *dccg,
254 int hpo_le_inst);
255
256 void (*set_symclk32_le_root_clock_gating)(
257 struct dccg *dccg,
258 int hpo_le_inst,
259 bool enable);
260
261 void (*set_physymclk)(
262 struct dccg *dccg,
263 int phy_inst,
264 enum physymclk_clock_source clk_src,
265 bool force_enable);
266
267 void (*set_physymclk_root_clock_gating)(
268 struct dccg *dccg,
269 int phy_inst,
270 bool enable);
271
272 void (*set_dtbclk_dto)(
273 struct dccg *dccg,
274 const struct dtbclk_dto_params *params);
275
276 void (*set_audio_dtbclk_dto)(
277 struct dccg *dccg,
278 const struct dtbclk_dto_params *params);
279
280 void (*set_dispclk_change_mode)(
281 struct dccg *dccg,
282 enum dentist_dispclk_change_mode change_mode);
283
284 void (*disable_dsc)(
285 struct dccg *dccg,
286 int inst);
287
288 void (*enable_dsc)(
289 struct dccg *dccg,
290 int inst);
291
292 void (*set_pixel_rate_div)(struct dccg *dccg,
293 uint32_t otg_inst,
294 enum pixel_rate_div k1,
295 enum pixel_rate_div k2);
296
297 void (*get_pixel_rate_div)(struct dccg *dccg,
298 uint32_t otg_inst,
299 uint32_t *div_factor1,
300 uint32_t *div_factor2);
301
302 void (*set_valid_pixel_rate)(
303 struct dccg *dccg,
304 int ref_dtbclk_khz,
305 int otg_inst,
306 int pixclk_khz);
307
308 void (*trigger_dio_fifo_resync)(
309 struct dccg *dccg);
310
311 void (*dpp_root_clock_control)(
312 struct dccg *dccg,
313 unsigned int dpp_inst,
314 bool clock_on);
315
316 void (*enable_symclk_se)(
317 struct dccg *dccg,
318 uint32_t stream_enc_inst,
319 uint32_t link_enc_inst);
320
321 void (*disable_symclk_se)(
322 struct dccg *dccg,
323 uint32_t stream_enc_inst,
324 uint32_t link_enc_inst);
325 void (*set_dp_dto)(
326 struct dccg *dccg,
327 const struct dp_dto_params *params);
328 void (*set_dtbclk_p_src)(
329 struct dccg *dccg,
330 enum streamclk_source src,
331 uint32_t otg_inst);
332 void (*set_dto_dscclk)(struct dccg *dccg, uint32_t dsc_inst, uint32_t num_slices_h);
333 void (*set_ref_dscclk)(struct dccg *dccg, uint32_t dsc_inst);
334 void (*dccg_root_gate_disable_control)(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating);
335 void (*dccg_read_reg_state)(struct dccg *dccg, struct dcn_dccg_reg_state *dccg_reg_state);
336};
337
338#endif //__DAL_DCCG_H__
339

source code of linux/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h