1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DC_STREAM_ENCODER_DCE110_H__
27#define __DC_STREAM_ENCODER_DCE110_H__
28
29#include "stream_encoder.h"
30
31#define DCE110STRENC_FROM_STRENC(stream_encoder)\
32 container_of(stream_encoder, struct dce110_stream_encoder, base)
33
34#ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK
35 #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x00000010L
36 #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x00000300L
37 #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x00000004
38 #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x00000008
39#endif
40
41
42#define SE_COMMON_REG_LIST_DCE_BASE(id) \
43 SE_COMMON_REG_LIST_BASE(id),\
44 SRI(AFMT_AVI_INFO0, DIG, id), \
45 SRI(AFMT_AVI_INFO1, DIG, id), \
46 SRI(AFMT_AVI_INFO2, DIG, id), \
47 SRI(AFMT_AVI_INFO3, DIG, id)
48
49#define SE_COMMON_REG_LIST_BASE(id) \
50 SRI(AFMT_GENERIC_0, DIG, id), \
51 SRI(AFMT_GENERIC_1, DIG, id), \
52 SRI(AFMT_GENERIC_2, DIG, id), \
53 SRI(AFMT_GENERIC_3, DIG, id), \
54 SRI(AFMT_GENERIC_4, DIG, id), \
55 SRI(AFMT_GENERIC_5, DIG, id), \
56 SRI(AFMT_GENERIC_6, DIG, id), \
57 SRI(AFMT_GENERIC_7, DIG, id), \
58 SRI(AFMT_GENERIC_HDR, DIG, id), \
59 SRI(AFMT_INFOFRAME_CONTROL0, DIG, id), \
60 SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \
61 SRI(AFMT_AUDIO_PACKET_CONTROL, DIG, id), \
62 SRI(AFMT_AUDIO_PACKET_CONTROL2, DIG, id), \
63 SRI(AFMT_AUDIO_SRC_CONTROL, DIG, id), \
64 SRI(AFMT_60958_0, DIG, id), \
65 SRI(AFMT_60958_1, DIG, id), \
66 SRI(AFMT_60958_2, DIG, id), \
67 SRI(DIG_FE_CNTL, DIG, id), \
68 SRI(HDMI_CONTROL, DIG, id), \
69 SRI(HDMI_GC, DIG, id), \
70 SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
71 SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
72 SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \
73 SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
74 SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \
75 SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
76 SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
77 SRI(HDMI_ACR_32_0, DIG, id),\
78 SRI(HDMI_ACR_32_1, DIG, id),\
79 SRI(HDMI_ACR_44_0, DIG, id),\
80 SRI(HDMI_ACR_44_1, DIG, id),\
81 SRI(HDMI_ACR_48_0, DIG, id),\
82 SRI(HDMI_ACR_48_1, DIG, id),\
83 SRI(TMDS_CNTL, DIG, id), \
84 SRI(DP_MSE_RATE_CNTL, DP, id), \
85 SRI(DP_MSE_RATE_UPDATE, DP, id), \
86 SRI(DP_PIXEL_FORMAT, DP, id), \
87 SRI(DP_SEC_CNTL, DP, id), \
88 SRI(DP_STEER_FIFO, DP, id), \
89 SRI(DP_VID_M, DP, id), \
90 SRI(DP_VID_N, DP, id), \
91 SRI(DP_VID_STREAM_CNTL, DP, id), \
92 SRI(DP_VID_TIMING, DP, id), \
93 SRI(DP_SEC_AUD_N, DP, id), \
94 SRI(DP_SEC_TIMESTAMP, DP, id)
95
96#define SE_COMMON_REG_LIST(id)\
97 SE_COMMON_REG_LIST_DCE_BASE(id), \
98 SRI(AFMT_CNTL, DIG, id)
99
100#define SE_DCN_REG_LIST(id)\
101 SE_COMMON_REG_LIST_BASE(id),\
102 SRI(AFMT_CNTL, DIG, id),\
103 SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id),\
104 SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
105 SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
106 SRI(DP_DB_CNTL, DP, id), \
107 SRI(DP_MSA_MISC, DP, id), \
108 SRI(DP_MSA_COLORIMETRY, DP, id), \
109 SRI(DP_MSA_TIMING_PARAM1, DP, id), \
110 SRI(DP_MSA_TIMING_PARAM2, DP, id), \
111 SRI(DP_MSA_TIMING_PARAM3, DP, id), \
112 SRI(DP_MSA_TIMING_PARAM4, DP, id), \
113 SRI(HDMI_DB_CONTROL, DIG, id)
114
115#define SE_SF(reg_name, field_name, post_fix)\
116 .field_name = reg_name ## __ ## field_name ## post_fix
117
118#define SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh)\
119 SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\
120 SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC0_UPDATE, mask_sh),\
121 SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC2_UPDATE, mask_sh),\
122 SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\
123 SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\
124 SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\
125 SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\
126 SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\
127 SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\
128 SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\
129 SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
130 SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
131 SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh),\
132 SE_SF(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\
133 SE_SF(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\
134 SE_SF(DP_PIXEL_FORMAT, DP_DYN_RANGE, mask_sh),\
135 SE_SF(DP_PIXEL_FORMAT, DP_YCBCR_RANGE, mask_sh),\
136 SE_SF(HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\
137 SE_SF(HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\
138 SE_SF(HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
139 SE_SF(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
140 SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
141 SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\
142 SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\
143 SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh),\
144 SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\
145 SE_SF(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\
146 SE_SF(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
147 SE_SF(HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
148 SE_SF(DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\
149 SE_SF(DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\
150 SE_SF(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\
151 SE_SF(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, mask_sh),\
152 SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, mask_sh),\
153 SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, mask_sh),\
154 SE_SF(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, mask_sh),\
155 SE_SF(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
156 SE_SF(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
157 SE_SF(DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\
158 SE_SF(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
159 SE_SF(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
160 SE_SF(DP_SEC_CNTL, DP_SEC_AVI_ENABLE, mask_sh),\
161 SE_SF(DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
162 SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
163 SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
164 SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
165 SE_SF(DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
166 SE_SF(DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
167 SE_SF(DP_VID_N, DP_VID_N, mask_sh),\
168 SE_SF(DP_VID_M, DP_VID_M, mask_sh),\
169 SE_SF(DIG_FE_CNTL, DIG_START, mask_sh),\
170 SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
171 SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
172 SE_SF(AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\
173 SE_SF(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\
174 SE_SF(HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\
175 SE_SF(HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\
176 SE_SF(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\
177 SE_SF(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\
178 SE_SF(AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\
179 SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
180 SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
181 SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
182 SE_SF(HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
183 SE_SF(HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
184 SE_SF(HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
185 SE_SF(HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
186 SE_SF(HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
187 SE_SF(HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
188 SE_SF(AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\
189 SE_SF(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\
190 SE_SF(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\
191 SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\
192 SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\
193 SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\
194 SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\
195 SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\
196 SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\
197 SE_SF(DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
198 SE_SF(DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
199 SE_SF(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
200 SE_SF(DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
201 SE_SF(DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
202 SE_SF(DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
203 SE_SF(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\
204 SE_SF(DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh)
205
206#define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\
207 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\
208 SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\
209 SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\
210 SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\
211 SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\
212 SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\
213 SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\
214 SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\
215 SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
216 SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
217 SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh),\
218 SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\
219 SE_SF(DP0_DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\
220 SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\
221 SE_SF(DIG0_HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\
222 SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
223 SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
224 SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
225 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
226 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\
227 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\
228 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh),\
229 SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\
230 SE_SF(DIG0_AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\
231 SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
232 SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
233 SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\
234 SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\
235 SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\
236 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
237 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
238 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\
239 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
240 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
241 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
242 SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
243 SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
244 SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
245 SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
246 SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
247 SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\
248 SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\
249 SE_SF(DIG0_DIG_FE_CNTL, DIG_START, mask_sh),\
250 SE_SF(DIG0_AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\
251 SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\
252 SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\
253 SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\
254 SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\
255 SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\
256 SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\
257 SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
258 SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
259 SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
260 SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
261 SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
262 SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
263 SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
264 SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
265 SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
266 SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\
267 SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\
268 SE_SF(DIG0_AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\
269 SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\
270 SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\
271 SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\
272 SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\
273 SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\
274 SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\
275 SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
276 SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
277 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
278 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
279 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
280 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
281 SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\
282 SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
283 SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
284 SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
285 SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
286 SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
287 SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
288 SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh)
289
290#define SE_COMMON_MASK_SH_LIST_DCE80_100(mask_sh)\
291 SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\
292 SE_SF(TMDS_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
293 SE_SF(TMDS_CNTL, TMDS_COLOR_FORMAT, mask_sh)
294
295#define SE_COMMON_MASK_SH_LIST_DCE110(mask_sh)\
296 SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\
297 SE_SF(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
298 SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
299 SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
300 SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
301 SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
302 SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
303 SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh)
304
305#define SE_COMMON_MASK_SH_LIST_DCE112(mask_sh)\
306 SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\
307 SE_SF(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
308 SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
309 SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
310 SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
311 SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
312 SE_SF(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh)
313
314#define SE_COMMON_MASK_SH_LIST_DCE120(mask_sh)\
315 SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\
316 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC0_UPDATE, mask_sh),\
317 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC2_UPDATE, mask_sh),\
318 SE_SF(DP0_DP_PIXEL_FORMAT, DP_DYN_RANGE, mask_sh),\
319 SE_SF(DP0_DP_PIXEL_FORMAT, DP_YCBCR_RANGE, mask_sh),\
320 SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, mask_sh),\
321 SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, mask_sh),\
322 SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, mask_sh),\
323 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AVI_ENABLE, mask_sh),\
324 SE_SF(DIG0_AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, mask_sh),\
325 SE_SF(DP0_DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh)
326
327#define SE_COMMON_MASK_SH_LIST_DCN10(mask_sh)\
328 SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\
329 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, mask_sh),\
330 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, mask_sh),\
331 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, mask_sh),\
332 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE_PENDING, mask_sh),\
333 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE_PENDING, mask_sh),\
334 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE_PENDING, mask_sh),\
335 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE_PENDING, mask_sh),\
336 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE_PENDING, mask_sh),\
337 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE_PENDING, mask_sh),\
338 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE_PENDING, mask_sh),\
339 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE_PENDING, mask_sh),\
340 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE, mask_sh),\
341 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE, mask_sh),\
342 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE, mask_sh),\
343 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE, mask_sh),\
344 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE, mask_sh),\
345 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE, mask_sh),\
346 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE, mask_sh),\
347 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, mask_sh),\
348 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\
349 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
350 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\
351 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\
352 SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\
353 SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\
354 SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\
355 SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\
356 SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\
357 SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\
358 SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\
359 SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\
360 SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\
361 SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\
362 SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\
363 SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\
364 SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\
365 SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh)
366
367struct dce_stream_encoder_shift {
368 uint8_t AFMT_GENERIC_INDEX;
369 uint8_t AFMT_GENERIC0_UPDATE;
370 uint8_t AFMT_GENERIC2_UPDATE;
371 uint8_t AFMT_GENERIC_HB0;
372 uint8_t AFMT_GENERIC_HB1;
373 uint8_t AFMT_GENERIC_HB2;
374 uint8_t AFMT_GENERIC_HB3;
375 uint8_t AFMT_GENERIC_LOCK_STATUS;
376 uint8_t AFMT_GENERIC_CONFLICT;
377 uint8_t AFMT_GENERIC_CONFLICT_CLR;
378 uint8_t AFMT_GENERIC0_FRAME_UPDATE_PENDING;
379 uint8_t AFMT_GENERIC1_FRAME_UPDATE_PENDING;
380 uint8_t AFMT_GENERIC2_FRAME_UPDATE_PENDING;
381 uint8_t AFMT_GENERIC3_FRAME_UPDATE_PENDING;
382 uint8_t AFMT_GENERIC4_FRAME_UPDATE_PENDING;
383 uint8_t AFMT_GENERIC5_FRAME_UPDATE_PENDING;
384 uint8_t AFMT_GENERIC6_FRAME_UPDATE_PENDING;
385 uint8_t AFMT_GENERIC7_FRAME_UPDATE_PENDING;
386 uint8_t AFMT_GENERIC0_FRAME_UPDATE;
387 uint8_t AFMT_GENERIC1_FRAME_UPDATE;
388 uint8_t AFMT_GENERIC2_FRAME_UPDATE;
389 uint8_t AFMT_GENERIC3_FRAME_UPDATE;
390 uint8_t AFMT_GENERIC4_FRAME_UPDATE;
391 uint8_t AFMT_GENERIC5_FRAME_UPDATE;
392 uint8_t AFMT_GENERIC6_FRAME_UPDATE;
393 uint8_t AFMT_GENERIC7_FRAME_UPDATE;
394 uint8_t HDMI_GENERIC0_CONT;
395 uint8_t HDMI_GENERIC0_SEND;
396 uint8_t HDMI_GENERIC0_LINE;
397 uint8_t HDMI_GENERIC1_CONT;
398 uint8_t HDMI_GENERIC1_SEND;
399 uint8_t HDMI_GENERIC1_LINE;
400 uint8_t DP_PIXEL_ENCODING;
401 uint8_t DP_COMPONENT_DEPTH;
402 uint8_t DP_DYN_RANGE;
403 uint8_t DP_YCBCR_RANGE;
404 uint8_t HDMI_PACKET_GEN_VERSION;
405 uint8_t HDMI_KEEPOUT_MODE;
406 uint8_t HDMI_DEEP_COLOR_ENABLE;
407 uint8_t HDMI_CLOCK_CHANNEL_RATE;
408 uint8_t HDMI_DEEP_COLOR_DEPTH;
409 uint8_t HDMI_GC_CONT;
410 uint8_t HDMI_GC_SEND;
411 uint8_t HDMI_NULL_SEND;
412 uint8_t HDMI_DATA_SCRAMBLE_EN;
413 uint8_t HDMI_ACP_SEND;
414 uint8_t HDMI_AUDIO_INFO_SEND;
415 uint8_t AFMT_AUDIO_INFO_UPDATE;
416 uint8_t HDMI_AUDIO_INFO_LINE;
417 uint8_t HDMI_GC_AVMUTE;
418 uint8_t DP_MSE_RATE_X;
419 uint8_t DP_MSE_RATE_Y;
420 uint8_t DP_MSE_RATE_UPDATE_PENDING;
421 uint8_t AFMT_AVI_INFO_VERSION;
422 uint8_t HDMI_AVI_INFO_SEND;
423 uint8_t HDMI_AVI_INFO_CONT;
424 uint8_t HDMI_AVI_INFO_LINE;
425 uint8_t DP_SEC_GSP0_ENABLE;
426 uint8_t DP_SEC_STREAM_ENABLE;
427 uint8_t DP_SEC_GSP1_ENABLE;
428 uint8_t DP_SEC_GSP2_ENABLE;
429 uint8_t DP_SEC_GSP3_ENABLE;
430 uint8_t DP_SEC_GSP4_ENABLE;
431 uint8_t DP_SEC_GSP5_ENABLE;
432 uint8_t DP_SEC_GSP6_ENABLE;
433 uint8_t DP_SEC_GSP7_ENABLE;
434 uint8_t DP_SEC_AVI_ENABLE;
435 uint8_t DP_SEC_MPG_ENABLE;
436 uint8_t DP_VID_STREAM_DIS_DEFER;
437 uint8_t DP_VID_STREAM_ENABLE;
438 uint8_t DP_VID_STREAM_STATUS;
439 uint8_t DP_STEER_FIFO_RESET;
440 uint8_t DP_VID_M_N_GEN_EN;
441 uint8_t DP_VID_N;
442 uint8_t DP_VID_M;
443 uint8_t DIG_START;
444 uint8_t AFMT_AUDIO_SRC_SELECT;
445 uint8_t AFMT_AUDIO_CHANNEL_ENABLE;
446 uint8_t HDMI_AUDIO_PACKETS_PER_LINE;
447 uint8_t HDMI_AUDIO_DELAY_EN;
448 uint8_t AFMT_60958_CS_UPDATE;
449 uint8_t AFMT_AUDIO_LAYOUT_OVRD;
450 uint8_t AFMT_60958_OSF_OVRD;
451 uint8_t HDMI_ACR_AUTO_SEND;
452 uint8_t HDMI_ACR_SOURCE;
453 uint8_t HDMI_ACR_AUDIO_PRIORITY;
454 uint8_t HDMI_ACR_CTS_32;
455 uint8_t HDMI_ACR_N_32;
456 uint8_t HDMI_ACR_CTS_44;
457 uint8_t HDMI_ACR_N_44;
458 uint8_t HDMI_ACR_CTS_48;
459 uint8_t HDMI_ACR_N_48;
460 uint8_t AFMT_60958_CS_CHANNEL_NUMBER_L;
461 uint8_t AFMT_60958_CS_CLOCK_ACCURACY;
462 uint8_t AFMT_60958_CS_CHANNEL_NUMBER_R;
463 uint8_t AFMT_60958_CS_CHANNEL_NUMBER_2;
464 uint8_t AFMT_60958_CS_CHANNEL_NUMBER_3;
465 uint8_t AFMT_60958_CS_CHANNEL_NUMBER_4;
466 uint8_t AFMT_60958_CS_CHANNEL_NUMBER_5;
467 uint8_t AFMT_60958_CS_CHANNEL_NUMBER_6;
468 uint8_t AFMT_60958_CS_CHANNEL_NUMBER_7;
469 uint8_t DP_SEC_AUD_N;
470 uint8_t DP_SEC_TIMESTAMP_MODE;
471 uint8_t DP_SEC_ASP_ENABLE;
472 uint8_t DP_SEC_ATP_ENABLE;
473 uint8_t DP_SEC_AIP_ENABLE;
474 uint8_t DP_SEC_ACM_ENABLE;
475 uint8_t AFMT_AUDIO_SAMPLE_SEND;
476 uint8_t AFMT_AUDIO_CLOCK_EN;
477 uint8_t TMDS_PIXEL_ENCODING;
478 uint8_t TMDS_COLOR_FORMAT;
479 uint8_t DIG_STEREOSYNC_SELECT;
480 uint8_t DIG_STEREOSYNC_GATE_EN;
481 uint8_t DP_DB_DISABLE;
482 uint8_t DP_MSA_MISC0;
483 uint8_t DP_MSA_HTOTAL;
484 uint8_t DP_MSA_VTOTAL;
485 uint8_t DP_MSA_HSTART;
486 uint8_t DP_MSA_VSTART;
487 uint8_t DP_MSA_HSYNCWIDTH;
488 uint8_t DP_MSA_HSYNCPOLARITY;
489 uint8_t DP_MSA_VSYNCWIDTH;
490 uint8_t DP_MSA_VSYNCPOLARITY;
491 uint8_t DP_MSA_HWIDTH;
492 uint8_t DP_MSA_VHEIGHT;
493 uint8_t HDMI_DB_DISABLE;
494 uint8_t DP_VID_N_MUL;
495 uint8_t DP_VID_M_DOUBLE_VALUE_EN;
496 uint8_t DIG_SOURCE_SELECT;
497};
498
499struct dce_stream_encoder_mask {
500 uint32_t AFMT_GENERIC_INDEX;
501 uint32_t AFMT_GENERIC0_UPDATE;
502 uint32_t AFMT_GENERIC2_UPDATE;
503 uint32_t AFMT_GENERIC_HB0;
504 uint32_t AFMT_GENERIC_HB1;
505 uint32_t AFMT_GENERIC_HB2;
506 uint32_t AFMT_GENERIC_HB3;
507 uint32_t AFMT_GENERIC_LOCK_STATUS;
508 uint32_t AFMT_GENERIC_CONFLICT;
509 uint32_t AFMT_GENERIC_CONFLICT_CLR;
510 uint32_t AFMT_GENERIC0_FRAME_UPDATE_PENDING;
511 uint32_t AFMT_GENERIC1_FRAME_UPDATE_PENDING;
512 uint32_t AFMT_GENERIC2_FRAME_UPDATE_PENDING;
513 uint32_t AFMT_GENERIC3_FRAME_UPDATE_PENDING;
514 uint32_t AFMT_GENERIC4_FRAME_UPDATE_PENDING;
515 uint32_t AFMT_GENERIC5_FRAME_UPDATE_PENDING;
516 uint32_t AFMT_GENERIC6_FRAME_UPDATE_PENDING;
517 uint32_t AFMT_GENERIC7_FRAME_UPDATE_PENDING;
518 uint32_t AFMT_GENERIC0_FRAME_UPDATE;
519 uint32_t AFMT_GENERIC1_FRAME_UPDATE;
520 uint32_t AFMT_GENERIC2_FRAME_UPDATE;
521 uint32_t AFMT_GENERIC3_FRAME_UPDATE;
522 uint32_t AFMT_GENERIC4_FRAME_UPDATE;
523 uint32_t AFMT_GENERIC5_FRAME_UPDATE;
524 uint32_t AFMT_GENERIC6_FRAME_UPDATE;
525 uint32_t AFMT_GENERIC7_FRAME_UPDATE;
526 uint32_t HDMI_GENERIC0_CONT;
527 uint32_t HDMI_GENERIC0_SEND;
528 uint32_t HDMI_GENERIC0_LINE;
529 uint32_t HDMI_GENERIC1_CONT;
530 uint32_t HDMI_GENERIC1_SEND;
531 uint32_t HDMI_GENERIC1_LINE;
532 uint32_t DP_PIXEL_ENCODING;
533 uint32_t DP_COMPONENT_DEPTH;
534 uint32_t DP_DYN_RANGE;
535 uint32_t DP_YCBCR_RANGE;
536 uint32_t HDMI_PACKET_GEN_VERSION;
537 uint32_t HDMI_KEEPOUT_MODE;
538 uint32_t HDMI_DEEP_COLOR_ENABLE;
539 uint32_t HDMI_CLOCK_CHANNEL_RATE;
540 uint32_t HDMI_DEEP_COLOR_DEPTH;
541 uint32_t HDMI_GC_CONT;
542 uint32_t HDMI_GC_SEND;
543 uint32_t HDMI_NULL_SEND;
544 uint32_t HDMI_DATA_SCRAMBLE_EN;
545 uint32_t HDMI_ACP_SEND;
546 uint32_t HDMI_AUDIO_INFO_SEND;
547 uint32_t AFMT_AUDIO_INFO_UPDATE;
548 uint32_t HDMI_AUDIO_INFO_LINE;
549 uint32_t HDMI_GC_AVMUTE;
550 uint32_t DP_MSE_RATE_X;
551 uint32_t DP_MSE_RATE_Y;
552 uint32_t DP_MSE_RATE_UPDATE_PENDING;
553 uint32_t AFMT_AVI_INFO_VERSION;
554 uint32_t HDMI_AVI_INFO_SEND;
555 uint32_t HDMI_AVI_INFO_CONT;
556 uint32_t HDMI_AVI_INFO_LINE;
557 uint32_t DP_SEC_GSP0_ENABLE;
558 uint32_t DP_SEC_STREAM_ENABLE;
559 uint32_t DP_SEC_GSP1_ENABLE;
560 uint32_t DP_SEC_GSP2_ENABLE;
561 uint32_t DP_SEC_GSP3_ENABLE;
562 uint32_t DP_SEC_GSP4_ENABLE;
563 uint32_t DP_SEC_GSP5_ENABLE;
564 uint32_t DP_SEC_GSP6_ENABLE;
565 uint32_t DP_SEC_GSP7_ENABLE;
566 uint32_t DP_SEC_AVI_ENABLE;
567 uint32_t DP_SEC_MPG_ENABLE;
568 uint32_t DP_VID_STREAM_DIS_DEFER;
569 uint32_t DP_VID_STREAM_ENABLE;
570 uint32_t DP_VID_STREAM_STATUS;
571 uint32_t DP_STEER_FIFO_RESET;
572 uint32_t DP_VID_M_N_GEN_EN;
573 uint32_t DP_VID_N;
574 uint32_t DP_VID_M;
575 uint32_t DIG_START;
576 uint32_t AFMT_AUDIO_SRC_SELECT;
577 uint32_t AFMT_AUDIO_CHANNEL_ENABLE;
578 uint32_t HDMI_AUDIO_PACKETS_PER_LINE;
579 uint32_t HDMI_AUDIO_DELAY_EN;
580 uint32_t AFMT_60958_CS_UPDATE;
581 uint32_t AFMT_AUDIO_LAYOUT_OVRD;
582 uint32_t AFMT_60958_OSF_OVRD;
583 uint32_t HDMI_ACR_AUTO_SEND;
584 uint32_t HDMI_ACR_SOURCE;
585 uint32_t HDMI_ACR_AUDIO_PRIORITY;
586 uint32_t HDMI_ACR_CTS_32;
587 uint32_t HDMI_ACR_N_32;
588 uint32_t HDMI_ACR_CTS_44;
589 uint32_t HDMI_ACR_N_44;
590 uint32_t HDMI_ACR_CTS_48;
591 uint32_t HDMI_ACR_N_48;
592 uint32_t AFMT_60958_CS_CHANNEL_NUMBER_L;
593 uint32_t AFMT_60958_CS_CLOCK_ACCURACY;
594 uint32_t AFMT_60958_CS_CHANNEL_NUMBER_R;
595 uint32_t AFMT_60958_CS_CHANNEL_NUMBER_2;
596 uint32_t AFMT_60958_CS_CHANNEL_NUMBER_3;
597 uint32_t AFMT_60958_CS_CHANNEL_NUMBER_4;
598 uint32_t AFMT_60958_CS_CHANNEL_NUMBER_5;
599 uint32_t AFMT_60958_CS_CHANNEL_NUMBER_6;
600 uint32_t AFMT_60958_CS_CHANNEL_NUMBER_7;
601 uint32_t DP_SEC_AUD_N;
602 uint32_t DP_SEC_TIMESTAMP_MODE;
603 uint32_t DP_SEC_ASP_ENABLE;
604 uint32_t DP_SEC_ATP_ENABLE;
605 uint32_t DP_SEC_AIP_ENABLE;
606 uint32_t DP_SEC_ACM_ENABLE;
607 uint32_t AFMT_AUDIO_SAMPLE_SEND;
608 uint32_t AFMT_AUDIO_CLOCK_EN;
609 uint32_t TMDS_PIXEL_ENCODING;
610 uint32_t DIG_STEREOSYNC_SELECT;
611 uint32_t DIG_STEREOSYNC_GATE_EN;
612 uint32_t TMDS_COLOR_FORMAT;
613 uint32_t DP_DB_DISABLE;
614 uint32_t DP_MSA_MISC0;
615 uint32_t DP_MSA_HTOTAL;
616 uint32_t DP_MSA_VTOTAL;
617 uint32_t DP_MSA_HSTART;
618 uint32_t DP_MSA_VSTART;
619 uint32_t DP_MSA_HSYNCWIDTH;
620 uint32_t DP_MSA_HSYNCPOLARITY;
621 uint32_t DP_MSA_VSYNCWIDTH;
622 uint32_t DP_MSA_VSYNCPOLARITY;
623 uint32_t DP_MSA_HWIDTH;
624 uint32_t DP_MSA_VHEIGHT;
625 uint32_t HDMI_DB_DISABLE;
626 uint32_t DP_VID_N_MUL;
627 uint32_t DP_VID_M_DOUBLE_VALUE_EN;
628 uint32_t DIG_SOURCE_SELECT;
629};
630
631struct dce110_stream_enc_registers {
632 uint32_t AFMT_CNTL;
633 uint32_t AFMT_AVI_INFO0;
634 uint32_t AFMT_AVI_INFO1;
635 uint32_t AFMT_AVI_INFO2;
636 uint32_t AFMT_AVI_INFO3;
637 uint32_t AFMT_GENERIC_0;
638 uint32_t AFMT_GENERIC_1;
639 uint32_t AFMT_GENERIC_2;
640 uint32_t AFMT_GENERIC_3;
641 uint32_t AFMT_GENERIC_4;
642 uint32_t AFMT_GENERIC_5;
643 uint32_t AFMT_GENERIC_6;
644 uint32_t AFMT_GENERIC_7;
645 uint32_t AFMT_GENERIC_HDR;
646 uint32_t AFMT_INFOFRAME_CONTROL0;
647 uint32_t AFMT_VBI_PACKET_CONTROL;
648 uint32_t AFMT_VBI_PACKET_CONTROL1;
649 uint32_t AFMT_AUDIO_PACKET_CONTROL;
650 uint32_t AFMT_AUDIO_PACKET_CONTROL2;
651 uint32_t AFMT_AUDIO_SRC_CONTROL;
652 uint32_t AFMT_60958_0;
653 uint32_t AFMT_60958_1;
654 uint32_t AFMT_60958_2;
655 uint32_t DIG_FE_CNTL;
656 uint32_t DP_MSE_RATE_CNTL;
657 uint32_t DP_MSE_RATE_UPDATE;
658 uint32_t DP_PIXEL_FORMAT;
659 uint32_t DP_SEC_CNTL;
660 uint32_t DP_STEER_FIFO;
661 uint32_t DP_VID_M;
662 uint32_t DP_VID_N;
663 uint32_t DP_VID_STREAM_CNTL;
664 uint32_t DP_VID_TIMING;
665 uint32_t DP_SEC_AUD_N;
666 uint32_t DP_SEC_TIMESTAMP;
667 uint32_t HDMI_CONTROL;
668 uint32_t HDMI_GC;
669 uint32_t HDMI_GENERIC_PACKET_CONTROL0;
670 uint32_t HDMI_GENERIC_PACKET_CONTROL1;
671 uint32_t HDMI_GENERIC_PACKET_CONTROL2;
672 uint32_t HDMI_GENERIC_PACKET_CONTROL3;
673 uint32_t HDMI_INFOFRAME_CONTROL0;
674 uint32_t HDMI_INFOFRAME_CONTROL1;
675 uint32_t HDMI_VBI_PACKET_CONTROL;
676 uint32_t HDMI_AUDIO_PACKET_CONTROL;
677 uint32_t HDMI_ACR_PACKET_CONTROL;
678 uint32_t HDMI_ACR_32_0;
679 uint32_t HDMI_ACR_32_1;
680 uint32_t HDMI_ACR_44_0;
681 uint32_t HDMI_ACR_44_1;
682 uint32_t HDMI_ACR_48_0;
683 uint32_t HDMI_ACR_48_1;
684 uint32_t TMDS_CNTL;
685 uint32_t DP_DB_CNTL;
686 uint32_t DP_MSA_MISC;
687 uint32_t DP_MSA_COLORIMETRY;
688 uint32_t DP_MSA_TIMING_PARAM1;
689 uint32_t DP_MSA_TIMING_PARAM2;
690 uint32_t DP_MSA_TIMING_PARAM3;
691 uint32_t DP_MSA_TIMING_PARAM4;
692 uint32_t HDMI_DB_CONTROL;
693};
694
695struct dce110_stream_encoder {
696 struct stream_encoder base;
697 const struct dce110_stream_enc_registers *regs;
698 const struct dce_stream_encoder_shift *se_shift;
699 const struct dce_stream_encoder_mask *se_mask;
700};
701
702void dce110_stream_encoder_construct(
703 struct dce110_stream_encoder *enc110,
704 struct dc_context *ctx,
705 struct dc_bios *bp,
706 enum engine_id eng_id,
707 const struct dce110_stream_enc_registers *regs,
708 const struct dce_stream_encoder_shift *se_shift,
709 const struct dce_stream_encoder_mask *se_mask);
710
711void dce110_analog_stream_encoder_construct(
712 struct dce110_stream_encoder *enc110,
713 struct dc_context *ctx,
714 struct dc_bios *bp,
715 enum engine_id eng_id);
716
717void dce110_se_audio_mute_control(
718 struct stream_encoder *enc, bool mute);
719
720void dce110_se_dp_audio_setup(
721 struct stream_encoder *enc,
722 unsigned int az_inst,
723 struct audio_info *info);
724
725void dce110_se_dp_audio_enable(
726 struct stream_encoder *enc);
727
728void dce110_se_dp_audio_disable(
729 struct stream_encoder *enc);
730
731void dce110_se_hdmi_audio_setup(
732 struct stream_encoder *enc,
733 unsigned int az_inst,
734 struct audio_info *info,
735 struct audio_crtc_info *audio_crtc_info);
736
737void dce110_se_hdmi_audio_disable(
738 struct stream_encoder *enc);
739
740#endif /* __DC_STREAM_ENCODER_DCE110_H__ */
741

source code of linux/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h