1/* Copyright 2012-15 Advanced Micro Devices, Inc.
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice shall be included in
11 * all copies or substantial portions of the Software.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
19 * OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * Authors: AMD
22 *
23 */
24
25#ifndef __DC_CLOCK_SOURCE_DCE_H__
26#define __DC_CLOCK_SOURCE_DCE_H__
27
28#include "../inc/clock_source.h"
29
30#define TO_DCE110_CLK_SRC(clk_src)\
31 container_of(clk_src, struct dce110_clk_src, base)
32
33#define CS_COMMON_REG_LIST_DCE_100_110(id) \
34 SRI(RESYNC_CNTL, PIXCLK, id), \
35 SRI(PLL_CNTL, BPHYC_PLL, id)
36
37#define CS_COMMON_REG_LIST_DCE_80(id) \
38 SRI(RESYNC_CNTL, PIXCLK, id), \
39 SRI(PLL_CNTL, DCCG_PLL, id)
40
41#define CS_COMMON_REG_LIST_DCE_112(id) \
42 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, id)
43
44
45#define CS_SF(reg_name, field_name, post_fix)\
46 .field_name = reg_name ## __ ## field_name ## post_fix
47
48#define CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\
49 CS_SF(PLL_CNTL, PLL_REF_DIV_SRC, mask_sh),\
50 CS_SF(PIXCLK1_RESYNC_CNTL, DCCG_DEEP_COLOR_CNTL1, mask_sh),\
51 CS_SF(PLL_POST_DIV, PLL_POST_DIV_PIXCLK, mask_sh),\
52 CS_SF(PLL_REF_DIV, PLL_REF_DIV, mask_sh)
53
54#define CS_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\
55 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
56 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh)
57
58#define CS_COMMON_REG_LIST_DCN2_0(index, pllid) \
59 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
60 SRII(PHASE, DP_DTO, 0),\
61 SRII(PHASE, DP_DTO, 1),\
62 SRII(PHASE, DP_DTO, 2),\
63 SRII(PHASE, DP_DTO, 3),\
64 SRII(PHASE, DP_DTO, 4),\
65 SRII(PHASE, DP_DTO, 5),\
66 SRII(MODULO, DP_DTO, 0),\
67 SRII(MODULO, DP_DTO, 1),\
68 SRII(MODULO, DP_DTO, 2),\
69 SRII(MODULO, DP_DTO, 3),\
70 SRII(MODULO, DP_DTO, 4),\
71 SRII(MODULO, DP_DTO, 5),\
72 SRII(PIXEL_RATE_CNTL, OTG, 0),\
73 SRII(PIXEL_RATE_CNTL, OTG, 1),\
74 SRII(PIXEL_RATE_CNTL, OTG, 2),\
75 SRII(PIXEL_RATE_CNTL, OTG, 3),\
76 SRII(PIXEL_RATE_CNTL, OTG, 4),\
77 SRII(PIXEL_RATE_CNTL, OTG, 5)
78
79#define CS_COMMON_REG_LIST_DCN201(index, pllid) \
80 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
81 SRII(PHASE, DP_DTO, 0),\
82 SRII(PHASE, DP_DTO, 1),\
83 SRII(MODULO, DP_DTO, 0),\
84 SRII(MODULO, DP_DTO, 1),\
85 SRII(PIXEL_RATE_CNTL, OTG, 0),\
86 SRII(PIXEL_RATE_CNTL, OTG, 1)
87
88#define CS_COMMON_REG_LIST_DCN2_1(index, pllid) \
89 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
90 SRII(PHASE, DP_DTO, 0),\
91 SRII(PHASE, DP_DTO, 1),\
92 SRII(PHASE, DP_DTO, 2),\
93 SRII(PHASE, DP_DTO, 3),\
94 SRII(MODULO, DP_DTO, 0),\
95 SRII(MODULO, DP_DTO, 1),\
96 SRII(MODULO, DP_DTO, 2),\
97 SRII(MODULO, DP_DTO, 3),\
98 SRII(PIXEL_RATE_CNTL, OTG, 0),\
99 SRII(PIXEL_RATE_CNTL, OTG, 1),\
100 SRII(PIXEL_RATE_CNTL, OTG, 2),\
101 SRII(PIXEL_RATE_CNTL, OTG, 3)
102
103#define CS_COMMON_REG_LIST_DCN3_0(index, pllid) \
104 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
105 SRII(PHASE, DP_DTO, 0),\
106 SRII(PHASE, DP_DTO, 1),\
107 SRII(PHASE, DP_DTO, 2),\
108 SRII(PHASE, DP_DTO, 3),\
109 SRII(MODULO, DP_DTO, 0),\
110 SRII(MODULO, DP_DTO, 1),\
111 SRII(MODULO, DP_DTO, 2),\
112 SRII(MODULO, DP_DTO, 3),\
113 SRII(PIXEL_RATE_CNTL, OTG, 0),\
114 SRII(PIXEL_RATE_CNTL, OTG, 1),\
115 SRII(PIXEL_RATE_CNTL, OTG, 2),\
116 SRII(PIXEL_RATE_CNTL, OTG, 3)
117
118#define CS_COMMON_REG_LIST_DCN3_01(index, pllid) \
119 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
120 SRII(PHASE, DP_DTO, 0),\
121 SRII(PHASE, DP_DTO, 1),\
122 SRII(PHASE, DP_DTO, 2),\
123 SRII(PHASE, DP_DTO, 3),\
124 SRII(MODULO, DP_DTO, 0),\
125 SRII(MODULO, DP_DTO, 1),\
126 SRII(MODULO, DP_DTO, 2),\
127 SRII(MODULO, DP_DTO, 3),\
128 SRII(PIXEL_RATE_CNTL, OTG, 0),\
129 SRII(PIXEL_RATE_CNTL, OTG, 1),\
130 SRII(PIXEL_RATE_CNTL, OTG, 2),\
131 SRII(PIXEL_RATE_CNTL, OTG, 3)
132
133#define CS_COMMON_REG_LIST_DCN3_02(index, pllid) \
134 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
135 SRII(PHASE, DP_DTO, 0),\
136 SRII(PHASE, DP_DTO, 1),\
137 SRII(PHASE, DP_DTO, 2),\
138 SRII(PHASE, DP_DTO, 3),\
139 SRII(PHASE, DP_DTO, 4),\
140 SRII(MODULO, DP_DTO, 0),\
141 SRII(MODULO, DP_DTO, 1),\
142 SRII(MODULO, DP_DTO, 2),\
143 SRII(MODULO, DP_DTO, 3),\
144 SRII(MODULO, DP_DTO, 4),\
145 SRII(PIXEL_RATE_CNTL, OTG, 0),\
146 SRII(PIXEL_RATE_CNTL, OTG, 1),\
147 SRII(PIXEL_RATE_CNTL, OTG, 2),\
148 SRII(PIXEL_RATE_CNTL, OTG, 3),\
149 SRII(PIXEL_RATE_CNTL, OTG, 4)
150
151#define CS_COMMON_REG_LIST_DCN3_03(index, pllid) \
152 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
153 SRII(PHASE, DP_DTO, 0),\
154 SRII(PHASE, DP_DTO, 1),\
155 SRII(MODULO, DP_DTO, 0),\
156 SRII(MODULO, DP_DTO, 1),\
157 SRII(PIXEL_RATE_CNTL, OTG, 0),\
158 SRII(PIXEL_RATE_CNTL, OTG, 1)
159
160#define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\
161 CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\
162 CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\
163 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
164 CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
165
166#define CS_COMMON_MASK_SH_LIST_DCN3_1_4(mask_sh)\
167 CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh),\
168 CS_SF(OTG0_PIXEL_RATE_CNTL, PIPE0_DTO_SRC_SEL, mask_sh),
169
170#define CS_COMMON_MASK_SH_LIST_DCN3_2(mask_sh)\
171 CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh),\
172 CS_SF(OTG0_PIXEL_RATE_CNTL, PIPE0_DTO_SRC_SEL, mask_sh)
173
174#define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \
175 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
176 SRII(PHASE, DP_DTO, 0),\
177 SRII(PHASE, DP_DTO, 1),\
178 SRII(PHASE, DP_DTO, 2),\
179 SRII(PHASE, DP_DTO, 3),\
180 SRII(MODULO, DP_DTO, 0),\
181 SRII(MODULO, DP_DTO, 1),\
182 SRII(MODULO, DP_DTO, 2),\
183 SRII(MODULO, DP_DTO, 3),\
184 SRII(PIXEL_RATE_CNTL, OTG, 0), \
185 SRII(PIXEL_RATE_CNTL, OTG, 1), \
186 SRII(PIXEL_RATE_CNTL, OTG, 2), \
187 SRII(PIXEL_RATE_CNTL, OTG, 3)
188
189#define CS_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
190 CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\
191 CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\
192 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
193 CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
194
195
196#define CS_REG_FIELD_LIST(type) \
197 type PLL_REF_DIV_SRC; \
198 type DCCG_DEEP_COLOR_CNTL1; \
199 type PHYPLLA_DCCG_DEEP_COLOR_CNTL; \
200 type PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE; \
201 type PLL_POST_DIV_PIXCLK; \
202 type PLL_REF_DIV; \
203 type DP_DTO0_PHASE; \
204 type DP_DTO0_MODULO; \
205 type DP_DTO0_ENABLE;
206
207#define CS_REG_FIELD_LIST_DCN32(type) \
208 type PIPE0_DTO_SRC_SEL;
209
210struct dce110_clk_src_shift {
211 CS_REG_FIELD_LIST(uint8_t)
212 CS_REG_FIELD_LIST_DCN32(uint8_t)
213};
214
215struct dce110_clk_src_mask{
216 CS_REG_FIELD_LIST(uint32_t)
217 CS_REG_FIELD_LIST_DCN32(uint32_t)
218};
219
220struct dce110_clk_src_regs {
221 uint32_t RESYNC_CNTL;
222 uint32_t PIXCLK_RESYNC_CNTL;
223 uint32_t PLL_CNTL;
224
225 /* below are for DTO.
226 * todo: should probably use different struct to not waste space
227 */
228 uint32_t PHASE[MAX_PIPES];
229 uint32_t MODULO[MAX_PIPES];
230 uint32_t PIXEL_RATE_CNTL[MAX_PIPES];
231};
232
233struct dce110_clk_src {
234 struct clock_source base;
235 const struct dce110_clk_src_regs *regs;
236 const struct dce110_clk_src_mask *cs_mask;
237 const struct dce110_clk_src_shift *cs_shift;
238 struct dc_bios *bios;
239
240 struct spread_spectrum_data *dp_ss_params;
241 uint32_t dp_ss_params_cnt;
242 struct spread_spectrum_data *hdmi_ss_params;
243 uint32_t hdmi_ss_params_cnt;
244 struct spread_spectrum_data *dvi_ss_params;
245 uint32_t dvi_ss_params_cnt;
246 struct spread_spectrum_data *lvds_ss_params;
247 uint32_t lvds_ss_params_cnt;
248
249 uint32_t ext_clk_khz;
250 uint32_t ref_freq_khz;
251
252 struct calc_pll_clock_source calc_pll;
253 struct calc_pll_clock_source calc_pll_hdmi;
254};
255
256bool dce110_clk_src_construct(
257 struct dce110_clk_src *clk_src,
258 struct dc_context *ctx,
259 struct dc_bios *bios,
260 enum clock_source_id id,
261 const struct dce110_clk_src_regs *regs,
262 const struct dce110_clk_src_shift *cs_shift,
263 const struct dce110_clk_src_mask *cs_mask);
264
265bool dce112_clk_src_construct(
266 struct dce110_clk_src *clk_src,
267 struct dc_context *ctx,
268 struct dc_bios *bios,
269 enum clock_source_id id,
270 const struct dce110_clk_src_regs *regs,
271 const struct dce110_clk_src_shift *cs_shift,
272 const struct dce110_clk_src_mask *cs_mask);
273
274bool dcn20_clk_src_construct(
275 struct dce110_clk_src *clk_src,
276 struct dc_context *ctx,
277 struct dc_bios *bios,
278 enum clock_source_id id,
279 const struct dce110_clk_src_regs *regs,
280 const struct dce110_clk_src_shift *cs_shift,
281 const struct dce110_clk_src_mask *cs_mask);
282
283bool dcn3_clk_src_construct(
284 struct dce110_clk_src *clk_src,
285 struct dc_context *ctx,
286 struct dc_bios *bios,
287 enum clock_source_id id,
288 const struct dce110_clk_src_regs *regs,
289 const struct dce110_clk_src_shift *cs_shift,
290 const struct dce110_clk_src_mask *cs_mask);
291
292bool dcn301_clk_src_construct(
293 struct dce110_clk_src *clk_src,
294 struct dc_context *ctx,
295 struct dc_bios *bios,
296 enum clock_source_id id,
297 const struct dce110_clk_src_regs *regs,
298 const struct dce110_clk_src_shift *cs_shift,
299 const struct dce110_clk_src_mask *cs_mask);
300
301bool dcn31_clk_src_construct(
302 struct dce110_clk_src *clk_src,
303 struct dc_context *ctx,
304 struct dc_bios *bios,
305 enum clock_source_id id,
306 const struct dce110_clk_src_regs *regs,
307 const struct dce110_clk_src_shift *cs_shift,
308 const struct dce110_clk_src_mask *cs_mask);
309
310bool dcn401_clk_src_construct(
311 struct dce110_clk_src *clk_src,
312 struct dc_context *ctx,
313 struct dc_bios *bios,
314 enum clock_source_id id,
315 const struct dce110_clk_src_regs *regs,
316 const struct dce110_clk_src_shift *cs_shift,
317 const struct dce110_clk_src_mask *cs_mask);
318/* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */
319struct pixel_rate_range_table_entry {
320 unsigned int range_min_khz;
321 unsigned int range_max_khz;
322 unsigned int target_pixel_rate_khz;
323 unsigned short mult_factor;
324 unsigned short div_factor;
325};
326
327extern const struct pixel_rate_range_table_entry video_optimized_pixel_rates[];
328const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb(
329 unsigned int pixel_rate_khz);
330
331#endif
332

source code of linux/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h