1/* SPDX-License-Identifier: GPL-2.0 OR MIT */
2/*
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef KFD_CRAT_H_INCLUDED
25#define KFD_CRAT_H_INCLUDED
26
27#include <linux/types.h>
28
29#pragma pack(1)
30
31/*
32 * 4CC signature value for the CRAT ACPI table
33 */
34
35#define CRAT_SIGNATURE "CRAT"
36
37/*
38 * Component Resource Association Table (CRAT)
39 */
40
41#define CRAT_OEMID_LENGTH 6
42#define CRAT_OEMTABLEID_LENGTH 8
43#define CRAT_RESERVED_LENGTH 6
44
45/* Compute Unit flags */
46#define COMPUTE_UNIT_CPU (1 << 0) /* Create Virtual CRAT for CPU */
47#define COMPUTE_UNIT_GPU (1 << 1) /* Create Virtual CRAT for GPU */
48
49struct crat_header {
50 uint32_t signature;
51 uint32_t length;
52 uint8_t revision;
53 uint8_t checksum;
54 uint8_t oem_id[CRAT_OEMID_LENGTH];
55 uint8_t oem_table_id[CRAT_OEMTABLEID_LENGTH];
56 uint32_t oem_revision;
57 uint32_t creator_id;
58 uint32_t creator_revision;
59 uint32_t total_entries;
60 uint16_t num_domains;
61 uint8_t reserved[CRAT_RESERVED_LENGTH];
62};
63
64/*
65 * The header structure is immediately followed by total_entries of the
66 * data definitions
67 */
68
69/*
70 * The currently defined subtype entries in the CRAT
71 */
72#define CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY 0
73#define CRAT_SUBTYPE_MEMORY_AFFINITY 1
74#define CRAT_SUBTYPE_CACHE_AFFINITY 2
75#define CRAT_SUBTYPE_TLB_AFFINITY 3
76#define CRAT_SUBTYPE_CCOMPUTE_AFFINITY 4
77#define CRAT_SUBTYPE_IOLINK_AFFINITY 5
78#define CRAT_SUBTYPE_MAX 6
79
80/*
81 * Do not change the value of CRAT_SIBLINGMAP_SIZE from 32
82 * as it breaks the ABI.
83 */
84#define CRAT_SIBLINGMAP_SIZE 32
85
86/*
87 * ComputeUnit Affinity structure and definitions
88 */
89#define CRAT_CU_FLAGS_ENABLED 0x00000001
90#define CRAT_CU_FLAGS_HOT_PLUGGABLE 0x00000002
91#define CRAT_CU_FLAGS_CPU_PRESENT 0x00000004
92#define CRAT_CU_FLAGS_GPU_PRESENT 0x00000008
93#define CRAT_CU_FLAGS_IOMMU_PRESENT 0x00000010
94#define CRAT_CU_FLAGS_RESERVED 0xffffffe0
95
96#define CRAT_COMPUTEUNIT_RESERVED_LENGTH 4
97
98struct crat_subtype_computeunit {
99 uint8_t type;
100 uint8_t length;
101 uint16_t reserved;
102 uint32_t flags;
103 uint32_t proximity_domain;
104 uint32_t processor_id_low;
105 uint16_t num_cpu_cores;
106 uint16_t num_simd_cores;
107 uint16_t max_waves_simd;
108 uint16_t io_count;
109 uint16_t hsa_capability;
110 uint16_t lds_size_in_kb;
111 uint8_t wave_front_size;
112 uint8_t num_banks;
113 uint16_t micro_engine_id;
114 uint8_t array_count;
115 uint8_t num_cu_per_array;
116 uint8_t num_simd_per_cu;
117 uint8_t max_slots_scatch_cu;
118 uint8_t reserved2[CRAT_COMPUTEUNIT_RESERVED_LENGTH];
119};
120
121/*
122 * HSA Memory Affinity structure and definitions
123 */
124#define CRAT_MEM_FLAGS_ENABLED 0x00000001
125#define CRAT_MEM_FLAGS_HOT_PLUGGABLE 0x00000002
126#define CRAT_MEM_FLAGS_NON_VOLATILE 0x00000004
127#define CRAT_MEM_FLAGS_RESERVED 0xfffffff8
128
129#define CRAT_MEMORY_RESERVED_LENGTH 8
130
131struct crat_subtype_memory {
132 uint8_t type;
133 uint8_t length;
134 uint16_t reserved;
135 uint32_t flags;
136 uint32_t proximity_domain;
137 uint32_t base_addr_low;
138 uint32_t base_addr_high;
139 uint32_t length_low;
140 uint32_t length_high;
141 uint32_t width;
142 uint8_t visibility_type; /* for virtual (dGPU) CRAT */
143 uint8_t reserved2[CRAT_MEMORY_RESERVED_LENGTH - 1];
144};
145
146/*
147 * HSA Cache Affinity structure and definitions
148 */
149#define CRAT_CACHE_FLAGS_ENABLED 0x00000001
150#define CRAT_CACHE_FLAGS_DATA_CACHE 0x00000002
151#define CRAT_CACHE_FLAGS_INST_CACHE 0x00000004
152#define CRAT_CACHE_FLAGS_CPU_CACHE 0x00000008
153#define CRAT_CACHE_FLAGS_SIMD_CACHE 0x00000010
154#define CRAT_CACHE_FLAGS_RESERVED 0xffffffe0
155
156#define CRAT_CACHE_RESERVED_LENGTH 8
157
158struct crat_subtype_cache {
159 uint8_t type;
160 uint8_t length;
161 uint16_t reserved;
162 uint32_t flags;
163 uint32_t processor_id_low;
164 uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE];
165 uint32_t cache_size;
166 uint8_t cache_level;
167 uint8_t lines_per_tag;
168 uint16_t cache_line_size;
169 uint8_t associativity;
170 uint8_t cache_properties;
171 uint16_t cache_latency;
172 uint8_t reserved2[CRAT_CACHE_RESERVED_LENGTH];
173};
174
175/*
176 * HSA TLB Affinity structure and definitions
177 */
178#define CRAT_TLB_FLAGS_ENABLED 0x00000001
179#define CRAT_TLB_FLAGS_DATA_TLB 0x00000002
180#define CRAT_TLB_FLAGS_INST_TLB 0x00000004
181#define CRAT_TLB_FLAGS_CPU_TLB 0x00000008
182#define CRAT_TLB_FLAGS_SIMD_TLB 0x00000010
183#define CRAT_TLB_FLAGS_RESERVED 0xffffffe0
184
185#define CRAT_TLB_RESERVED_LENGTH 4
186
187struct crat_subtype_tlb {
188 uint8_t type;
189 uint8_t length;
190 uint16_t reserved;
191 uint32_t flags;
192 uint32_t processor_id_low;
193 uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE];
194 uint32_t tlb_level;
195 uint8_t data_tlb_associativity_2mb;
196 uint8_t data_tlb_size_2mb;
197 uint8_t instruction_tlb_associativity_2mb;
198 uint8_t instruction_tlb_size_2mb;
199 uint8_t data_tlb_associativity_4k;
200 uint8_t data_tlb_size_4k;
201 uint8_t instruction_tlb_associativity_4k;
202 uint8_t instruction_tlb_size_4k;
203 uint8_t data_tlb_associativity_1gb;
204 uint8_t data_tlb_size_1gb;
205 uint8_t instruction_tlb_associativity_1gb;
206 uint8_t instruction_tlb_size_1gb;
207 uint8_t reserved2[CRAT_TLB_RESERVED_LENGTH];
208};
209
210/*
211 * HSA CCompute/APU Affinity structure and definitions
212 */
213#define CRAT_CCOMPUTE_FLAGS_ENABLED 0x00000001
214#define CRAT_CCOMPUTE_FLAGS_RESERVED 0xfffffffe
215
216#define CRAT_CCOMPUTE_RESERVED_LENGTH 16
217
218struct crat_subtype_ccompute {
219 uint8_t type;
220 uint8_t length;
221 uint16_t reserved;
222 uint32_t flags;
223 uint32_t processor_id_low;
224 uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE];
225 uint32_t apu_size;
226 uint8_t reserved2[CRAT_CCOMPUTE_RESERVED_LENGTH];
227};
228
229/*
230 * HSA IO Link Affinity structure and definitions
231 */
232#define CRAT_IOLINK_FLAGS_ENABLED (1 << 0)
233#define CRAT_IOLINK_FLAGS_NON_COHERENT (1 << 1)
234#define CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT (1 << 2)
235#define CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT (1 << 3)
236#define CRAT_IOLINK_FLAGS_NO_PEER_TO_PEER_DMA (1 << 4)
237#define CRAT_IOLINK_FLAGS_BI_DIRECTIONAL (1 << 31)
238#define CRAT_IOLINK_FLAGS_RESERVED_MASK 0x7fffffe0
239
240/*
241 * IO interface types
242 */
243#define CRAT_IOLINK_TYPE_UNDEFINED 0
244#define CRAT_IOLINK_TYPE_HYPERTRANSPORT 1
245#define CRAT_IOLINK_TYPE_PCIEXPRESS 2
246#define CRAT_IOLINK_TYPE_AMBA 3
247#define CRAT_IOLINK_TYPE_MIPI 4
248#define CRAT_IOLINK_TYPE_QPI_1_1 5
249#define CRAT_IOLINK_TYPE_RESERVED1 6
250#define CRAT_IOLINK_TYPE_RESERVED2 7
251#define CRAT_IOLINK_TYPE_RAPID_IO 8
252#define CRAT_IOLINK_TYPE_INFINIBAND 9
253#define CRAT_IOLINK_TYPE_RESERVED3 10
254#define CRAT_IOLINK_TYPE_XGMI 11
255#define CRAT_IOLINK_TYPE_XGOP 12
256#define CRAT_IOLINK_TYPE_GZ 13
257#define CRAT_IOLINK_TYPE_ETHERNET_RDMA 14
258#define CRAT_IOLINK_TYPE_RDMA_OTHER 15
259#define CRAT_IOLINK_TYPE_OTHER 16
260#define CRAT_IOLINK_TYPE_MAX 255
261
262#define CRAT_IOLINK_RESERVED_LENGTH 24
263
264struct crat_subtype_iolink {
265 uint8_t type;
266 uint8_t length;
267 uint16_t reserved;
268 uint32_t flags;
269 uint32_t proximity_domain_from;
270 uint32_t proximity_domain_to;
271 uint8_t io_interface_type;
272 uint8_t version_major;
273 uint16_t version_minor;
274 uint32_t minimum_latency;
275 uint32_t maximum_latency;
276 uint32_t minimum_bandwidth_mbs;
277 uint32_t maximum_bandwidth_mbs;
278 uint32_t recommended_transfer_size;
279 uint8_t reserved2[CRAT_IOLINK_RESERVED_LENGTH - 1];
280 uint8_t weight_xgmi;
281};
282
283/*
284 * HSA generic sub-type header
285 */
286
287#define CRAT_SUBTYPE_FLAGS_ENABLED 0x00000001
288
289struct crat_subtype_generic {
290 uint8_t type;
291 uint8_t length;
292 uint16_t reserved;
293 uint32_t flags;
294};
295
296#pragma pack()
297
298struct kfd_node;
299
300/* Static table to describe GPU Cache information */
301struct kfd_gpu_cache_info {
302 uint32_t cache_size;
303 uint32_t cache_level;
304 uint32_t cache_line_size;
305 uint32_t flags;
306 /* Indicates how many Compute Units share this cache
307 * within a SA. Value = 1 indicates the cache is not shared
308 */
309 uint32_t num_cu_shared;
310};
311int kfd_get_gpu_cache_info(struct kfd_node *kdev, struct kfd_gpu_cache_info **pcache_info);
312
313void kfd_destroy_crat_image(void *crat_image);
314int kfd_parse_crat_table(void *crat_image, struct list_head *device_list,
315 uint32_t proximity_domain);
316int kfd_create_crat_image_virtual(void **crat_image, size_t *size,
317 int flags, struct kfd_node *kdev,
318 uint32_t proximity_domain);
319
320#endif /* KFD_CRAT_H_INCLUDED */
321

source code of linux/drivers/gpu/drm/amd/amdkfd/kfd_crat.h