1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef _TA_RAS_IF_H
25#define _TA_RAS_IF_H
26
27#define RAS_TA_HOST_IF_VER 0
28
29/* Responses have bit 31 set */
30#define RSP_ID_MASK (1U << 31)
31#define RSP_ID(cmdId) (((uint32_t)(cmdId)) | RSP_ID_MASK)
32
33/* invalid node instance value */
34#define TA_RAS_INV_NODE 0xffff
35
36/* RAS related enumerations */
37/**********************************************************/
38enum ras_command {
39 TA_RAS_COMMAND__ENABLE_FEATURES = 0,
40 TA_RAS_COMMAND__DISABLE_FEATURES,
41 TA_RAS_COMMAND__TRIGGER_ERROR,
42 TA_RAS_COMMAND__QUERY_BLOCK_INFO,
43 TA_RAS_COMMAND__QUERY_SUB_BLOCK_INFO,
44 TA_RAS_COMMAND__QUERY_ADDRESS,
45};
46
47enum ta_ras_status {
48 TA_RAS_STATUS__SUCCESS = 0x0000,
49 TA_RAS_STATUS__RESET_NEEDED = 0xA001,
50 TA_RAS_STATUS__ERROR_INVALID_PARAMETER = 0xA002,
51 TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE = 0xA003,
52 TA_RAS_STATUS__ERROR_RAS_DUPLICATE_CMD = 0xA004,
53 TA_RAS_STATUS__ERROR_INJECTION_FAILED = 0xA005,
54 TA_RAS_STATUS__ERROR_ASD_READ_WRITE = 0xA006,
55 TA_RAS_STATUS__ERROR_TOGGLE_DF_CSTATE = 0xA007,
56 TA_RAS_STATUS__ERROR_TIMEOUT = 0xA008,
57 TA_RAS_STATUS__ERROR_BLOCK_DISABLED = 0XA009,
58 TA_RAS_STATUS__ERROR_GENERIC = 0xA00A,
59 TA_RAS_STATUS__ERROR_RAS_MMHUB_INIT = 0xA00B,
60 TA_RAS_STATUS__ERROR_GET_DEV_INFO = 0xA00C,
61 TA_RAS_STATUS__ERROR_UNSUPPORTED_DEV = 0xA00D,
62 TA_RAS_STATUS__ERROR_NOT_INITIALIZED = 0xA00E,
63 TA_RAS_STATUS__ERROR_TEE_INTERNAL = 0xA00F,
64 TA_RAS_STATUS__ERROR_UNSUPPORTED_FUNCTION = 0xA010,
65 TA_RAS_STATUS__ERROR_SYS_DRV_REG_ACCESS = 0xA011,
66 TA_RAS_STATUS__ERROR_RAS_READ_WRITE = 0xA012,
67 TA_RAS_STATUS__ERROR_NULL_PTR = 0xA013,
68 TA_RAS_STATUS__ERROR_UNSUPPORTED_IP = 0xA014,
69 TA_RAS_STATUS__ERROR_PCS_STATE_QUIET = 0xA015,
70 TA_RAS_STATUS__ERROR_PCS_STATE_ERROR = 0xA016,
71 TA_RAS_STATUS__ERROR_PCS_STATE_HANG = 0xA017,
72 TA_RAS_STATUS__ERROR_PCS_STATE_UNKNOWN = 0xA018,
73 TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ = 0xA019,
74 TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED = 0xA01A
75};
76
77enum ta_ras_block {
78 TA_RAS_BLOCK__UMC = 0,
79 TA_RAS_BLOCK__SDMA,
80 TA_RAS_BLOCK__GFX,
81 TA_RAS_BLOCK__MMHUB,
82 TA_RAS_BLOCK__ATHUB,
83 TA_RAS_BLOCK__PCIE_BIF,
84 TA_RAS_BLOCK__HDP,
85 TA_RAS_BLOCK__XGMI_WAFL,
86 TA_RAS_BLOCK__DF,
87 TA_RAS_BLOCK__SMN,
88 TA_RAS_BLOCK__SEM,
89 TA_RAS_BLOCK__MP0,
90 TA_RAS_BLOCK__MP1,
91 TA_RAS_BLOCK__FUSE,
92 TA_RAS_BLOCK__MCA,
93 TA_RAS_BLOCK__VCN,
94 TA_RAS_BLOCK__JPEG,
95 TA_RAS_BLOCK__IH,
96 TA_RAS_BLOCK__MPIO,
97 TA_RAS_BLOCK__MMSCH,
98 TA_NUM_BLOCK_MAX
99};
100
101enum ta_ras_mca_block {
102 TA_RAS_MCA_BLOCK__MP0 = 0,
103 TA_RAS_MCA_BLOCK__MP1 = 1,
104 TA_RAS_MCA_BLOCK__MPIO = 2,
105 TA_RAS_MCA_BLOCK__IOHC = 3,
106 TA_MCA_NUM_BLOCK_MAX
107};
108
109enum ta_ras_error_type {
110 TA_RAS_ERROR__NONE = 0,
111 TA_RAS_ERROR__PARITY = 1,
112 TA_RAS_ERROR__SINGLE_CORRECTABLE = 2,
113 TA_RAS_ERROR__MULTI_UNCORRECTABLE = 4,
114 TA_RAS_ERROR__POISON = 8,
115};
116
117enum ta_ras_address_type {
118 TA_RAS_MCA_TO_PA,
119 TA_RAS_PA_TO_MCA,
120};
121
122enum ta_ras_nps_mode {
123 TA_RAS_UNKNOWN_MODE = 0,
124 TA_RAS_NPS1_MODE = 1,
125 TA_RAS_NPS2_MODE = 2,
126 TA_RAS_NPS4_MODE = 4,
127 TA_RAS_NPS8_MODE = 8,
128};
129
130/* Input/output structures for RAS commands */
131/**********************************************************/
132
133struct ta_ras_enable_features_input {
134 enum ta_ras_block block_id;
135 enum ta_ras_error_type error_type;
136};
137
138struct ta_ras_disable_features_input {
139 enum ta_ras_block block_id;
140 enum ta_ras_error_type error_type;
141};
142
143struct ta_ras_trigger_error_input {
144 enum ta_ras_block block_id; // ras-block. i.e. umc, gfx
145 enum ta_ras_error_type inject_error_type; // type of error. i.e. single_correctable
146 uint32_t sub_block_index; // mem block. i.e. hbm, sram etc.
147 uint64_t address; // explicit address of error
148 uint64_t value; // method if error injection. i.e persistent, coherent etc.
149};
150
151struct ta_ras_init_flags {
152 uint8_t poison_mode_en;
153 uint8_t dgpu_mode;
154 uint16_t xcc_mask;
155 uint8_t channel_dis_num;
156 uint8_t nps_mode;
157 uint32_t active_umc_mask;
158};
159
160struct ta_ras_mca_addr {
161 uint64_t err_addr;
162 uint32_t ch_inst;
163 uint32_t umc_inst;
164 uint32_t node_inst;
165 uint32_t socket_id;
166};
167
168struct ta_ras_phy_addr {
169 uint64_t pa;
170 uint32_t bank;
171 uint32_t channel_idx;
172};
173
174struct ta_ras_query_address_input {
175 enum ta_ras_address_type addr_type;
176 struct ta_ras_mca_addr ma;
177 struct ta_ras_phy_addr pa;
178};
179
180struct ta_ras_output_flags {
181 uint8_t ras_init_success_flag;
182 uint8_t err_inject_switch_disable_flag;
183 uint8_t reg_access_failure_flag;
184};
185
186struct ta_ras_query_address_output {
187 /* don't use the flags here */
188 struct ta_ras_output_flags flags;
189 struct ta_ras_mca_addr ma;
190 struct ta_ras_phy_addr pa;
191};
192
193/* Common input structure for RAS callbacks */
194/**********************************************************/
195union ta_ras_cmd_input {
196 struct ta_ras_init_flags init_flags;
197 struct ta_ras_enable_features_input enable_features;
198 struct ta_ras_disable_features_input disable_features;
199 struct ta_ras_trigger_error_input trigger_error;
200 struct ta_ras_query_address_input address;
201
202 uint32_t reserve_pad[256];
203};
204
205union ta_ras_cmd_output {
206 struct ta_ras_output_flags flags;
207 struct ta_ras_query_address_output address;
208
209 uint32_t reserve_pad[256];
210};
211
212/* Shared Memory structures */
213/**********************************************************/
214struct ta_ras_shared_memory {
215 uint32_t cmd_id;
216 uint32_t resp_id;
217 uint32_t ras_status;
218 uint32_t if_version;
219 union ta_ras_cmd_input ras_in_message;
220 union ta_ras_cmd_output ras_out_message;
221};
222
223#endif // TL_RAS_IF_H_
224

source code of linux/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h