| 1 | /* |
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| 2 | * Copyright 2016 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | */ |
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| 23 | |
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| 24 | #ifndef __SOC15_COMMON_H__ |
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| 25 | #define __SOC15_COMMON_H__ |
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| 26 | |
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| 27 | /* GET_INST returns the physical instance corresponding to a logical instance */ |
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| 28 | #define GET_INST(ip, inst) \ |
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| 29 | (adev->ip_map.logical_to_dev_inst ? \ |
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| 30 | adev->ip_map.logical_to_dev_inst(adev, ip##_HWIP, inst) : inst) |
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| 31 | #define GET_MASK(ip, mask) \ |
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| 32 | (adev->ip_map.logical_to_dev_mask ? \ |
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| 33 | adev->ip_map.logical_to_dev_mask(adev, ip##_HWIP, mask) : mask) |
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| 34 | |
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| 35 | /* Register Access Macros */ |
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| 36 | #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) |
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| 37 | #define SOC15_REG_OFFSET1(ip, inst, reg, offset) \ |
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| 38 | (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)+(offset)) |
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| 39 | |
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| 40 | #define __WREG32_SOC15_RLC__(reg, value, flag, hwip, inst) \ |
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| 41 | ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? \ |
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| 42 | amdgpu_sriov_wreg(adev, reg, value, flag, hwip, inst) : \ |
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| 43 | WREG32(reg, value)) |
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| 44 | |
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| 45 | #define __RREG32_SOC15_RLC__(reg, flag, hwip, inst) \ |
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| 46 | ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? \ |
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| 47 | amdgpu_sriov_rreg(adev, reg, flag, hwip, inst) : \ |
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| 48 | RREG32(reg)) |
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| 49 | |
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| 50 | #define WREG32_FIELD15(ip, idx, reg, field, val) \ |
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| 51 | __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \ |
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| 52 | (__RREG32_SOC15_RLC__( \ |
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| 53 | adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \ |
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| 54 | 0, ip##_HWIP, idx) & \ |
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| 55 | ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \ |
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| 56 | 0, ip##_HWIP, idx) |
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| 57 | |
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| 58 | #define WREG32_FIELD15_PREREG(ip, idx, reg_name, field, val) \ |
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| 59 | __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, \ |
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| 60 | (__RREG32_SOC15_RLC__( \ |
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| 61 | adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, \ |
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| 62 | 0, ip##_HWIP, idx) & \ |
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| 63 | ~REG_FIELD_MASK(reg_name, field)) | (val) << REG_FIELD_SHIFT(reg_name, field), \ |
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| 64 | 0, ip##_HWIP, idx) |
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| 65 | |
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| 66 | #define RREG32_SOC15(ip, inst, reg) \ |
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| 67 | __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \ |
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| 68 | 0, ip##_HWIP, inst) |
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| 69 | |
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| 70 | #define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP, 0) |
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| 71 | |
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| 72 | #define RREG32_SOC15_IP_NO_KIQ(ip, reg, inst) __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ, ip##_HWIP, inst) |
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| 73 | |
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| 74 | #define RREG32_SOC15_NO_KIQ(ip, inst, reg) \ |
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| 75 | __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \ |
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| 76 | AMDGPU_REGS_NO_KIQ, ip##_HWIP, inst) |
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| 77 | |
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| 78 | #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \ |
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| 79 | __RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)) + \ |
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| 80 | (offset), 0, ip##_HWIP, inst) |
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| 81 | |
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| 82 | #define WREG32_SOC15(ip, inst, reg, value) \ |
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| 83 | __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \ |
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| 84 | value, 0, ip##_HWIP, inst) |
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| 85 | |
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| 86 | #define WREG32_SOC15_IP(ip, reg, value) \ |
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| 87 | __WREG32_SOC15_RLC__(reg, value, 0, ip##_HWIP, 0) |
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| 88 | |
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| 89 | #define WREG32_SOC15_IP_NO_KIQ(ip, reg, value, inst) \ |
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| 90 | __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ, ip##_HWIP, inst) |
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| 91 | |
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| 92 | #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \ |
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| 93 | __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \ |
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| 94 | value, AMDGPU_REGS_NO_KIQ, ip##_HWIP, inst) |
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| 95 | |
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| 96 | #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \ |
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| 97 | __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, \ |
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| 98 | value, 0, ip##_HWIP, inst) |
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| 99 | |
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| 100 | #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \ |
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| 101 | amdgpu_device_wait_on_rreg(adev, inst, \ |
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| 102 | (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)), \ |
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| 103 | #reg, expected_value, mask) |
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| 104 | |
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| 105 | #define SOC15_WAIT_ON_RREG_OFFSET(ip, inst, reg, offset, expected_value, mask) \ |
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| 106 | amdgpu_device_wait_on_rreg(adev, inst, \ |
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| 107 | (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg) + (offset)), \ |
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| 108 | #reg, expected_value, mask) |
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| 109 | |
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| 110 | #define WREG32_RLC(reg, value) \ |
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| 111 | __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_RLC, GC_HWIP, 0) |
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| 112 | |
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| 113 | #define WREG32_RLC_EX(prefix, reg, value, inst) \ |
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| 114 | do { \ |
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| 115 | if (amdgpu_sriov_fullaccess(adev)) { \ |
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| 116 | uint32_t i = 0; \ |
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| 117 | uint32_t retries = 50000; \ |
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| 118 | uint32_t r0 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG0_BASE_IDX] + prefix##SCRATCH_REG0; \ |
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| 119 | uint32_t r1 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG1; \ |
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| 120 | uint32_t spare_int = adev->reg_offset[GC_HWIP][inst][prefix##RLC_SPARE_INT_BASE_IDX] + prefix##RLC_SPARE_INT; \ |
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| 121 | WREG32(r0, value); \ |
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| 122 | WREG32(r1, (reg | 0x80000000)); \ |
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| 123 | WREG32(spare_int, 0x1); \ |
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| 124 | for (i = 0; i < retries; i++) { \ |
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| 125 | u32 tmp = RREG32(r1); \ |
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| 126 | if (!(tmp & 0x80000000)) \ |
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| 127 | break; \ |
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| 128 | udelay(10); \ |
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| 129 | } \ |
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| 130 | if (i >= retries) \ |
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| 131 | pr_err("timeout: rlcg program reg:0x%05x failed !\n", reg); \ |
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| 132 | } else { \ |
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| 133 | WREG32(reg, value); \ |
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| 134 | } \ |
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| 135 | } while (0) |
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| 136 | |
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| 137 | /* shadow the registers in the callback function */ |
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| 138 | #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \ |
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| 139 | __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value, AMDGPU_REGS_RLC, GC_HWIP, inst) |
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| 140 | |
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| 141 | /* for GC only */ |
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| 142 | #define RREG32_RLC(reg) \ |
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| 143 | __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP, 0) |
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| 144 | |
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| 145 | #define WREG32_RLC_NO_KIQ(reg, value, hwip) \ |
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| 146 | __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip, 0) |
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| 147 | |
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| 148 | #define RREG32_RLC_NO_KIQ(reg, hwip) \ |
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| 149 | __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip, 0) |
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| 150 | |
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| 151 | #define WREG32_SOC15_RLC_SHADOW_EX(prefix, ip, inst, reg, value) \ |
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| 152 | do { \ |
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| 153 | uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\ |
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| 154 | if (amdgpu_sriov_fullaccess(adev)) { \ |
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| 155 | uint32_t r2 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG2; \ |
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| 156 | uint32_t r3 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG3; \ |
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| 157 | uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][inst][prefix##GRBM_GFX_CNTL_BASE_IDX] + prefix##GRBM_GFX_CNTL; \ |
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| 158 | uint32_t grbm_idx = adev->reg_offset[GC_HWIP][inst][prefix##GRBM_GFX_INDEX_BASE_IDX] + prefix##GRBM_GFX_INDEX; \ |
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| 159 | if (target_reg == grbm_cntl) \ |
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| 160 | WREG32(r2, value); \ |
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| 161 | else if (target_reg == grbm_idx) \ |
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| 162 | WREG32(r3, value); \ |
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| 163 | WREG32(target_reg, value); \ |
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| 164 | } else { \ |
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| 165 | WREG32(target_reg, value); \ |
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| 166 | } \ |
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| 167 | } while (0) |
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| 168 | |
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| 169 | #define RREG32_SOC15_RLC(ip, inst, reg) \ |
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| 170 | __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, AMDGPU_REGS_RLC, ip##_HWIP, inst) |
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| 171 | |
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| 172 | #define WREG32_SOC15_RLC(ip, inst, reg, value) \ |
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| 173 | do { \ |
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| 174 | uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\ |
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| 175 | __WREG32_SOC15_RLC__(target_reg, value, AMDGPU_REGS_RLC, ip##_HWIP, inst); \ |
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| 176 | } while (0) |
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| 177 | |
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| 178 | #define WREG32_SOC15_RLC_EX(prefix, ip, inst, reg, value) \ |
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| 179 | do { \ |
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| 180 | uint32_t target_reg = adev->reg_offset[GC_HWIP][inst][reg##_BASE_IDX] + reg;\ |
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| 181 | WREG32_RLC_EX(prefix, target_reg, value, inst); \ |
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| 182 | } while (0) |
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| 183 | |
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| 184 | #define WREG32_FIELD15_RLC(ip, idx, reg, field, val) \ |
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| 185 | __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \ |
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| 186 | (__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \ |
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| 187 | AMDGPU_REGS_RLC, ip##_HWIP, idx) & \ |
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| 188 | ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \ |
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| 189 | AMDGPU_REGS_RLC, ip##_HWIP, idx) |
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| 190 | |
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| 191 | #define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \ |
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| 192 | __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value, AMDGPU_REGS_RLC, ip##_HWIP, inst) |
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| 193 | |
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| 194 | #define RREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset) \ |
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| 195 | __RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, AMDGPU_REGS_RLC, ip##_HWIP, inst) |
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| 196 | |
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| 197 | /* inst equals to ext for some IPs */ |
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| 198 | #define RREG32_SOC15_EXT(ip, inst, reg, ext) \ |
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| 199 | RREG32_PCIE_EXT((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) * 4 \ |
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| 200 | + adev->asic_funcs->encode_ext_smn_addressing(ext)) \ |
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| 201 | |
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| 202 | #define WREG32_SOC15_EXT(ip, inst, reg, ext, value) \ |
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| 203 | WREG32_PCIE_EXT((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) * 4 \ |
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| 204 | + adev->asic_funcs->encode_ext_smn_addressing(ext), \ |
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| 205 | value) \ |
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| 206 | |
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| 207 | #define RREG64_MCA(ext, mca_base, idx) \ |
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| 208 | RREG64_PCIE_EXT(adev->asic_funcs->encode_ext_smn_addressing(ext) + mca_base + (idx * 8)) |
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| 209 | |
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| 210 | #define WREG64_MCA(ext, mca_base, idx, val) \ |
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| 211 | WREG64_PCIE_EXT(adev->asic_funcs->encode_ext_smn_addressing(ext) + mca_base + (idx * 8), val) |
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| 212 | |
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| 213 | #endif |
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| 214 | |
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