| 1 | /* |
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| 2 | * Copyright 2019 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | */ |
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| 23 | |
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| 24 | #ifndef __JPEG_V2_0_H__ |
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| 25 | #define __JPEG_V2_0_H__ |
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| 26 | |
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| 27 | #define mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET 0x1bfff |
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| 28 | #define mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET 0x4029 |
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| 29 | #define mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET 0x402a |
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| 30 | #define mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET 0x402b |
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| 31 | #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ea |
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| 32 | #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40eb |
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| 33 | #define mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET 0x40cf |
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| 34 | #define mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET 0x40d1 |
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| 35 | #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40e8 |
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| 36 | #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40e9 |
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| 37 | #define mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET 0x4082 |
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| 38 | #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ec |
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| 39 | #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40ed |
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| 40 | #define mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET 0x4085 |
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| 41 | #define mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET 0x4084 |
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| 42 | #define mmUVD_JRBC_STATUS_INTERNAL_OFFSET 0x4089 |
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| 43 | #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f |
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| 44 | #define mmUVD_JPEG_IH_CTRL_INTERNAL_OFFSET 0x4149 |
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| 45 | |
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| 46 | #define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x18000 |
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| 47 | |
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| 48 | void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring); |
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| 49 | void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring); |
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| 50 | void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, |
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| 51 | unsigned flags); |
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| 52 | void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job, |
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| 53 | struct amdgpu_ib *ib, uint32_t flags); |
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| 54 | void jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, |
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| 55 | uint32_t val, uint32_t mask); |
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| 56 | void jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, |
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| 57 | unsigned vmid, uint64_t pd_addr); |
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| 58 | void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); |
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| 59 | void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count); |
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| 60 | |
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| 61 | extern const struct amdgpu_ip_block_version jpeg_v2_0_ip_block; |
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| 62 | |
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| 63 | #endif /* __JPEG_V2_0_H__ */ |
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| 64 | |
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