1/*
2 * Copyright (c) 2018-2021 Advanced Micro Devices, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
21 */
22
23#ifndef AMDGV_SRIOV_MSG__H_
24#define AMDGV_SRIOV_MSG__H_
25
26#define AMD_SRIOV_MSG_SIZE_KB 1
27
28/*
29 * layout v1
30 * 0 64KB 65KB 66KB 68KB 132KB
31 * | VBIOS | PF2VF | VF2PF | Bad Page | RAS Telemetry Region | ...
32 * | 64KB | 1KB | 1KB | 2KB | 64KB | ...
33 */
34
35/*
36 * layout v2 (offsets are dynamically allocated and the offsets below are examples)
37 * 0 1KB 64KB 65KB 66KB 68KB 132KB
38 * | INITD_H | VBIOS | PF2VF | VF2PF | Bad Page | RAS Telemetry Region | ...
39 * | 1KB | 64KB | 1KB | 1KB | 2KB | 64KB | ...
40 *
41 * Note: PF2VF + VF2PF + Bad Page = DataExchange region (allocated contiguously)
42 */
43
44/* v1 layout sizes */
45#define AMD_SRIOV_MSG_VBIOS_SIZE_KB_V1 64
46#define AMD_SRIOV_MSG_PF2VF_SIZE_KB_V1 1
47#define AMD_SRIOV_MSG_VF2PF_SIZE_KB_V1 1
48#define AMD_SRIOV_MSG_BAD_PAGE_SIZE_KB_V1 2
49#define AMD_SRIOV_MSG_RAS_TELEMETRY_SIZE_KB_V1 64
50#define AMD_SRIOV_MSG_DATAEXCHANGE_SIZE_KB_V1 \
51 (AMD_SRIOV_MSG_PF2VF_SIZE_KB_V1 + AMD_SRIOV_MSG_VF2PF_SIZE_KB_V1 + \
52 AMD_SRIOV_MSG_BAD_PAGE_SIZE_KB_V1)
53
54/* v1 offsets */
55#define AMD_SRIOV_MSG_VBIOS_OFFSET_V1 0
56#define AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB_V1 AMD_SRIOV_MSG_VBIOS_SIZE_KB_V1
57#define AMD_SRIOV_MSG_TMR_OFFSET_KB 2048
58#define AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB_V1
59#define AMD_SRIOV_MSG_VF2PF_OFFSET_KB_V1 \
60 (AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 + AMD_SRIOV_MSG_SIZE_KB)
61#define AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB_V1 \
62 (AMD_SRIOV_MSG_VF2PF_OFFSET_KB_V1 + AMD_SRIOV_MSG_SIZE_KB)
63#define AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB_V1 \
64 (AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB_V1 + AMD_SRIOV_MSG_BAD_PAGE_SIZE_KB_V1)
65#define AMD_SRIOV_MSG_INIT_DATA_TOT_SIZE_KB_V1 \
66 (AMD_SRIOV_MSG_VBIOS_SIZE_KB_V1 + AMD_SRIOV_MSG_DATAEXCHANGE_SIZE_KB_V1 + \
67 AMD_SRIOV_MSG_RAS_TELEMETRY_SIZE_KB_V1)
68
69enum amd_sriov_crit_region_version {
70 GPU_CRIT_REGION_V1 = 1,
71 GPU_CRIT_REGION_V2 = 2,
72};
73
74/* v2 layout offset enum (in order of allocation) */
75enum amd_sriov_msg_table_id_enum {
76 AMD_SRIOV_MSG_IPD_TABLE_ID = 0,
77 AMD_SRIOV_MSG_VBIOS_IMG_TABLE_ID,
78 AMD_SRIOV_MSG_RAS_TELEMETRY_TABLE_ID,
79 AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID,
80 AMD_SRIOV_MSG_BAD_PAGE_INFO_TABLE_ID,
81 AMD_SRIOV_MSG_INITD_H_TABLE_ID,
82 AMD_SRIOV_MSG_MAX_TABLE_ID,
83};
84
85struct amd_sriov_msg_init_data_header {
86 char signature[4]; /* "INDA" */
87 uint32_t version;
88 uint32_t checksum;
89 uint32_t initdata_offset; /* 0 */
90 uint32_t initdata_size_in_kb; /* 5MB */
91 uint32_t valid_tables;
92 uint32_t vbios_img_offset;
93 uint32_t vbios_img_size_in_kb;
94 uint32_t dataexchange_offset;
95 uint32_t dataexchange_size_in_kb;
96 uint32_t ras_tele_info_offset;
97 uint32_t ras_tele_info_size_in_kb;
98 uint32_t ip_discovery_offset;
99 uint32_t ip_discovery_size_in_kb;
100 uint32_t bad_page_info_offset;
101 uint32_t bad_page_size_in_kb;
102 uint32_t reserved[8];
103};
104
105/*
106 * PF2VF history log:
107 * v1 defined in amdgim
108 * v2 current
109 *
110 * VF2PF history log:
111 * v1 defined in amdgim
112 * v2 defined in amdgim
113 * v3 current
114 */
115#define AMD_SRIOV_MSG_FW_VRAM_PF2VF_VER 2
116#define AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER 3
117
118#define AMD_SRIOV_MSG_RESERVE_UCODE 24
119
120#define AMD_SRIOV_MSG_RESERVE_VCN_INST 4
121
122enum amd_sriov_ucode_engine_id {
123 AMD_SRIOV_UCODE_ID_VCE = 0,
124 AMD_SRIOV_UCODE_ID_UVD,
125 AMD_SRIOV_UCODE_ID_MC,
126 AMD_SRIOV_UCODE_ID_ME,
127 AMD_SRIOV_UCODE_ID_PFP,
128 AMD_SRIOV_UCODE_ID_CE,
129 AMD_SRIOV_UCODE_ID_RLC,
130 AMD_SRIOV_UCODE_ID_RLC_SRLC,
131 AMD_SRIOV_UCODE_ID_RLC_SRLG,
132 AMD_SRIOV_UCODE_ID_RLC_SRLS,
133 AMD_SRIOV_UCODE_ID_MEC,
134 AMD_SRIOV_UCODE_ID_MEC2,
135 AMD_SRIOV_UCODE_ID_SOS,
136 AMD_SRIOV_UCODE_ID_ASD,
137 AMD_SRIOV_UCODE_ID_TA_RAS,
138 AMD_SRIOV_UCODE_ID_TA_XGMI,
139 AMD_SRIOV_UCODE_ID_SMC,
140 AMD_SRIOV_UCODE_ID_SDMA,
141 AMD_SRIOV_UCODE_ID_SDMA2,
142 AMD_SRIOV_UCODE_ID_VCN,
143 AMD_SRIOV_UCODE_ID_DMCU,
144 AMD_SRIOV_UCODE_ID__MAX
145};
146
147#pragma pack(push, 1) // PF2VF / VF2PF data areas are byte packed
148
149union amd_sriov_msg_feature_flags {
150 struct {
151 uint32_t error_log_collect : 1;
152 uint32_t host_load_ucodes : 1;
153 uint32_t host_flr_vramlost : 1;
154 uint32_t mm_bw_management : 1;
155 uint32_t pp_one_vf_mode : 1;
156 uint32_t reg_indirect_acc : 1;
157 uint32_t av1_support : 1;
158 uint32_t vcn_rb_decouple : 1;
159 uint32_t mes_info_dump_enable : 1;
160 uint32_t ras_caps : 1;
161 uint32_t ras_telemetry : 1;
162 uint32_t ras_cper : 1;
163 uint32_t xgmi_ta_ext_peer_link : 1;
164 uint32_t reserved : 19;
165 } flags;
166 uint32_t all;
167};
168
169union amd_sriov_reg_access_flags {
170 struct {
171 uint32_t vf_reg_access_ih : 1;
172 uint32_t vf_reg_access_mmhub : 1;
173 uint32_t vf_reg_access_gc : 1;
174 uint32_t vf_reg_access_l1_tlb_cntl : 1;
175 uint32_t vf_reg_access_sq_config : 1;
176 uint32_t reserved : 27;
177 } flags;
178 uint32_t all;
179};
180
181union amd_sriov_ras_caps {
182 struct {
183 uint64_t block_umc : 1;
184 uint64_t block_sdma : 1;
185 uint64_t block_gfx : 1;
186 uint64_t block_mmhub : 1;
187 uint64_t block_athub : 1;
188 uint64_t block_pcie_bif : 1;
189 uint64_t block_hdp : 1;
190 uint64_t block_xgmi_wafl : 1;
191 uint64_t block_df : 1;
192 uint64_t block_smn : 1;
193 uint64_t block_sem : 1;
194 uint64_t block_mp0 : 1;
195 uint64_t block_mp1 : 1;
196 uint64_t block_fuse : 1;
197 uint64_t block_mca : 1;
198 uint64_t block_vcn : 1;
199 uint64_t block_jpeg : 1;
200 uint64_t block_ih : 1;
201 uint64_t block_mpio : 1;
202 uint64_t block_mmsch : 1;
203 uint64_t poison_propogation_mode : 1;
204 uint64_t reserved : 43;
205 } bits;
206 uint64_t all;
207};
208
209union amd_sriov_msg_os_info {
210 struct {
211 uint32_t windows : 1;
212 uint32_t reserved : 31;
213 } info;
214 uint32_t all;
215};
216
217struct amd_sriov_msg_uuid_info {
218 union {
219 struct {
220 uint32_t did : 16;
221 uint32_t fcn : 8;
222 uint32_t asic_7 : 8;
223 };
224 uint32_t time_low;
225 };
226
227 struct {
228 uint32_t time_mid : 16;
229 uint32_t time_high : 12;
230 uint32_t version : 4;
231 };
232
233 struct {
234 struct {
235 uint8_t clk_seq_hi : 6;
236 uint8_t variant : 2;
237 };
238 union {
239 uint8_t clk_seq_low;
240 uint8_t asic_6;
241 };
242 uint16_t asic_4;
243 };
244
245 uint32_t asic_0;
246};
247
248struct amd_sriov_msg_pf2vf_info_header {
249 /* the total structure size in byte */
250 uint32_t size;
251 /* version of this structure, written by the HOST */
252 uint32_t version;
253 /* reserved */
254 uint32_t reserved[2];
255};
256
257#define AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE (55)
258struct amd_sriov_msg_pf2vf_info {
259 /* header contains size and version */
260 struct amd_sriov_msg_pf2vf_info_header header;
261 /* use private key from mailbox 2 to create checksum */
262 uint32_t checksum;
263 /* The features flags of the HOST driver supports */
264 union amd_sriov_msg_feature_flags feature_flags;
265 /* (max_width * max_height * fps) / (16 * 16) */
266 uint32_t hevc_enc_max_mb_per_second;
267 /* (max_width * max_height) / (16 * 16) */
268 uint32_t hevc_enc_max_mb_per_frame;
269 /* (max_width * max_height * fps) / (16 * 16) */
270 uint32_t avc_enc_max_mb_per_second;
271 /* (max_width * max_height) / (16 * 16) */
272 uint32_t avc_enc_max_mb_per_frame;
273 /* MEC FW position in BYTE from the start of VF visible frame buffer */
274 uint64_t mecfw_offset;
275 /* MEC FW size in BYTE */
276 uint32_t mecfw_size;
277 /* UVD FW position in BYTE from the start of VF visible frame buffer */
278 uint64_t uvdfw_offset;
279 /* UVD FW size in BYTE */
280 uint32_t uvdfw_size;
281 /* VCE FW position in BYTE from the start of VF visible frame buffer */
282 uint64_t vcefw_offset;
283 /* VCE FW size in BYTE */
284 uint32_t vcefw_size;
285 /* Bad pages block position in BYTE */
286 uint32_t bp_block_offset_low;
287 uint32_t bp_block_offset_high;
288 /* Bad pages block size in BYTE */
289 uint32_t bp_block_size;
290 /* frequency for VF to update the VF2PF area in msec, 0 = manual */
291 uint32_t vf2pf_update_interval_ms;
292 /* identification in ROCm SMI */
293 uint64_t uuid;
294 uint32_t fcn_idx;
295 /* flags to indicate which register access method VF should use */
296 union amd_sriov_reg_access_flags reg_access_flags;
297 /* MM BW management */
298 struct {
299 uint32_t decode_max_dimension_pixels;
300 uint32_t decode_max_frame_pixels;
301 uint32_t encode_max_dimension_pixels;
302 uint32_t encode_max_frame_pixels;
303 } mm_bw_management[AMD_SRIOV_MSG_RESERVE_VCN_INST];
304 /* UUID info */
305 struct amd_sriov_msg_uuid_info uuid_info;
306 /* PCIE atomic ops support flag */
307 uint32_t pcie_atomic_ops_support_flags;
308 /* Portion of GPU memory occupied by VF. MAX value is 65535, but set to uint32_t to maintain alignment with reserved size */
309 uint32_t gpu_capacity;
310 /* vf bdf on host pci tree for debug only */
311 uint32_t bdf_on_host;
312 uint32_t more_bp; //Reserved for future use.
313 union amd_sriov_ras_caps ras_en_caps;
314 union amd_sriov_ras_caps ras_telemetry_en_caps;
315
316 /* reserved */
317 uint32_t reserved[256 - AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE];
318} __packed;
319
320struct amd_sriov_msg_vf2pf_info_header {
321 /* the total structure size in byte */
322 uint32_t size;
323 /* version of this structure, written by the guest */
324 uint32_t version;
325 /* reserved */
326 uint32_t reserved[2];
327};
328
329#define AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE (73)
330struct amd_sriov_msg_vf2pf_info {
331 /* header contains size and version */
332 struct amd_sriov_msg_vf2pf_info_header header;
333 uint32_t checksum;
334 /* driver version */
335 uint8_t driver_version[64];
336 /* driver certification, 1=WHQL, 0=None */
337 uint32_t driver_cert;
338 /* guest OS type and version */
339 union amd_sriov_msg_os_info os_info;
340 /* guest fb information in the unit of MB */
341 uint32_t fb_usage;
342 /* guest gfx engine usage percentage */
343 uint32_t gfx_usage;
344 /* guest gfx engine health percentage */
345 uint32_t gfx_health;
346 /* guest compute engine usage percentage */
347 uint32_t compute_usage;
348 /* guest compute engine health percentage */
349 uint32_t compute_health;
350 /* guest avc engine usage percentage. 0xffff means N/A */
351 uint32_t avc_enc_usage;
352 /* guest avc engine health percentage. 0xffff means N/A */
353 uint32_t avc_enc_health;
354 /* guest hevc engine usage percentage. 0xffff means N/A */
355 uint32_t hevc_enc_usage;
356 /* guest hevc engine usage percentage. 0xffff means N/A */
357 uint32_t hevc_enc_health;
358 /* combined encode/decode usage */
359 uint32_t encode_usage;
360 uint32_t decode_usage;
361 /* Version of PF2VF that VF understands */
362 uint32_t pf2vf_version_required;
363 /* additional FB usage */
364 uint32_t fb_vis_usage;
365 uint32_t fb_vis_size;
366 uint32_t fb_size;
367 /* guest ucode data, each one is 1.25 Dword */
368 struct {
369 uint8_t id;
370 uint32_t version;
371 } ucode_info[AMD_SRIOV_MSG_RESERVE_UCODE];
372 uint64_t dummy_page_addr;
373 /* FB allocated for guest MES to record UQ info */
374 uint64_t mes_info_addr;
375 uint32_t mes_info_size;
376 /* reserved */
377 uint32_t reserved[256 - AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE];
378} __packed;
379
380/* mailbox message send from guest to host */
381enum amd_sriov_mailbox_request_message {
382 MB_REQ_MSG_REQ_GPU_INIT_ACCESS = 1,
383 MB_REQ_MSG_REL_GPU_INIT_ACCESS,
384 MB_REQ_MSG_REQ_GPU_FINI_ACCESS,
385 MB_REQ_MSG_REL_GPU_FINI_ACCESS,
386 MB_REQ_MSG_REQ_GPU_RESET_ACCESS,
387 MB_REQ_MSG_REQ_GPU_INIT_DATA,
388 MB_REQ_MSG_PSP_VF_CMD_RELAY,
389
390 MB_REQ_MSG_LOG_VF_ERROR = 200,
391 MB_REQ_MSG_READY_TO_RESET = 201,
392 MB_REQ_MSG_RAS_POISON = 202,
393 MB_REQ_RAS_ERROR_COUNT = 203,
394 MB_REQ_RAS_CPER_DUMP = 204,
395 MB_REQ_RAS_BAD_PAGES = 205,
396};
397
398/* mailbox message send from host to guest */
399enum amd_sriov_mailbox_response_message {
400 MB_RES_MSG_CLR_MSG_BUF = 0,
401 MB_RES_MSG_READY_TO_ACCESS_GPU = 1,
402 MB_RES_MSG_FLR_NOTIFICATION = 2,
403 MB_RES_MSG_FLR_NOTIFICATION_COMPLETION = 3,
404 MB_RES_MSG_SUCCESS = 4,
405 MB_RES_MSG_FAIL = 5,
406 MB_RES_MSG_QUERY_ALIVE = 6,
407 MB_RES_MSG_GPU_INIT_DATA_READY = 7,
408 MB_RES_MSG_RAS_POISON_READY = 8,
409 MB_RES_MSG_PF_SOFT_FLR_NOTIFICATION = 9,
410 MB_RES_MSG_GPU_RMA = 10,
411 MB_RES_MSG_RAS_ERROR_COUNT_READY = 11,
412 MB_REQ_RAS_CPER_DUMP_READY = 14,
413 MB_RES_MSG_RAS_BAD_PAGES_READY = 15,
414 MB_RES_MSG_RAS_BAD_PAGES_NOTIFICATION = 16,
415 MB_RES_MSG_UNRECOV_ERR_NOTIFICATION = 17,
416 MB_RES_MSG_TEXT_MESSAGE = 255
417};
418
419enum amd_sriov_ras_telemetry_gpu_block {
420 RAS_TELEMETRY_GPU_BLOCK_UMC = 0,
421 RAS_TELEMETRY_GPU_BLOCK_SDMA = 1,
422 RAS_TELEMETRY_GPU_BLOCK_GFX = 2,
423 RAS_TELEMETRY_GPU_BLOCK_MMHUB = 3,
424 RAS_TELEMETRY_GPU_BLOCK_ATHUB = 4,
425 RAS_TELEMETRY_GPU_BLOCK_PCIE_BIF = 5,
426 RAS_TELEMETRY_GPU_BLOCK_HDP = 6,
427 RAS_TELEMETRY_GPU_BLOCK_XGMI_WAFL = 7,
428 RAS_TELEMETRY_GPU_BLOCK_DF = 8,
429 RAS_TELEMETRY_GPU_BLOCK_SMN = 9,
430 RAS_TELEMETRY_GPU_BLOCK_SEM = 10,
431 RAS_TELEMETRY_GPU_BLOCK_MP0 = 11,
432 RAS_TELEMETRY_GPU_BLOCK_MP1 = 12,
433 RAS_TELEMETRY_GPU_BLOCK_FUSE = 13,
434 RAS_TELEMETRY_GPU_BLOCK_MCA = 14,
435 RAS_TELEMETRY_GPU_BLOCK_VCN = 15,
436 RAS_TELEMETRY_GPU_BLOCK_JPEG = 16,
437 RAS_TELEMETRY_GPU_BLOCK_IH = 17,
438 RAS_TELEMETRY_GPU_BLOCK_MPIO = 18,
439 RAS_TELEMETRY_GPU_BLOCK_COUNT = 19,
440};
441
442struct amd_sriov_ras_telemetry_header {
443 uint32_t checksum;
444 uint32_t used_size;
445 uint32_t reserved[2];
446};
447
448struct amd_sriov_ras_telemetry_error_count {
449 struct {
450 uint32_t ce_count;
451 uint32_t ue_count;
452 uint32_t de_count;
453 uint32_t ce_overflow_count;
454 uint32_t ue_overflow_count;
455 uint32_t de_overflow_count;
456 uint32_t reserved[6];
457 } block[RAS_TELEMETRY_GPU_BLOCK_COUNT];
458};
459
460struct amd_sriov_ras_cper_dump {
461 uint32_t more;
462 uint64_t overflow_count;
463 uint64_t count;
464 uint64_t wptr;
465 uint32_t buf[];
466};
467
468struct amd_sriov_ras_chk_criti {
469 uint32_t hit;
470};
471
472struct amdsriov_ras_telemetry {
473 struct amd_sriov_ras_telemetry_header header;
474
475 union {
476 struct amd_sriov_ras_telemetry_error_count error_count;
477 struct amd_sriov_ras_cper_dump cper_dump;
478 struct amd_sriov_ras_chk_criti chk_criti;
479 } body;
480};
481
482/* version data stored in MAILBOX_MSGBUF_RCV_DW1 for future expansion */
483enum amd_sriov_gpu_init_data_version {
484 GPU_INIT_DATA_READY_V1 = 1,
485};
486
487#pragma pack(pop) // Restore previous packing option
488
489/* checksum function between host and guest */
490unsigned int amd_sriov_msg_checksum(void *obj, unsigned long obj_size, unsigned int key,
491 unsigned int checksum);
492
493/* assertion at compile time */
494#ifdef __linux__
495#define stringification(s) _stringification(s)
496#define _stringification(s) #s
497
498_Static_assert(
499 sizeof(struct amd_sriov_msg_vf2pf_info) == AMD_SRIOV_MSG_SIZE_KB << 10,
500 "amd_sriov_msg_vf2pf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB");
501
502_Static_assert(
503 sizeof(struct amd_sriov_msg_pf2vf_info) == AMD_SRIOV_MSG_SIZE_KB << 10,
504 "amd_sriov_msg_pf2vf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB");
505
506_Static_assert(AMD_SRIOV_MSG_RESERVE_UCODE % 4 == 0,
507 "AMD_SRIOV_MSG_RESERVE_UCODE must be multiple of 4");
508
509_Static_assert(AMD_SRIOV_MSG_RESERVE_UCODE > AMD_SRIOV_UCODE_ID__MAX,
510 "AMD_SRIOV_MSG_RESERVE_UCODE must be bigger than AMD_SRIOV_UCODE_ID__MAX");
511
512#undef _stringification
513#undef stringification
514#endif
515
516#endif /* AMDGV_SRIOV_MSG__H_ */
517

source code of linux/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h