1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __AMDGPU_UVD_H__
25#define __AMDGPU_UVD_H__
26
27#define AMDGPU_DEFAULT_UVD_HANDLES 10
28#define AMDGPU_MAX_UVD_HANDLES 40
29#define AMDGPU_UVD_STACK_SIZE (200*1024)
30#define AMDGPU_UVD_HEAP_SIZE (256*1024)
31#define AMDGPU_UVD_SESSION_SIZE (50*1024)
32#define AMDGPU_UVD_FIRMWARE_OFFSET 256
33
34#define AMDGPU_MAX_UVD_INSTANCES 2
35
36#define AMDGPU_UVD_FIRMWARE_SIZE(adev) \
37 (AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(((const struct common_firmware_header *)(adev)->uvd.fw->data)->ucode_size_bytes) + \
38 8) - AMDGPU_UVD_FIRMWARE_OFFSET)
39
40struct amdgpu_uvd_inst {
41 struct amdgpu_bo *vcpu_bo;
42 void *cpu_addr;
43 uint64_t gpu_addr;
44 void *saved_bo;
45 struct amdgpu_ring ring;
46 struct amdgpu_ring ring_enc[AMDGPU_MAX_UVD_ENC_RINGS];
47 struct amdgpu_irq_src irq;
48 uint32_t srbm_soft_reset;
49};
50
51#define AMDGPU_UVD_HARVEST_UVD0 (1 << 0)
52#define AMDGPU_UVD_HARVEST_UVD1 (1 << 1)
53
54struct amdgpu_uvd {
55 const struct firmware *fw; /* UVD firmware */
56 unsigned fw_version;
57 unsigned max_handles;
58 unsigned num_enc_rings;
59 uint8_t num_uvd_inst;
60 bool address_64_bit;
61 bool use_ctx_buf;
62 struct amdgpu_uvd_inst inst[AMDGPU_MAX_UVD_INSTANCES];
63 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
64 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
65 struct drm_sched_entity entity;
66 struct delayed_work idle_work;
67 unsigned harvest_config;
68 /* store image width to adjust nb memory state */
69 unsigned decode_image_width;
70 uint32_t keyselect;
71 struct amdgpu_bo *ib_bo;
72};
73
74int amdgpu_uvd_sw_init(struct amdgpu_device *adev);
75int amdgpu_uvd_sw_fini(struct amdgpu_device *adev);
76int amdgpu_uvd_entity_init(struct amdgpu_device *adev, struct amdgpu_ring *ring);
77int amdgpu_uvd_prepare_suspend(struct amdgpu_device *adev);
78int amdgpu_uvd_suspend(struct amdgpu_device *adev);
79int amdgpu_uvd_resume(struct amdgpu_device *adev);
80int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
81 struct dma_fence **fence);
82int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
83 bool direct, struct dma_fence **fence);
84void amdgpu_uvd_free_handles(struct amdgpu_device *adev,
85 struct drm_file *filp);
86int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser,
87 struct amdgpu_job *job,
88 struct amdgpu_ib *ib);
89void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring);
90void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring);
91int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout);
92uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev);
93
94#endif
95

source code of linux/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h