1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Huang Rui
23 *
24 */
25#ifndef __AMDGPU_PSP_H__
26#define __AMDGPU_PSP_H__
27
28#include "amdgpu.h"
29#include "psp_gfx_if.h"
30#include "ta_xgmi_if.h"
31#include "ta_ras_if.h"
32#include "ta_rap_if.h"
33#include "ta_secureDisplay_if.h"
34
35#define PSP_FENCE_BUFFER_SIZE 0x1000
36#define PSP_CMD_BUFFER_SIZE 0x1000
37#define PSP_1_MEG 0x100000
38#define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000)
39#define PSP_TMR_ALIGNMENT 0x100000
40#define PSP_FW_NAME_LEN 0x24
41
42/* VBIOS gfl defines */
43#define MBOX_READY_MASK 0x80000000
44#define MBOX_STATUS_MASK 0x0000FFFF
45#define MBOX_COMMAND_MASK 0x00FF0000
46#define MBOX_READY_FLAG 0x80000000
47#define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2
48#define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3
49#define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4
50#define C2PMSG_CMD_SPI_GET_ROM_IMAGE_ADDR_LO 0xf
51#define C2PMSG_CMD_SPI_GET_ROM_IMAGE_ADDR_HI 0x10
52#define C2PMSG_CMD_SPI_GET_FLASH_IMAGE 0x11
53
54/* Command register bit 31 set to indicate readiness */
55#define MBOX_TOS_READY_FLAG (GFX_FLAG_RESPONSE)
56#define MBOX_TOS_READY_MASK (GFX_CMD_RESPONSE_MASK | GFX_CMD_STATUS_MASK)
57
58/* Values to check for a successful GFX_CMD response wait. Check against
59 * both status bits and response state - helps to detect a command failure
60 * or other unexpected cases like a device drop reading all 0xFFs
61 */
62#define MBOX_TOS_RESP_FLAG (GFX_FLAG_RESPONSE)
63#define MBOX_TOS_RESP_MASK (GFX_CMD_RESPONSE_MASK | GFX_CMD_STATUS_MASK)
64
65extern const struct attribute_group amdgpu_flash_attr_group;
66
67enum psp_shared_mem_size {
68 PSP_ASD_SHARED_MEM_SIZE = 0x0,
69 PSP_XGMI_SHARED_MEM_SIZE = 0x4000,
70 PSP_RAS_SHARED_MEM_SIZE = 0x4000,
71 PSP_HDCP_SHARED_MEM_SIZE = 0x4000,
72 PSP_DTM_SHARED_MEM_SIZE = 0x4000,
73 PSP_RAP_SHARED_MEM_SIZE = 0x4000,
74 PSP_SECUREDISPLAY_SHARED_MEM_SIZE = 0x4000,
75};
76
77enum ta_type_id {
78 TA_TYPE_XGMI = 1,
79 TA_TYPE_RAS,
80 TA_TYPE_HDCP,
81 TA_TYPE_DTM,
82 TA_TYPE_RAP,
83 TA_TYPE_SECUREDISPLAY,
84
85 TA_TYPE_MAX_INDEX,
86};
87
88struct psp_context;
89struct psp_xgmi_node_info;
90struct psp_xgmi_topology_info;
91struct psp_bin_desc;
92
93enum psp_bootloader_cmd {
94 PSP_BL__LOAD_SYSDRV = 0x10000,
95 PSP_BL__LOAD_SOSDRV = 0x20000,
96 PSP_BL__LOAD_KEY_DATABASE = 0x80000,
97 PSP_BL__LOAD_SOCDRV = 0xB0000,
98 PSP_BL__LOAD_DBGDRV = 0xC0000,
99 PSP_BL__LOAD_HADDRV = PSP_BL__LOAD_DBGDRV,
100 PSP_BL__LOAD_INTFDRV = 0xD0000,
101 PSP_BL__LOAD_RASDRV = 0xE0000,
102 PSP_BL__LOAD_IPKEYMGRDRV = 0xF0000,
103 PSP_BL__DRAM_LONG_TRAIN = 0x100000,
104 PSP_BL__DRAM_SHORT_TRAIN = 0x200000,
105 PSP_BL__LOAD_TOS_SPL_TABLE = 0x10000000,
106 PSP_BL__LOAD_SPDMDRV = 0x20000000,
107};
108
109enum psp_ring_type {
110 PSP_RING_TYPE__INVALID = 0,
111 /*
112 * These values map to the way the PSP kernel identifies the
113 * rings.
114 */
115 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */
116 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */
117};
118
119struct psp_ring {
120 enum psp_ring_type ring_type;
121 struct psp_gfx_rb_frame *ring_mem;
122 uint64_t ring_mem_mc_addr;
123 void *ring_mem_handle;
124 uint32_t ring_size;
125 uint32_t ring_wptr;
126};
127
128/* More registers may will be supported */
129enum psp_reg_prog_id {
130 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */
131 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */
132 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */
133 PSP_REG_MMHUB_L1_TLB_CNTL = 25,
134 PSP_REG_LAST
135};
136
137#define PSP_WAITREG_CHANGED BIT(0) /* check if the value has changed */
138#define PSP_WAITREG_NOVERBOSE BIT(1) /* No error verbose */
139
140struct psp_funcs {
141 int (*init_microcode)(struct psp_context *psp);
142 int (*wait_for_bootloader)(struct psp_context *psp);
143 int (*bootloader_load_kdb)(struct psp_context *psp);
144 int (*bootloader_load_spl)(struct psp_context *psp);
145 int (*bootloader_load_sysdrv)(struct psp_context *psp);
146 int (*bootloader_load_soc_drv)(struct psp_context *psp);
147 int (*bootloader_load_intf_drv)(struct psp_context *psp);
148 int (*bootloader_load_dbg_drv)(struct psp_context *psp);
149 int (*bootloader_load_ras_drv)(struct psp_context *psp);
150 int (*bootloader_load_ipkeymgr_drv)(struct psp_context *psp);
151 int (*bootloader_load_spdm_drv)(struct psp_context *psp);
152 int (*bootloader_load_sos)(struct psp_context *psp);
153 int (*ring_create)(struct psp_context *psp,
154 enum psp_ring_type ring_type);
155 int (*ring_stop)(struct psp_context *psp,
156 enum psp_ring_type ring_type);
157 int (*ring_destroy)(struct psp_context *psp,
158 enum psp_ring_type ring_type);
159 bool (*smu_reload_quirk)(struct psp_context *psp);
160 int (*mode1_reset)(struct psp_context *psp);
161 int (*mem_training)(struct psp_context *psp, uint32_t ops);
162 uint32_t (*ring_get_wptr)(struct psp_context *psp);
163 void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);
164 int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
165 int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver);
166 int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
167 int (*dump_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
168 int (*vbflash_stat)(struct psp_context *psp);
169 int (*fatal_error_recovery_quirk)(struct psp_context *psp);
170 bool (*get_ras_capability)(struct psp_context *psp);
171 bool (*is_aux_sos_load_required)(struct psp_context *psp);
172 bool (*is_reload_needed)(struct psp_context *psp);
173 int (*reg_program_no_ring)(struct psp_context *psp, uint32_t val,
174 enum psp_reg_prog_id id);
175};
176
177struct ta_funcs {
178 int (*fn_ta_initialize)(struct psp_context *psp);
179 int (*fn_ta_invoke)(struct psp_context *psp, uint32_t ta_cmd_id);
180 int (*fn_ta_terminate)(struct psp_context *psp);
181};
182
183#define AMDGPU_XGMI_MAX_CONNECTED_NODES 64
184struct psp_xgmi_node_info {
185 uint64_t node_id;
186 uint8_t num_hops;
187 uint8_t is_sharing_enabled;
188 enum ta_xgmi_assigned_sdma_engine sdma_engine;
189 uint8_t num_links;
190 struct xgmi_connected_port_num port_num[TA_XGMI__MAX_PORT_NUM];
191};
192
193struct psp_xgmi_topology_info {
194 uint32_t num_nodes;
195 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
196};
197
198struct psp_bin_desc {
199 uint32_t fw_version;
200 uint32_t feature_version;
201 uint32_t size_bytes;
202 uint8_t *start_addr;
203};
204
205struct ta_mem_context {
206 struct amdgpu_bo *shared_bo;
207 uint64_t shared_mc_addr;
208 void *shared_buf;
209 enum psp_shared_mem_size shared_mem_size;
210};
211
212struct ta_context {
213 bool initialized;
214 uint32_t session_id;
215 uint32_t resp_status;
216 struct ta_mem_context mem_context;
217 struct psp_bin_desc bin_desc;
218 enum psp_gfx_cmd_id ta_load_type;
219 enum ta_type_id ta_type;
220};
221
222struct ta_cp_context {
223 struct ta_context context;
224 struct mutex mutex;
225};
226
227struct psp_xgmi_context {
228 struct ta_context context;
229 struct psp_xgmi_topology_info top_info;
230 bool supports_extended_data;
231 uint8_t xgmi_ta_caps;
232};
233
234struct psp_ras_context {
235 struct ta_context context;
236 struct amdgpu_ras *ras;
237 struct mutex mutex;
238};
239
240#define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942
241#define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000
242#define GDDR6_MEM_TRAINING_OFFSET 0x8000
243/*Define the VRAM size that will be encroached by BIST training.*/
244#define BIST_MEM_TRAINING_ENCROACHED_SIZE 0x2000000
245
246enum psp_memory_training_init_flag {
247 PSP_MEM_TRAIN_NOT_SUPPORT = 0x0,
248 PSP_MEM_TRAIN_SUPPORT = 0x1,
249 PSP_MEM_TRAIN_INIT_FAILED = 0x2,
250 PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4,
251 PSP_MEM_TRAIN_INIT_SUCCESS = 0x8,
252};
253
254enum psp_memory_training_ops {
255 PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1,
256 PSP_MEM_TRAIN_SAVE = 0x2,
257 PSP_MEM_TRAIN_RESTORE = 0x4,
258 PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8,
259 PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG,
260 PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG,
261};
262
263struct psp_memory_training_context {
264 /*training data size*/
265 u64 train_data_size;
266 /*
267 * sys_cache
268 * cpu virtual address
269 * system memory buffer that used to store the training data.
270 */
271 void *sys_cache;
272
273 /*vram offset of the p2c training data*/
274 u64 p2c_train_data_offset;
275
276 /*vram offset of the c2p training data*/
277 u64 c2p_train_data_offset;
278 struct amdgpu_bo *c2p_bo;
279
280 enum psp_memory_training_init_flag init;
281 u32 training_cnt;
282 bool enable_mem_training;
283};
284
285/** PSP runtime DB **/
286#define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000
287#define PSP_RUNTIME_DB_OFFSET 0x100000
288#define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5
289#define PSP_RUNTIME_DB_VER_1 0x0100
290#define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40
291
292enum psp_runtime_entry_type {
293 PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0,
294 PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1,
295 PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */
296 PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */
297 PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */
298 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */
299 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS = 0x6, /* SCPM validation data */
300};
301
302/* PSP runtime DB header */
303struct psp_runtime_data_header {
304 /* determine the existence of runtime db */
305 uint16_t cookie;
306 /* version of runtime db */
307 uint16_t version;
308};
309
310/* PSP runtime DB entry */
311struct psp_runtime_entry {
312 /* type of runtime db entry */
313 uint32_t entry_type;
314 /* offset of entry in bytes */
315 uint16_t offset;
316 /* size of entry in bytes */
317 uint16_t size;
318};
319
320/* PSP runtime DB directory */
321struct psp_runtime_data_directory {
322 /* number of valid entries */
323 uint16_t entry_count;
324 /* db entries*/
325 struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT];
326};
327
328/* PSP runtime DB boot config feature bitmask */
329enum psp_runtime_boot_cfg_feature {
330 BOOT_CFG_FEATURE_GECC = 0x1,
331 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2,
332};
333
334/* PSP run time DB SCPM authentication defines */
335enum psp_runtime_scpm_authentication {
336 SCPM_DISABLE = 0x0,
337 SCPM_ENABLE = 0x1,
338 SCPM_ENABLE_WITH_SCPM_ERR = 0x2,
339};
340
341/* PSP runtime DB boot config entry */
342struct psp_runtime_boot_cfg_entry {
343 uint32_t boot_cfg_bitmask;
344 uint32_t reserved;
345};
346
347/* PSP runtime DB SCPM entry */
348struct psp_runtime_scpm_entry {
349 enum psp_runtime_scpm_authentication scpm_status;
350};
351
352#if defined(CONFIG_DEBUG_FS)
353struct spirom_bo {
354 struct amdgpu_bo *bo;
355 uint64_t mc_addr;
356 void *cpu_addr;
357};
358#endif
359
360struct psp_context {
361 struct amdgpu_device *adev;
362 struct psp_ring km_ring;
363 struct psp_gfx_cmd_resp *cmd;
364
365 const struct psp_funcs *funcs;
366 const struct ta_funcs *ta_funcs;
367
368 /* firmware buffer */
369 struct amdgpu_bo *fw_pri_bo;
370 uint64_t fw_pri_mc_addr;
371 void *fw_pri_buf;
372
373 /* sos firmware */
374 const struct firmware *sos_fw;
375 struct psp_bin_desc sys;
376 struct psp_bin_desc sos;
377 struct psp_bin_desc toc;
378 struct psp_bin_desc kdb;
379 struct psp_bin_desc spl;
380 struct psp_bin_desc rl;
381 struct psp_bin_desc soc_drv;
382 struct psp_bin_desc intf_drv;
383 struct psp_bin_desc dbg_drv;
384 struct psp_bin_desc ras_drv;
385 struct psp_bin_desc ipkeymgr_drv;
386 struct psp_bin_desc spdm_drv;
387
388 /* tmr buffer */
389 struct amdgpu_bo *tmr_bo;
390 uint64_t tmr_mc_addr;
391
392 /* asd firmware */
393 const struct firmware *asd_fw;
394
395 /* toc firmware */
396 const struct firmware *toc_fw;
397
398 /* cap firmware */
399 const struct firmware *cap_fw;
400
401 /* fence buffer */
402 struct amdgpu_bo *fence_buf_bo;
403 uint64_t fence_buf_mc_addr;
404 void *fence_buf;
405
406 /* cmd buffer */
407 struct amdgpu_bo *cmd_buf_bo;
408 uint64_t cmd_buf_mc_addr;
409 struct psp_gfx_cmd_resp *cmd_buf_mem;
410
411 /* fence value associated with cmd buffer */
412 atomic_t fence_value;
413 /* flag to mark whether gfx fw autoload is supported or not */
414 bool autoload_supported;
415 /* flag to mark whether psp use runtime TMR or boottime TMR */
416 bool boot_time_tmr;
417 /* flag to mark whether df cstate management centralized to PMFW */
418 bool pmfw_centralized_cstate_management;
419
420 /* xgmi ta firmware and buffer */
421 const struct firmware *ta_fw;
422 uint32_t ta_fw_version;
423
424 uint32_t cap_fw_version;
425 uint32_t cap_feature_version;
426 uint32_t cap_ucode_size;
427
428 struct ta_context asd_context;
429 struct psp_xgmi_context xgmi_context;
430 struct psp_ras_context ras_context;
431 struct ta_cp_context hdcp_context;
432 struct ta_cp_context dtm_context;
433 struct ta_cp_context rap_context;
434 struct ta_cp_context securedisplay_context;
435 struct mutex mutex;
436 struct psp_memory_training_context mem_train_ctx;
437
438 uint32_t boot_cfg_bitmask;
439
440 /* firmware upgrades supported */
441 bool sup_pd_fw_up;
442 bool sup_ifwi_up;
443
444 char *vbflash_tmp_buf;
445 size_t vbflash_image_size;
446 bool vbflash_done;
447#if defined(CONFIG_DEBUG_FS)
448 struct spirom_bo *spirom_dump_trip;
449#endif
450};
451
452struct amdgpu_psp_funcs {
453 bool (*check_fw_loading_status)(struct amdgpu_device *adev,
454 enum AMDGPU_UCODE_ID);
455};
456
457
458#define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
459#define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
460#define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
461#define psp_init_microcode(psp) \
462 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
463#define psp_bootloader_load_kdb(psp) \
464 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0)
465#define psp_bootloader_load_spl(psp) \
466 ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0)
467#define psp_bootloader_load_sysdrv(psp) \
468 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
469#define psp_bootloader_load_soc_drv(psp) \
470 ((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0)
471#define psp_bootloader_load_intf_drv(psp) \
472 ((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0)
473#define psp_bootloader_load_dbg_drv(psp) \
474 ((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0)
475#define psp_bootloader_load_ras_drv(psp) \
476 ((psp)->funcs->bootloader_load_ras_drv ? \
477 (psp)->funcs->bootloader_load_ras_drv((psp)) : 0)
478#define psp_bootloader_load_ipkeymgr_drv(psp) \
479 ((psp)->funcs->bootloader_load_ipkeymgr_drv ? \
480 (psp)->funcs->bootloader_load_ipkeymgr_drv((psp)) : 0)
481#define psp_bootloader_load_spdm_drv(psp) \
482 ((psp)->funcs->bootloader_load_spdm_drv ? \
483 (psp)->funcs->bootloader_load_spdm_drv((psp)) : 0)
484#define psp_bootloader_load_sos(psp) \
485 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
486#define psp_smu_reload_quirk(psp) \
487 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
488#define psp_mode1_reset(psp) \
489 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
490#define psp_mem_training(psp, ops) \
491 ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0)
492
493#define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp))
494#define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value))
495
496#define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \
497 ((psp)->funcs->load_usbc_pd_fw ? \
498 (psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL)
499
500#define psp_read_usbc_pd_fw(psp, fw_ver) \
501 ((psp)->funcs->read_usbc_pd_fw ? \
502 (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL)
503
504#define psp_update_spirom(psp, fw_pri_mc_addr) \
505 ((psp)->funcs->update_spirom ? \
506 (psp)->funcs->update_spirom((psp), fw_pri_mc_addr) : -EINVAL)
507
508#define psp_dump_spirom(psp, fw_pri_mc_addr) \
509 ((psp)->funcs->dump_spirom ? \
510 (psp)->funcs->dump_spirom((psp), fw_pri_mc_addr) : -EINVAL)
511
512#define psp_vbflash_status(psp) \
513 ((psp)->funcs->vbflash_stat ? \
514 (psp)->funcs->vbflash_stat((psp)) : -EINVAL)
515
516#define psp_fatal_error_recovery_quirk(psp) \
517 ((psp)->funcs->fatal_error_recovery_quirk ? \
518 (psp)->funcs->fatal_error_recovery_quirk((psp)) : 0)
519
520#define psp_is_aux_sos_load_required(psp) \
521 ((psp)->funcs->is_aux_sos_load_required ? (psp)->funcs->is_aux_sos_load_required((psp)) : 0)
522
523#define psp_reg_program_no_ring(psp, val, id) \
524 ((psp)->funcs->reg_program_no_ring ? \
525 (psp)->funcs->reg_program_no_ring((psp), val, id) : -EINVAL)
526
527extern const struct amd_ip_funcs psp_ip_funcs;
528
529extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
530extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
531extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
532extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block;
533extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;
534extern const struct amdgpu_ip_block_version psp_v13_0_ip_block;
535extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block;
536extern const struct amdgpu_ip_block_version psp_v14_0_ip_block;
537
538int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
539 uint32_t field_val, uint32_t mask, uint32_t flags);
540extern int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index,
541 uint32_t field_val, uint32_t mask, uint32_t msec_timeout);
542
543int psp_execute_ip_fw_load(struct psp_context *psp,
544 struct amdgpu_firmware_info *ucode);
545
546int psp_gpu_reset(struct amdgpu_device *adev);
547
548int psp_ta_init_shared_buf(struct psp_context *psp,
549 struct ta_mem_context *mem_ctx);
550void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx);
551int psp_ta_unload(struct psp_context *psp, struct ta_context *context);
552int psp_ta_load(struct psp_context *psp, struct ta_context *context);
553int psp_ta_invoke(struct psp_context *psp,
554 uint32_t ta_cmd_id,
555 struct ta_context *context);
556
557int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta);
558int psp_xgmi_terminate(struct psp_context *psp);
559int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
560int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id);
561int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id);
562int psp_xgmi_get_topology_info(struct psp_context *psp,
563 int number_devices,
564 struct psp_xgmi_topology_info *topology,
565 bool get_extended_data);
566int psp_xgmi_set_topology_info(struct psp_context *psp,
567 int number_devices,
568 struct psp_xgmi_topology_info *topology);
569int psp_ras_initialize(struct psp_context *psp);
570int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
571int psp_ras_enable_features(struct psp_context *psp,
572 union ta_ras_cmd_input *info, bool enable);
573int psp_ras_trigger_error(struct psp_context *psp,
574 struct ta_ras_trigger_error_input *info, uint32_t instance_mask);
575int psp_ras_terminate(struct psp_context *psp);
576int psp_ras_query_address(struct psp_context *psp,
577 struct ta_ras_query_address_input *addr_in,
578 struct ta_ras_query_address_output *addr_out);
579
580int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
581int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
582int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status);
583int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
584
585int psp_rlc_autoload_start(struct psp_context *psp);
586
587int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
588 uint32_t value);
589int psp_ring_cmd_submit(struct psp_context *psp,
590 uint64_t cmd_buf_mc_addr,
591 uint64_t fence_mc_addr,
592 int index);
593int psp_init_asd_microcode(struct psp_context *psp,
594 const char *chip_name);
595int psp_init_toc_microcode(struct psp_context *psp,
596 const char *chip_name);
597int psp_init_sos_microcode(struct psp_context *psp,
598 const char *chip_name);
599int psp_init_ta_microcode(struct psp_context *psp,
600 const char *chip_name);
601int psp_init_cap_microcode(struct psp_context *psp,
602 const char *chip_name);
603int psp_get_fw_attestation_records_addr(struct psp_context *psp,
604 uint64_t *output_ptr);
605int psp_update_fw_reservation(struct psp_context *psp);
606int psp_load_fw_list(struct psp_context *psp,
607 struct amdgpu_firmware_info **ucode_list, int ucode_count);
608void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size);
609
610int psp_spatial_partition(struct psp_context *psp, int mode);
611int psp_memory_partition(struct psp_context *psp, int mode);
612
613int is_psp_fw_valid(struct psp_bin_desc bin);
614
615int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev);
616bool amdgpu_psp_get_ras_capability(struct psp_context *psp);
617
618int psp_config_sq_perfmon(struct psp_context *psp, uint32_t xcp_id,
619 bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable);
620bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev);
621int amdgpu_psp_reg_program_no_ring(struct psp_context *psp, uint32_t val,
622 enum psp_reg_prog_id id);
623void amdgpu_psp_debugfs_init(struct amdgpu_device *adev);
624
625
626#endif
627

source code of linux/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h