1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __AMDGPU_MES_H__
25#define __AMDGPU_MES_H__
26
27#include "amdgpu_irq.h"
28#include "kgd_kfd_interface.h"
29#include "amdgpu_gfx.h"
30#include "amdgpu_doorbell.h"
31#include <linux/sched/mm.h>
32
33#define AMDGPU_MES_MAX_COMPUTE_PIPES 8
34#define AMDGPU_MES_MAX_GFX_PIPES 2
35#define AMDGPU_MES_MAX_SDMA_PIPES 2
36
37#define AMDGPU_MES_API_VERSION_SHIFT 12
38#define AMDGPU_MES_FEAT_VERSION_SHIFT 24
39
40#define AMDGPU_MES_VERSION_MASK 0x00000fff
41#define AMDGPU_MES_API_VERSION_MASK 0x00fff000
42#define AMDGPU_MES_FEAT_VERSION_MASK 0xff000000
43#define AMDGPU_MES_MSCRATCH_SIZE 0x40000
44#define AMDGPU_MES_INVALID_DB_OFFSET 0xffffffff
45
46enum amdgpu_mes_priority_level {
47 AMDGPU_MES_PRIORITY_LEVEL_LOW = 0,
48 AMDGPU_MES_PRIORITY_LEVEL_NORMAL = 1,
49 AMDGPU_MES_PRIORITY_LEVEL_MEDIUM = 2,
50 AMDGPU_MES_PRIORITY_LEVEL_HIGH = 3,
51 AMDGPU_MES_PRIORITY_LEVEL_REALTIME = 4,
52 AMDGPU_MES_PRIORITY_NUM_LEVELS
53};
54
55#define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */
56#define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */
57
58struct amdgpu_mes_funcs;
59
60enum amdgpu_mes_pipe {
61 AMDGPU_MES_SCHED_PIPE = 0,
62 AMDGPU_MES_KIQ_PIPE,
63 AMDGPU_MAX_MES_PIPES = 2,
64};
65
66struct amdgpu_mes {
67 struct amdgpu_device *adev;
68
69 struct mutex mutex_hidden;
70
71 struct idr pasid_idr;
72 struct idr gang_id_idr;
73 struct idr queue_id_idr;
74 struct ida doorbell_ida;
75
76 spinlock_t queue_id_lock;
77
78 uint32_t sched_version;
79 uint32_t kiq_version;
80 uint32_t fw_version[AMDGPU_MAX_MES_PIPES];
81 bool enable_legacy_queue_map;
82
83 uint32_t total_max_queue;
84 uint32_t max_doorbell_slices;
85
86 uint64_t default_process_quantum;
87 uint64_t default_gang_quantum;
88
89 struct amdgpu_ring ring[AMDGPU_MAX_MES_PIPES];
90 spinlock_t ring_lock[AMDGPU_MAX_MES_PIPES];
91
92 const struct firmware *fw[AMDGPU_MAX_MES_PIPES];
93
94 /* mes ucode */
95 struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_PIPES];
96 uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES];
97 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES];
98 uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES];
99
100 /* mes ucode data */
101 struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_PIPES];
102 uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_PIPES];
103 uint32_t *data_fw_ptr[AMDGPU_MAX_MES_PIPES];
104 uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES];
105
106 /* eop gpu obj */
107 struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_PIPES];
108 uint64_t eop_gpu_addr[AMDGPU_MAX_MES_PIPES];
109
110 void *mqd_backup[AMDGPU_MAX_MES_PIPES];
111 struct amdgpu_irq_src irq[AMDGPU_MAX_MES_PIPES];
112
113 uint32_t vmid_mask_gfxhub;
114 uint32_t vmid_mask_mmhub;
115 uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES];
116 uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES];
117 uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES];
118 uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS];
119 uint32_t sch_ctx_offs[AMDGPU_MAX_MES_PIPES];
120 uint64_t sch_ctx_gpu_addr[AMDGPU_MAX_MES_PIPES];
121 uint64_t *sch_ctx_ptr[AMDGPU_MAX_MES_PIPES];
122 uint32_t query_status_fence_offs[AMDGPU_MAX_MES_PIPES];
123 uint64_t query_status_fence_gpu_addr[AMDGPU_MAX_MES_PIPES];
124 uint64_t *query_status_fence_ptr[AMDGPU_MAX_MES_PIPES];
125
126 uint32_t saved_flags;
127
128 /* initialize kiq pipe */
129 int (*kiq_hw_init)(struct amdgpu_device *adev);
130 int (*kiq_hw_fini)(struct amdgpu_device *adev);
131
132 /* MES doorbells */
133 uint32_t db_start_dw_offset;
134 uint32_t num_mes_dbs;
135 unsigned long *doorbell_bitmap;
136
137 /* MES event log buffer */
138 uint32_t event_log_size;
139 struct amdgpu_bo *event_log_gpu_obj;
140 uint64_t event_log_gpu_addr;
141 void *event_log_cpu_addr;
142
143 /* ip specific functions */
144 const struct amdgpu_mes_funcs *funcs;
145
146 /* mes resource_1 bo*/
147 struct amdgpu_bo *resource_1[AMDGPU_MAX_MES_PIPES];
148 uint64_t resource_1_gpu_addr[AMDGPU_MAX_MES_PIPES];
149 void *resource_1_addr[AMDGPU_MAX_MES_PIPES];
150
151 int hung_queue_db_array_size;
152 int hung_queue_hqd_info_offset;
153 struct amdgpu_bo *hung_queue_db_array_gpu_obj;
154 uint64_t hung_queue_db_array_gpu_addr;
155 void *hung_queue_db_array_cpu_addr;
156};
157
158struct amdgpu_mes_gang {
159 int gang_id;
160 int priority;
161 int inprocess_gang_priority;
162 int global_priority_level;
163 struct list_head list;
164 struct amdgpu_mes_process *process;
165 struct amdgpu_bo *gang_ctx_bo;
166 uint64_t gang_ctx_gpu_addr;
167 void *gang_ctx_cpu_ptr;
168 uint64_t gang_quantum;
169 struct list_head queue_list;
170};
171
172struct amdgpu_mes_queue {
173 struct list_head list;
174 struct amdgpu_mes_gang *gang;
175 int queue_id;
176 uint64_t doorbell_off;
177 struct amdgpu_bo *mqd_obj;
178 void *mqd_cpu_ptr;
179 uint64_t mqd_gpu_addr;
180 uint64_t wptr_gpu_addr;
181 int queue_type;
182 int paging;
183 struct amdgpu_ring *ring;
184};
185
186struct amdgpu_mes_queue_properties {
187 int queue_type;
188 uint64_t hqd_base_gpu_addr;
189 uint64_t rptr_gpu_addr;
190 uint64_t wptr_gpu_addr;
191 uint64_t wptr_mc_addr;
192 uint32_t queue_size;
193 uint64_t eop_gpu_addr;
194 uint32_t hqd_pipe_priority;
195 uint32_t hqd_queue_priority;
196 bool paging;
197 struct amdgpu_ring *ring;
198 /* out */
199 uint64_t doorbell_off;
200};
201
202struct amdgpu_mes_gang_properties {
203 uint32_t priority;
204 uint32_t gang_quantum;
205 uint32_t inprocess_gang_priority;
206 uint32_t priority_level;
207 int global_priority_level;
208};
209
210struct mes_add_queue_input {
211 uint32_t process_id;
212 uint64_t page_table_base_addr;
213 uint64_t process_va_start;
214 uint64_t process_va_end;
215 uint64_t process_quantum;
216 uint64_t process_context_addr;
217 uint64_t gang_quantum;
218 uint64_t gang_context_addr;
219 uint32_t inprocess_gang_priority;
220 uint32_t gang_global_priority_level;
221 uint32_t doorbell_offset;
222 uint64_t mqd_addr;
223 uint64_t wptr_addr;
224 uint64_t wptr_mc_addr;
225 uint32_t queue_type;
226 uint32_t paging;
227 uint32_t gws_base;
228 uint32_t gws_size;
229 uint64_t tba_addr;
230 uint64_t tma_addr;
231 uint32_t trap_en;
232 uint32_t skip_process_ctx_clear;
233 uint32_t is_kfd_process;
234 uint32_t is_aql_queue;
235 uint32_t queue_size;
236 uint32_t exclusively_scheduled;
237};
238
239struct mes_remove_queue_input {
240 uint32_t doorbell_offset;
241 uint64_t gang_context_addr;
242 bool remove_queue_after_reset;
243};
244
245struct mes_map_legacy_queue_input {
246 uint32_t queue_type;
247 uint32_t doorbell_offset;
248 uint32_t pipe_id;
249 uint32_t queue_id;
250 uint64_t mqd_addr;
251 uint64_t wptr_addr;
252};
253
254struct mes_unmap_legacy_queue_input {
255 enum amdgpu_unmap_queues_action action;
256 uint32_t queue_type;
257 uint32_t doorbell_offset;
258 uint32_t pipe_id;
259 uint32_t queue_id;
260 uint64_t trail_fence_addr;
261 uint64_t trail_fence_data;
262};
263
264struct mes_suspend_gang_input {
265 bool suspend_all_gangs;
266 uint64_t gang_context_addr;
267 uint64_t suspend_fence_addr;
268 uint32_t suspend_fence_value;
269};
270
271struct mes_resume_gang_input {
272 bool resume_all_gangs;
273 uint64_t gang_context_addr;
274};
275
276struct mes_reset_queue_input {
277 uint32_t queue_type;
278 uint32_t doorbell_offset;
279 bool use_mmio;
280 uint32_t me_id;
281 uint32_t pipe_id;
282 uint32_t queue_id;
283 uint64_t mqd_addr;
284 uint64_t wptr_addr;
285 uint32_t vmid;
286 bool legacy_gfx;
287 bool is_kq;
288};
289
290struct mes_detect_and_reset_queue_input {
291 uint32_t queue_type;
292 bool detect_only;
293};
294
295struct mes_inv_tlbs_pasid_input {
296 uint32_t xcc_id;
297 uint16_t pasid;
298 uint8_t hub_id;
299 uint8_t flush_type;
300};
301
302enum mes_misc_opcode {
303 MES_MISC_OP_WRITE_REG,
304 MES_MISC_OP_READ_REG,
305 MES_MISC_OP_WRM_REG_WAIT,
306 MES_MISC_OP_WRM_REG_WR_WAIT,
307 MES_MISC_OP_SET_SHADER_DEBUGGER,
308 MES_MISC_OP_CHANGE_CONFIG,
309};
310
311struct mes_misc_op_input {
312 enum mes_misc_opcode op;
313
314 union {
315 struct {
316 uint32_t reg_offset;
317 uint64_t buffer_addr;
318 } read_reg;
319
320 struct {
321 uint32_t reg_offset;
322 uint32_t reg_value;
323 } write_reg;
324
325 struct {
326 uint32_t ref;
327 uint32_t mask;
328 uint32_t reg0;
329 uint32_t reg1;
330 } wrm_reg;
331
332 struct {
333 uint64_t process_context_addr;
334 union {
335 struct {
336 uint32_t single_memop : 1;
337 uint32_t single_alu_op : 1;
338 uint32_t reserved: 29;
339 uint32_t process_ctx_flush: 1;
340 };
341 uint32_t u32all;
342 } flags;
343 uint32_t spi_gdbg_per_vmid_cntl;
344 uint32_t tcp_watch_cntl[4];
345 uint32_t trap_en;
346 } set_shader_debugger;
347
348 struct {
349 union {
350 struct {
351 uint32_t limit_single_process : 1;
352 uint32_t enable_hws_logging_buffer : 1;
353 uint32_t reserved : 30;
354 };
355 uint32_t all;
356 } option;
357 struct {
358 uint32_t tdr_level;
359 uint32_t tdr_delay;
360 } tdr_config;
361 } change_config;
362 };
363};
364
365struct amdgpu_mes_funcs {
366 int (*add_hw_queue)(struct amdgpu_mes *mes,
367 struct mes_add_queue_input *input);
368
369 int (*remove_hw_queue)(struct amdgpu_mes *mes,
370 struct mes_remove_queue_input *input);
371
372 int (*map_legacy_queue)(struct amdgpu_mes *mes,
373 struct mes_map_legacy_queue_input *input);
374
375 int (*unmap_legacy_queue)(struct amdgpu_mes *mes,
376 struct mes_unmap_legacy_queue_input *input);
377
378 int (*suspend_gang)(struct amdgpu_mes *mes,
379 struct mes_suspend_gang_input *input);
380
381 int (*resume_gang)(struct amdgpu_mes *mes,
382 struct mes_resume_gang_input *input);
383
384 int (*misc_op)(struct amdgpu_mes *mes,
385 struct mes_misc_op_input *input);
386
387 int (*reset_hw_queue)(struct amdgpu_mes *mes,
388 struct mes_reset_queue_input *input);
389
390 int (*detect_and_reset_hung_queues)(struct amdgpu_mes *mes,
391 struct mes_detect_and_reset_queue_input *input);
392
393
394 int (*invalidate_tlbs_pasid)(struct amdgpu_mes *mes,
395 struct mes_inv_tlbs_pasid_input *input);
396};
397
398#define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev))
399#define amdgpu_mes_kiq_hw_fini(adev) (adev)->mes.kiq_hw_fini((adev))
400
401int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe);
402int amdgpu_mes_init(struct amdgpu_device *adev);
403void amdgpu_mes_fini(struct amdgpu_device *adev);
404
405int amdgpu_mes_suspend(struct amdgpu_device *adev);
406int amdgpu_mes_resume(struct amdgpu_device *adev);
407
408int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev,
409 struct amdgpu_ring *ring);
410int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev,
411 struct amdgpu_ring *ring,
412 enum amdgpu_unmap_queues_action action,
413 u64 gpu_addr, u64 seq);
414int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev,
415 struct amdgpu_ring *ring,
416 unsigned int vmid,
417 bool use_mmio);
418
419int amdgpu_mes_get_hung_queue_db_array_size(struct amdgpu_device *adev);
420int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev,
421 int queue_type,
422 bool detect_only,
423 unsigned int *hung_db_num,
424 u32 *hung_db_array);
425
426uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg);
427int amdgpu_mes_wreg(struct amdgpu_device *adev,
428 uint32_t reg, uint32_t val);
429int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev,
430 uint32_t reg0, uint32_t reg1,
431 uint32_t ref, uint32_t mask);
432int amdgpu_mes_hdp_flush(struct amdgpu_device *adev);
433int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev,
434 uint64_t process_context_addr,
435 uint32_t spi_gdbg_per_vmid_cntl,
436 const uint32_t *tcp_watch_cntl,
437 uint32_t flags,
438 bool trap_en);
439int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev,
440 uint64_t process_context_addr);
441
442uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev,
443 enum amdgpu_mes_priority_level prio);
444
445int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev);
446
447/*
448 * MES lock can be taken in MMU notifiers.
449 *
450 * A bit more detail about why to set no-FS reclaim with MES lock:
451 *
452 * The purpose of the MMU notifier is to stop GPU access to memory so
453 * that the Linux VM subsystem can move pages around safely. This is
454 * done by preempting user mode queues for the affected process. When
455 * MES is used, MES lock needs to be taken to preempt the queues.
456 *
457 * The MMU notifier callback entry point in the driver is
458 * amdgpu_mn_invalidate_range_start_hsa. The relevant call chain from
459 * there is:
460 * amdgpu_amdkfd_evict_userptr -> kgd2kfd_quiesce_mm ->
461 * kfd_process_evict_queues -> pdd->dev->dqm->ops.evict_process_queues
462 *
463 * The last part of the chain is a function pointer where we take the
464 * MES lock.
465 *
466 * The problem with taking locks in the MMU notifier is, that MMU
467 * notifiers can be called in reclaim-FS context. That's where the
468 * kernel frees up pages to make room for new page allocations under
469 * memory pressure. While we are running in reclaim-FS context, we must
470 * not trigger another memory reclaim operation because that would
471 * recursively reenter the reclaim code and cause a deadlock. The
472 * memalloc_nofs_save/restore calls guarantee that.
473 *
474 * In addition we also need to avoid lock dependencies on other locks taken
475 * under the MES lock, for example reservation locks. Here is a possible
476 * scenario of a deadlock:
477 * Thread A: takes and holds reservation lock | triggers reclaim-FS |
478 * MMU notifier | blocks trying to take MES lock
479 * Thread B: takes and holds MES lock | blocks trying to take reservation lock
480 *
481 * In this scenario Thread B gets involved in a deadlock even without
482 * triggering a reclaim-FS operation itself.
483 * To fix this and break the lock dependency chain you'd need to either:
484 * 1. protect reservation locks with memalloc_nofs_save/restore, or
485 * 2. avoid taking reservation locks under the MES lock.
486 *
487 * Reservation locks are taken all over the kernel in different subsystems, we
488 * have no control over them and their lock dependencies.So the only workable
489 * solution is to avoid taking other locks under the MES lock.
490 * As a result, make sure no reclaim-FS happens while holding this lock anywhere
491 * to prevent deadlocks when an MMU notifier runs in reclaim-FS context.
492 */
493static inline void amdgpu_mes_lock(struct amdgpu_mes *mes)
494{
495 mutex_lock(&mes->mutex_hidden);
496 mes->saved_flags = memalloc_noreclaim_save();
497}
498
499static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes)
500{
501 memalloc_noreclaim_restore(flags: mes->saved_flags);
502 mutex_unlock(lock: &mes->mutex_hidden);
503}
504
505bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev);
506
507int amdgpu_mes_update_enforce_isolation(struct amdgpu_device *adev);
508
509#endif /* __AMDGPU_MES_H__ */
510

source code of linux/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h