1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright 2025 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25#ifndef __AMDGPU_CPER_H__
26#define __AMDGPU_CPER_H__
27
28#include "amd_cper.h"
29#include "amdgpu_aca.h"
30
31#define CPER_MAX_ALLOWED_COUNT 0x1000
32#define CPER_MAX_RING_SIZE 0X100000
33#define HDR_LEN (sizeof(struct cper_hdr))
34#define SEC_DESC_LEN (sizeof(struct cper_sec_desc))
35
36#define BOOT_SEC_LEN (sizeof(struct cper_sec_crashdump_boot))
37#define FATAL_SEC_LEN (sizeof(struct cper_sec_crashdump_fatal))
38#define NONSTD_SEC_LEN (sizeof(struct cper_sec_nonstd_err))
39
40#define SEC_DESC_OFFSET(idx) (HDR_LEN + (SEC_DESC_LEN * idx))
41
42#define BOOT_SEC_OFFSET(count, idx) (HDR_LEN + (SEC_DESC_LEN * count) + (BOOT_SEC_LEN * idx))
43#define FATAL_SEC_OFFSET(count, idx) (HDR_LEN + (SEC_DESC_LEN * count) + (FATAL_SEC_LEN * idx))
44#define NONSTD_SEC_OFFSET(count, idx) (HDR_LEN + (SEC_DESC_LEN * count) + (NONSTD_SEC_LEN * idx))
45
46enum amdgpu_cper_type {
47 AMDGPU_CPER_TYPE_RUNTIME,
48 AMDGPU_CPER_TYPE_FATAL,
49 AMDGPU_CPER_TYPE_BOOT,
50 AMDGPU_CPER_TYPE_BP_THRESHOLD,
51};
52
53struct amdgpu_cper {
54 bool enabled;
55
56 atomic_t unique_id;
57 struct mutex cper_lock;
58
59 /* Lifetime CPERs generated */
60 uint32_t count;
61 uint32_t max_count;
62
63 uint32_t wptr;
64
65 void *ring[CPER_MAX_ALLOWED_COUNT];
66 struct amdgpu_ring ring_buf;
67 struct mutex ring_lock;
68};
69
70void amdgpu_cper_entry_fill_hdr(struct amdgpu_device *adev,
71 struct cper_hdr *hdr,
72 enum amdgpu_cper_type type,
73 enum cper_error_severity sev);
74int amdgpu_cper_entry_fill_fatal_section(struct amdgpu_device *adev,
75 struct cper_hdr *hdr,
76 uint32_t idx,
77 struct cper_sec_crashdump_reg_data reg_data);
78int amdgpu_cper_entry_fill_runtime_section(struct amdgpu_device *adev,
79 struct cper_hdr *hdr,
80 uint32_t idx,
81 enum cper_error_severity sev,
82 uint32_t *reg_dump,
83 uint32_t reg_count);
84int amdgpu_cper_entry_fill_bad_page_threshold_section(struct amdgpu_device *adev,
85 struct cper_hdr *hdr,
86 uint32_t section_idx);
87
88struct cper_hdr *amdgpu_cper_alloc_entry(struct amdgpu_device *adev,
89 enum amdgpu_cper_type type,
90 uint16_t section_count);
91/* UE must be encoded into separated cper entries, 1 UE 1 cper */
92int amdgpu_cper_generate_ue_record(struct amdgpu_device *adev,
93 struct aca_bank *bank);
94/* CEs and DEs are combined into 1 cper entry */
95int amdgpu_cper_generate_ce_records(struct amdgpu_device *adev,
96 struct aca_banks *banks,
97 uint16_t bank_count);
98/* Bad page threshold is encoded into separated cper entry */
99int amdgpu_cper_generate_bp_threshold_record(struct amdgpu_device *adev);
100void amdgpu_cper_ring_write(struct amdgpu_ring *ring,
101 void *src, int count);
102int amdgpu_cper_init(struct amdgpu_device *adev);
103int amdgpu_cper_fini(struct amdgpu_device *adev);
104
105#endif
106

source code of linux/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.h