1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27#include <drm/amdgpu_drm.h>
28#include "amdgpu.h"
29#include "amdgpu_atombios.h"
30#include "amdgpu_atomfirmware.h"
31#include "amdgpu_i2c.h"
32#include "amdgpu_display.h"
33
34#include "atom.h"
35#include "atom-bits.h"
36#include "atombios_encoders.h"
37#include "bif/bif_4_1_d.h"
38
39static struct amdgpu_i2c_bus_rec amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
40{
41 struct amdgpu_i2c_bus_rec i2c;
42
43 memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
44
45 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex);
46 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex);
47 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex);
48 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex);
49 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex);
50 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex);
51 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex);
52 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex);
53 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
54 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
55 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
56 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
57 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
58 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
59 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
60 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
61
62 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
63 i2c.hw_capable = true;
64 else
65 i2c.hw_capable = false;
66
67 if (gpio->sucI2cId.ucAccess == 0xa0)
68 i2c.mm_i2c = true;
69 else
70 i2c.mm_i2c = false;
71
72 i2c.i2c_id = gpio->sucI2cId.ucAccess;
73
74 if (i2c.mask_clk_reg)
75 i2c.valid = true;
76 else
77 i2c.valid = false;
78
79 return i2c;
80}
81
82struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev,
83 uint8_t id)
84{
85 struct atom_context *ctx = adev->mode_info.atom_context;
86 ATOM_GPIO_I2C_ASSIGMENT *gpio;
87 struct amdgpu_i2c_bus_rec i2c;
88 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
89 struct _ATOM_GPIO_I2C_INFO *i2c_info;
90 uint16_t data_offset, size;
91 int i, num_indices;
92
93 memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
94 i2c.valid = false;
95
96 if (amdgpu_atom_parse_data_header(ctx, index, size: &size, NULL, NULL, data_start: &data_offset)) {
97 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
98
99 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
100 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
101
102 gpio = &i2c_info->asGPIO_Info[0];
103 for (i = 0; i < num_indices; i++) {
104 if (gpio->sucI2cId.ucAccess == id) {
105 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
106 break;
107 }
108 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
109 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
110 }
111 }
112
113 return i2c;
114}
115
116void amdgpu_atombios_i2c_init(struct amdgpu_device *adev)
117{
118 struct atom_context *ctx = adev->mode_info.atom_context;
119 ATOM_GPIO_I2C_ASSIGMENT *gpio;
120 struct amdgpu_i2c_bus_rec i2c;
121 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
122 struct _ATOM_GPIO_I2C_INFO *i2c_info;
123 uint16_t data_offset, size;
124 int i, num_indices;
125 char stmp[32];
126
127 if (amdgpu_atom_parse_data_header(ctx, index, size: &size, NULL, NULL, data_start: &data_offset)) {
128 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
129
130 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
131 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
132
133 gpio = &i2c_info->asGPIO_Info[0];
134 for (i = 0; i < num_indices; i++) {
135 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
136
137 if (i2c.valid) {
138 sprintf(buf: stmp, fmt: "0x%x", i2c.i2c_id);
139 adev->i2c_bus[i] = amdgpu_i2c_create(dev: adev_to_drm(adev), rec: &i2c, name: stmp);
140 }
141 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
142 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
143 }
144 }
145}
146
147void amdgpu_atombios_oem_i2c_init(struct amdgpu_device *adev, u8 i2c_id)
148{
149 struct atom_context *ctx = adev->mode_info.atom_context;
150 ATOM_GPIO_I2C_ASSIGMENT *gpio;
151 struct amdgpu_i2c_bus_rec i2c;
152 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
153 struct _ATOM_GPIO_I2C_INFO *i2c_info;
154 uint16_t data_offset, size;
155 int i, num_indices;
156 char stmp[32];
157
158 if (amdgpu_atom_parse_data_header(ctx, index, size: &size, NULL, NULL, data_start: &data_offset)) {
159 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
160
161 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
162 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
163
164 gpio = &i2c_info->asGPIO_Info[0];
165 for (i = 0; i < num_indices; i++) {
166 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
167
168 if (i2c.valid && i2c.i2c_id == i2c_id) {
169 sprintf(buf: stmp, fmt: "OEM 0x%x", i2c.i2c_id);
170 adev->i2c_bus[i] = amdgpu_i2c_create(dev: adev_to_drm(adev), rec: &i2c, name: stmp);
171 break;
172 }
173 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
174 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
175 }
176 }
177}
178
179struct amdgpu_gpio_rec
180amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev,
181 u8 id)
182{
183 struct atom_context *ctx = adev->mode_info.atom_context;
184 struct amdgpu_gpio_rec gpio;
185 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
186 struct _ATOM_GPIO_PIN_LUT *gpio_info;
187 ATOM_GPIO_PIN_ASSIGNMENT *pin;
188 u16 data_offset, size;
189 int i, num_indices;
190
191 memset(&gpio, 0, sizeof(struct amdgpu_gpio_rec));
192 gpio.valid = false;
193
194 if (amdgpu_atom_parse_data_header(ctx, index, size: &size, NULL, NULL, data_start: &data_offset)) {
195 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
196
197 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
198 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
199
200 pin = gpio_info->asGPIO_Pin;
201 for (i = 0; i < num_indices; i++) {
202 if (id == pin->ucGPIO_ID) {
203 gpio.id = pin->ucGPIO_ID;
204 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex);
205 gpio.shift = pin->ucGpioPinBitShift;
206 gpio.mask = (1 << pin->ucGpioPinBitShift);
207 gpio.valid = true;
208 break;
209 }
210 pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
211 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
212 }
213 }
214
215 return gpio;
216}
217
218static struct amdgpu_hpd
219amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev,
220 struct amdgpu_gpio_rec *gpio)
221{
222 struct amdgpu_hpd hpd;
223 u32 reg;
224
225 memset(&hpd, 0, sizeof(struct amdgpu_hpd));
226
227 reg = amdgpu_display_hpd_get_gpio_reg(adev);
228
229 hpd.gpio = *gpio;
230 if (gpio->reg == reg) {
231 switch(gpio->mask) {
232 case (1 << 0):
233 hpd.hpd = AMDGPU_HPD_1;
234 break;
235 case (1 << 8):
236 hpd.hpd = AMDGPU_HPD_2;
237 break;
238 case (1 << 16):
239 hpd.hpd = AMDGPU_HPD_3;
240 break;
241 case (1 << 24):
242 hpd.hpd = AMDGPU_HPD_4;
243 break;
244 case (1 << 26):
245 hpd.hpd = AMDGPU_HPD_5;
246 break;
247 case (1 << 28):
248 hpd.hpd = AMDGPU_HPD_6;
249 break;
250 default:
251 hpd.hpd = AMDGPU_HPD_NONE;
252 break;
253 }
254 } else
255 hpd.hpd = AMDGPU_HPD_NONE;
256 return hpd;
257}
258
259static const int object_connector_convert[] = {
260 DRM_MODE_CONNECTOR_Unknown,
261 DRM_MODE_CONNECTOR_DVII,
262 DRM_MODE_CONNECTOR_DVII,
263 DRM_MODE_CONNECTOR_DVID,
264 DRM_MODE_CONNECTOR_DVID,
265 DRM_MODE_CONNECTOR_VGA,
266 DRM_MODE_CONNECTOR_Composite,
267 DRM_MODE_CONNECTOR_SVIDEO,
268 DRM_MODE_CONNECTOR_Unknown,
269 DRM_MODE_CONNECTOR_Unknown,
270 DRM_MODE_CONNECTOR_9PinDIN,
271 DRM_MODE_CONNECTOR_Unknown,
272 DRM_MODE_CONNECTOR_HDMIA,
273 DRM_MODE_CONNECTOR_HDMIB,
274 DRM_MODE_CONNECTOR_LVDS,
275 DRM_MODE_CONNECTOR_9PinDIN,
276 DRM_MODE_CONNECTOR_Unknown,
277 DRM_MODE_CONNECTOR_Unknown,
278 DRM_MODE_CONNECTOR_Unknown,
279 DRM_MODE_CONNECTOR_DisplayPort,
280 DRM_MODE_CONNECTOR_eDP,
281 DRM_MODE_CONNECTOR_Unknown
282};
283
284bool amdgpu_atombios_has_dce_engine_info(struct amdgpu_device *adev)
285{
286 struct amdgpu_mode_info *mode_info = &adev->mode_info;
287 struct atom_context *ctx = mode_info->atom_context;
288 int index = GetIndexIntoMasterTable(DATA, Object_Header);
289 u16 size, data_offset;
290 u8 frev, crev;
291 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
292 ATOM_OBJECT_HEADER *obj_header;
293
294 if (!amdgpu_atom_parse_data_header(ctx, index, size: &size, frev: &frev, crev: &crev, data_start: &data_offset))
295 return false;
296
297 if (crev < 2)
298 return false;
299
300 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
301 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
302 (ctx->bios + data_offset +
303 le16_to_cpu(obj_header->usDisplayPathTableOffset));
304
305 if (path_obj->ucNumOfDispPath)
306 return true;
307 else
308 return false;
309}
310
311bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev)
312{
313 struct amdgpu_mode_info *mode_info = &adev->mode_info;
314 struct atom_context *ctx = mode_info->atom_context;
315 int index = GetIndexIntoMasterTable(DATA, Object_Header);
316 u16 size, data_offset;
317 u8 frev, crev;
318 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
319 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
320 ATOM_OBJECT_TABLE *router_obj;
321 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
322 ATOM_OBJECT_HEADER *obj_header;
323 int i, j, k, path_size, device_support;
324 int connector_type;
325 u16 conn_id, connector_object_id;
326 struct amdgpu_i2c_bus_rec ddc_bus;
327 struct amdgpu_router router;
328 struct amdgpu_gpio_rec gpio;
329 struct amdgpu_hpd hpd;
330
331 if (!amdgpu_atom_parse_data_header(ctx, index, size: &size, frev: &frev, crev: &crev, data_start: &data_offset))
332 return false;
333
334 if (crev < 2)
335 return false;
336
337 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
338 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
339 (ctx->bios + data_offset +
340 le16_to_cpu(obj_header->usDisplayPathTableOffset));
341 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
342 (ctx->bios + data_offset +
343 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
344 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
345 (ctx->bios + data_offset +
346 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
347 router_obj = (ATOM_OBJECT_TABLE *)
348 (ctx->bios + data_offset +
349 le16_to_cpu(obj_header->usRouterObjectTableOffset));
350 device_support = le16_to_cpu(obj_header->usDeviceSupport);
351
352 path_size = 0;
353 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
354 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
355 ATOM_DISPLAY_OBJECT_PATH *path;
356 addr += path_size;
357 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
358 path_size += le16_to_cpu(path->usSize);
359
360 if (device_support & le16_to_cpu(path->usDeviceTag)) {
361 uint8_t con_obj_id =
362 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
363 >> OBJECT_ID_SHIFT;
364
365 /* Skip TV/CV support */
366 if ((le16_to_cpu(path->usDeviceTag) ==
367 ATOM_DEVICE_TV1_SUPPORT) ||
368 (le16_to_cpu(path->usDeviceTag) ==
369 ATOM_DEVICE_CV_SUPPORT))
370 continue;
371
372 if (con_obj_id >= ARRAY_SIZE(object_connector_convert)) {
373 DRM_ERROR("invalid con_obj_id %d for device tag 0x%04x\n",
374 con_obj_id, le16_to_cpu(path->usDeviceTag));
375 continue;
376 }
377
378 connector_type =
379 object_connector_convert[con_obj_id];
380 connector_object_id = con_obj_id;
381
382 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
383 continue;
384
385 router.ddc_valid = false;
386 router.cd_valid = false;
387 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
388 uint8_t grph_obj_type =
389 (le16_to_cpu(path->usGraphicObjIds[j]) &
390 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
391
392 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
393 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
394 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
395 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
396 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
397 (ctx->bios + data_offset +
398 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
399 ATOM_ENCODER_CAP_RECORD *cap_record;
400 u16 caps = 0;
401
402 while (record->ucRecordSize > 0 &&
403 record->ucRecordType > 0 &&
404 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
405 switch (record->ucRecordType) {
406 case ATOM_ENCODER_CAP_RECORD_TYPE:
407 cap_record =(ATOM_ENCODER_CAP_RECORD *)
408 record;
409 caps = le16_to_cpu(cap_record->usEncoderCap);
410 break;
411 }
412 record = (ATOM_COMMON_RECORD_HEADER *)
413 ((char *)record + record->ucRecordSize);
414 }
415 amdgpu_display_add_encoder(adev, encoder_obj,
416 le16_to_cpu(path->usDeviceTag),
417 caps);
418 }
419 }
420 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
421 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
422 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
423 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
424 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
425 (ctx->bios + data_offset +
426 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
427 ATOM_I2C_RECORD *i2c_record;
428 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
429 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
430 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
431 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
432 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
433 (ctx->bios + data_offset +
434 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
435 u8 *num_dst_objs = (u8 *)
436 ((u8 *)router_src_dst_table + 1 +
437 (router_src_dst_table->ucNumberOfSrc * 2));
438 u16 *dst_objs = (u16 *)(num_dst_objs + 1);
439 int enum_id;
440
441 router.router_id = router_obj_id;
442 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
443 if (le16_to_cpu(path->usConnObjectId) ==
444 le16_to_cpu(dst_objs[enum_id]))
445 break;
446 }
447
448 while (record->ucRecordSize > 0 &&
449 record->ucRecordType > 0 &&
450 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
451 switch (record->ucRecordType) {
452 case ATOM_I2C_RECORD_TYPE:
453 i2c_record =
454 (ATOM_I2C_RECORD *)
455 record;
456 i2c_config =
457 (ATOM_I2C_ID_CONFIG_ACCESS *)
458 &i2c_record->sucI2cId;
459 router.i2c_info =
460 amdgpu_atombios_lookup_i2c_gpio(adev,
461 id: i2c_config->
462 ucAccess);
463 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
464 break;
465 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
466 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
467 record;
468 router.ddc_valid = true;
469 router.ddc_mux_type = ddc_path->ucMuxType;
470 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
471 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
472 break;
473 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
474 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
475 record;
476 router.cd_valid = true;
477 router.cd_mux_type = cd_path->ucMuxType;
478 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
479 router.cd_mux_state = cd_path->ucMuxState[enum_id];
480 break;
481 }
482 record = (ATOM_COMMON_RECORD_HEADER *)
483 ((char *)record + record->ucRecordSize);
484 }
485 }
486 }
487 }
488 }
489
490 /* look up gpio for ddc, hpd */
491 ddc_bus.valid = false;
492 hpd.hpd = AMDGPU_HPD_NONE;
493 if ((le16_to_cpu(path->usDeviceTag) &
494 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
495 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
496 if (le16_to_cpu(path->usConnObjectId) ==
497 le16_to_cpu(con_obj->asObjects[j].
498 usObjectID)) {
499 ATOM_COMMON_RECORD_HEADER
500 *record =
501 (ATOM_COMMON_RECORD_HEADER
502 *)
503 (ctx->bios + data_offset +
504 le16_to_cpu(con_obj->
505 asObjects[j].
506 usRecordOffset));
507 ATOM_I2C_RECORD *i2c_record;
508 ATOM_HPD_INT_RECORD *hpd_record;
509 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
510
511 while (record->ucRecordSize > 0 &&
512 record->ucRecordType > 0 &&
513 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
514 switch (record->ucRecordType) {
515 case ATOM_I2C_RECORD_TYPE:
516 i2c_record =
517 (ATOM_I2C_RECORD *)
518 record;
519 i2c_config =
520 (ATOM_I2C_ID_CONFIG_ACCESS *)
521 &i2c_record->sucI2cId;
522 ddc_bus = amdgpu_atombios_lookup_i2c_gpio(adev,
523 id: i2c_config->
524 ucAccess);
525 break;
526 case ATOM_HPD_INT_RECORD_TYPE:
527 hpd_record =
528 (ATOM_HPD_INT_RECORD *)
529 record;
530 gpio = amdgpu_atombios_lookup_gpio(adev,
531 id: hpd_record->ucHPDIntGPIOID);
532 hpd = amdgpu_atombios_get_hpd_info_from_gpio(adev, gpio: &gpio);
533 hpd.plugged_state = hpd_record->ucPlugged_PinState;
534 break;
535 }
536 record =
537 (ATOM_COMMON_RECORD_HEADER
538 *) ((char *)record
539 +
540 record->
541 ucRecordSize);
542 }
543 break;
544 }
545 }
546 }
547
548 /* needed for aux chan transactions */
549 ddc_bus.hpd = hpd.hpd;
550
551 conn_id = le16_to_cpu(path->usConnObjectId);
552
553 amdgpu_display_add_connector(adev,
554 conn_id,
555 le16_to_cpu(path->usDeviceTag),
556 connector_type, &ddc_bus,
557 connector_object_id,
558 &hpd,
559 &router);
560
561 }
562 }
563
564 amdgpu_link_encoder_connector(dev: adev_to_drm(adev));
565
566 return true;
567}
568
569union firmware_info {
570 ATOM_FIRMWARE_INFO info;
571 ATOM_FIRMWARE_INFO_V1_2 info_12;
572 ATOM_FIRMWARE_INFO_V1_3 info_13;
573 ATOM_FIRMWARE_INFO_V1_4 info_14;
574 ATOM_FIRMWARE_INFO_V2_1 info_21;
575 ATOM_FIRMWARE_INFO_V2_2 info_22;
576};
577
578int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev)
579{
580 struct amdgpu_mode_info *mode_info = &adev->mode_info;
581 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
582 uint8_t frev, crev;
583 uint16_t data_offset;
584 int ret = -EINVAL;
585
586 if (amdgpu_atom_parse_data_header(ctx: mode_info->atom_context, index, NULL,
587 frev: &frev, crev: &crev, data_start: &data_offset)) {
588 int i;
589 struct amdgpu_pll *ppll = &adev->clock.ppll[0];
590 struct amdgpu_pll *spll = &adev->clock.spll;
591 struct amdgpu_pll *mpll = &adev->clock.mpll;
592 union firmware_info *firmware_info =
593 (union firmware_info *)(mode_info->atom_context->bios +
594 data_offset);
595 /* pixel clocks */
596 ppll->reference_freq =
597 le16_to_cpu(firmware_info->info.usReferenceClock);
598 ppll->reference_div = 0;
599
600 ppll->pll_out_min =
601 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
602 ppll->pll_out_max =
603 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
604
605 ppll->lcd_pll_out_min =
606 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
607 if (ppll->lcd_pll_out_min == 0)
608 ppll->lcd_pll_out_min = ppll->pll_out_min;
609 ppll->lcd_pll_out_max =
610 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
611 if (ppll->lcd_pll_out_max == 0)
612 ppll->lcd_pll_out_max = ppll->pll_out_max;
613
614 if (ppll->pll_out_min == 0)
615 ppll->pll_out_min = 64800;
616
617 ppll->pll_in_min =
618 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
619 ppll->pll_in_max =
620 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
621
622 ppll->min_post_div = 2;
623 ppll->max_post_div = 0x7f;
624 ppll->min_frac_feedback_div = 0;
625 ppll->max_frac_feedback_div = 9;
626 ppll->min_ref_div = 2;
627 ppll->max_ref_div = 0x3ff;
628 ppll->min_feedback_div = 4;
629 ppll->max_feedback_div = 0xfff;
630 ppll->best_vco = 0;
631
632 for (i = 1; i < AMDGPU_MAX_PPLL; i++)
633 adev->clock.ppll[i] = *ppll;
634
635 /* system clock */
636 spll->reference_freq =
637 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
638 spll->reference_div = 0;
639
640 spll->pll_out_min =
641 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
642 spll->pll_out_max =
643 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
644
645 /* ??? */
646 if (spll->pll_out_min == 0)
647 spll->pll_out_min = 64800;
648
649 spll->pll_in_min =
650 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
651 spll->pll_in_max =
652 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
653
654 spll->min_post_div = 1;
655 spll->max_post_div = 1;
656 spll->min_ref_div = 2;
657 spll->max_ref_div = 0xff;
658 spll->min_feedback_div = 4;
659 spll->max_feedback_div = 0xff;
660 spll->best_vco = 0;
661
662 /* memory clock */
663 mpll->reference_freq =
664 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
665 mpll->reference_div = 0;
666
667 mpll->pll_out_min =
668 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
669 mpll->pll_out_max =
670 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
671
672 /* ??? */
673 if (mpll->pll_out_min == 0)
674 mpll->pll_out_min = 64800;
675
676 mpll->pll_in_min =
677 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
678 mpll->pll_in_max =
679 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
680
681 adev->clock.default_sclk =
682 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
683 adev->clock.default_mclk =
684 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
685
686 mpll->min_post_div = 1;
687 mpll->max_post_div = 1;
688 mpll->min_ref_div = 2;
689 mpll->max_ref_div = 0xff;
690 mpll->min_feedback_div = 4;
691 mpll->max_feedback_div = 0xff;
692 mpll->best_vco = 0;
693
694 /* disp clock */
695 adev->clock.default_dispclk =
696 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
697 /* set a reasonable default for DP */
698 if (adev->clock.default_dispclk < 53900) {
699 DRM_DEBUG("Changing default dispclk from %dMhz to 600Mhz\n",
700 adev->clock.default_dispclk / 100);
701 adev->clock.default_dispclk = 60000;
702 } else if (adev->clock.default_dispclk <= 60000) {
703 DRM_DEBUG("Changing default dispclk from %dMhz to 625Mhz\n",
704 adev->clock.default_dispclk / 100);
705 adev->clock.default_dispclk = 62500;
706 }
707 adev->clock.dp_extclk =
708 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
709
710 adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
711 if (adev->clock.max_pixel_clock == 0)
712 adev->clock.max_pixel_clock = 40000;
713
714 /* not technically a clock, but... */
715 adev->mode_info.firmware_flags =
716 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
717
718 ret = 0;
719 }
720
721 adev->pm.current_sclk = adev->clock.default_sclk;
722 adev->pm.current_mclk = adev->clock.default_mclk;
723
724 return ret;
725}
726
727union gfx_info {
728 ATOM_GFX_INFO_V2_1 info;
729};
730
731int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev)
732{
733 struct amdgpu_mode_info *mode_info = &adev->mode_info;
734 int index = GetIndexIntoMasterTable(DATA, GFX_Info);
735 uint8_t frev, crev;
736 uint16_t data_offset;
737 int ret = -EINVAL;
738
739 if (amdgpu_atom_parse_data_header(ctx: mode_info->atom_context, index, NULL,
740 frev: &frev, crev: &crev, data_start: &data_offset)) {
741 union gfx_info *gfx_info = (union gfx_info *)
742 (mode_info->atom_context->bios + data_offset);
743
744 adev->gfx.config.max_shader_engines = gfx_info->info.max_shader_engines;
745 adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes;
746 adev->gfx.config.max_cu_per_sh = gfx_info->info.max_cu_per_sh;
747 adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se;
748 adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se;
749 adev->gfx.config.max_texture_channel_caches =
750 gfx_info->info.max_texture_channel_caches;
751
752 ret = 0;
753 }
754 return ret;
755}
756
757union igp_info {
758 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
759 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
760 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
761 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
762 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
763 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9;
764};
765
766/*
767 * Return vram width from integrated system info table, if available,
768 * or 0 if not.
769 */
770int amdgpu_atombios_get_vram_width(struct amdgpu_device *adev)
771{
772 struct amdgpu_mode_info *mode_info = &adev->mode_info;
773 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
774 u16 data_offset, size;
775 union igp_info *igp_info;
776 u8 frev, crev;
777
778 /* get any igp specific overrides */
779 if (amdgpu_atom_parse_data_header(ctx: mode_info->atom_context, index, size: &size,
780 frev: &frev, crev: &crev, data_start: &data_offset)) {
781 igp_info = (union igp_info *)
782 (mode_info->atom_context->bios + data_offset);
783 switch (crev) {
784 case 8:
785 case 9:
786 return igp_info->info_8.ucUMAChannelNumber * 64;
787 default:
788 return 0;
789 }
790 }
791
792 return 0;
793}
794
795static void amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device *adev,
796 struct amdgpu_atom_ss *ss,
797 int id)
798{
799 struct amdgpu_mode_info *mode_info = &adev->mode_info;
800 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
801 u16 data_offset, size;
802 union igp_info *igp_info;
803 u8 frev, crev;
804 u16 percentage = 0, rate = 0;
805
806 /* get any igp specific overrides */
807 if (amdgpu_atom_parse_data_header(ctx: mode_info->atom_context, index, size: &size,
808 frev: &frev, crev: &crev, data_start: &data_offset)) {
809 igp_info = (union igp_info *)
810 (mode_info->atom_context->bios + data_offset);
811 switch (crev) {
812 case 6:
813 switch (id) {
814 case ASIC_INTERNAL_SS_ON_TMDS:
815 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
816 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
817 break;
818 case ASIC_INTERNAL_SS_ON_HDMI:
819 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
820 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
821 break;
822 case ASIC_INTERNAL_SS_ON_LVDS:
823 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
824 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
825 break;
826 }
827 break;
828 case 7:
829 switch (id) {
830 case ASIC_INTERNAL_SS_ON_TMDS:
831 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
832 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
833 break;
834 case ASIC_INTERNAL_SS_ON_HDMI:
835 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
836 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
837 break;
838 case ASIC_INTERNAL_SS_ON_LVDS:
839 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
840 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
841 break;
842 }
843 break;
844 case 8:
845 switch (id) {
846 case ASIC_INTERNAL_SS_ON_TMDS:
847 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
848 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
849 break;
850 case ASIC_INTERNAL_SS_ON_HDMI:
851 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
852 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
853 break;
854 case ASIC_INTERNAL_SS_ON_LVDS:
855 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
856 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
857 break;
858 }
859 break;
860 case 9:
861 switch (id) {
862 case ASIC_INTERNAL_SS_ON_TMDS:
863 percentage = le16_to_cpu(igp_info->info_9.usDVISSPercentage);
864 rate = le16_to_cpu(igp_info->info_9.usDVISSpreadRateIn10Hz);
865 break;
866 case ASIC_INTERNAL_SS_ON_HDMI:
867 percentage = le16_to_cpu(igp_info->info_9.usHDMISSPercentage);
868 rate = le16_to_cpu(igp_info->info_9.usHDMISSpreadRateIn10Hz);
869 break;
870 case ASIC_INTERNAL_SS_ON_LVDS:
871 percentage = le16_to_cpu(igp_info->info_9.usLvdsSSPercentage);
872 rate = le16_to_cpu(igp_info->info_9.usLvdsSSpreadRateIn10Hz);
873 break;
874 }
875 break;
876 default:
877 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
878 break;
879 }
880 if (percentage)
881 ss->percentage = percentage;
882 if (rate)
883 ss->rate = rate;
884 }
885}
886
887union asic_ss_info {
888 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
889 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
890 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
891};
892
893union asic_ss_assignment {
894 struct _ATOM_ASIC_SS_ASSIGNMENT v1;
895 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
896 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
897};
898
899bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,
900 struct amdgpu_atom_ss *ss,
901 int id, u32 clock)
902{
903 struct amdgpu_mode_info *mode_info = &adev->mode_info;
904 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
905 uint16_t data_offset, size;
906 union asic_ss_info *ss_info;
907 union asic_ss_assignment *ss_assign;
908 uint8_t frev, crev;
909 int i, num_indices;
910
911 if (id == ASIC_INTERNAL_MEMORY_SS) {
912 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
913 return false;
914 }
915 if (id == ASIC_INTERNAL_ENGINE_SS) {
916 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
917 return false;
918 }
919
920 memset(ss, 0, sizeof(struct amdgpu_atom_ss));
921 if (amdgpu_atom_parse_data_header(ctx: mode_info->atom_context, index, size: &size,
922 frev: &frev, crev: &crev, data_start: &data_offset)) {
923
924 ss_info =
925 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
926
927 switch (frev) {
928 case 1:
929 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
930 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
931
932 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
933 for (i = 0; i < num_indices; i++) {
934 if ((ss_assign->v1.ucClockIndication == id) &&
935 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
936 ss->percentage =
937 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
938 ss->type = ss_assign->v1.ucSpreadSpectrumMode;
939 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
940 ss->percentage_divider = 100;
941 return true;
942 }
943 ss_assign = (union asic_ss_assignment *)
944 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
945 }
946 break;
947 case 2:
948 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
949 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
950 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
951 for (i = 0; i < num_indices; i++) {
952 if ((ss_assign->v2.ucClockIndication == id) &&
953 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
954 ss->percentage =
955 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
956 ss->type = ss_assign->v2.ucSpreadSpectrumMode;
957 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
958 ss->percentage_divider = 100;
959 if ((crev == 2) &&
960 ((id == ASIC_INTERNAL_ENGINE_SS) ||
961 (id == ASIC_INTERNAL_MEMORY_SS)))
962 ss->rate /= 100;
963 return true;
964 }
965 ss_assign = (union asic_ss_assignment *)
966 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
967 }
968 break;
969 case 3:
970 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
971 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
972 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
973 for (i = 0; i < num_indices; i++) {
974 if ((ss_assign->v3.ucClockIndication == id) &&
975 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
976 ss->percentage =
977 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
978 ss->type = ss_assign->v3.ucSpreadSpectrumMode;
979 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
980 if (ss_assign->v3.ucSpreadSpectrumMode &
981 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
982 ss->percentage_divider = 1000;
983 else
984 ss->percentage_divider = 100;
985 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
986 (id == ASIC_INTERNAL_MEMORY_SS))
987 ss->rate /= 100;
988 if (adev->flags & AMD_IS_APU)
989 amdgpu_atombios_get_igp_ss_overrides(adev, ss, id);
990 return true;
991 }
992 ss_assign = (union asic_ss_assignment *)
993 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
994 }
995 break;
996 default:
997 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
998 break;
999 }
1000
1001 }
1002 return false;
1003}
1004
1005union get_clock_dividers {
1006 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
1007 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
1008 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
1009 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
1010 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
1011 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
1012 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
1013};
1014
1015int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,
1016 u8 clock_type,
1017 u32 clock,
1018 bool strobe_mode,
1019 struct atom_clock_dividers *dividers)
1020{
1021 union get_clock_dividers args;
1022 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
1023 u8 frev, crev;
1024
1025 memset(&args, 0, sizeof(args));
1026 memset(dividers, 0, sizeof(struct atom_clock_dividers));
1027
1028 if (!amdgpu_atom_parse_cmd_header(ctx: adev->mode_info.atom_context, index, frev: &frev, crev: &crev))
1029 return -EINVAL;
1030
1031 switch (crev) {
1032 case 2:
1033 case 3:
1034 case 5:
1035 /* r6xx, r7xx, evergreen, ni, si.
1036 * TODO: add support for asic_type <= CHIP_RV770*/
1037 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
1038 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
1039
1040 if (amdgpu_atom_execute_table(ctx: adev->mode_info.atom_context,
1041 index, params: (uint32_t *)&args, params_size: sizeof(args)))
1042 return -EINVAL;
1043
1044 dividers->post_div = args.v3.ucPostDiv;
1045 dividers->enable_post_div = (args.v3.ucCntlFlag &
1046 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
1047 dividers->enable_dithen = (args.v3.ucCntlFlag &
1048 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
1049 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
1050 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
1051 dividers->ref_div = args.v3.ucRefDiv;
1052 dividers->vco_mode = (args.v3.ucCntlFlag &
1053 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
1054 } else {
1055 /* for SI we use ComputeMemoryClockParam for memory plls */
1056 if (adev->asic_type >= CHIP_TAHITI)
1057 return -EINVAL;
1058 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
1059 if (strobe_mode)
1060 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
1061
1062 if (amdgpu_atom_execute_table(ctx: adev->mode_info.atom_context,
1063 index, params: (uint32_t *)&args, params_size: sizeof(args)))
1064 return -EINVAL;
1065
1066 dividers->post_div = args.v5.ucPostDiv;
1067 dividers->enable_post_div = (args.v5.ucCntlFlag &
1068 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
1069 dividers->enable_dithen = (args.v5.ucCntlFlag &
1070 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
1071 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
1072 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
1073 dividers->ref_div = args.v5.ucRefDiv;
1074 dividers->vco_mode = (args.v5.ucCntlFlag &
1075 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
1076 }
1077 break;
1078 case 4:
1079 /* fusion */
1080 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
1081
1082 if (amdgpu_atom_execute_table(ctx: adev->mode_info.atom_context,
1083 index, params: (uint32_t *)&args, params_size: sizeof(args)))
1084 return -EINVAL;
1085
1086 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
1087 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
1088 break;
1089 case 6:
1090 /* CI */
1091 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
1092 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
1093 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
1094
1095 if (amdgpu_atom_execute_table(ctx: adev->mode_info.atom_context,
1096 index, params: (uint32_t *)&args, params_size: sizeof(args)))
1097 return -EINVAL;
1098
1099 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
1100 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
1101 dividers->ref_div = args.v6_out.ucPllRefDiv;
1102 dividers->post_div = args.v6_out.ucPllPostDiv;
1103 dividers->flags = args.v6_out.ucPllCntlFlag;
1104 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
1105 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
1106 break;
1107 default:
1108 return -EINVAL;
1109 }
1110 return 0;
1111}
1112
1113#ifdef CONFIG_DRM_AMDGPU_SI
1114int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev,
1115 u32 clock,
1116 bool strobe_mode,
1117 struct atom_mpll_param *mpll_param)
1118{
1119 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
1120 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
1121 u8 frev, crev;
1122
1123 memset(&args, 0, sizeof(args));
1124 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
1125
1126 if (!amdgpu_atom_parse_cmd_header(ctx: adev->mode_info.atom_context, index, frev: &frev, crev: &crev))
1127 return -EINVAL;
1128
1129 switch (frev) {
1130 case 2:
1131 switch (crev) {
1132 case 1:
1133 /* SI */
1134 args.ulClock = cpu_to_le32(clock); /* 10 khz */
1135 args.ucInputFlag = 0;
1136 if (strobe_mode)
1137 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
1138
1139 if (amdgpu_atom_execute_table(ctx: adev->mode_info.atom_context,
1140 index, params: (uint32_t *)&args, params_size: sizeof(args)))
1141 return -EINVAL;
1142
1143 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
1144 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
1145 mpll_param->post_div = args.ucPostDiv;
1146 mpll_param->dll_speed = args.ucDllSpeed;
1147 mpll_param->bwcntl = args.ucBWCntl;
1148 mpll_param->vco_mode =
1149 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
1150 mpll_param->yclk_sel =
1151 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
1152 mpll_param->qdr =
1153 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
1154 mpll_param->half_rate =
1155 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
1156 break;
1157 default:
1158 return -EINVAL;
1159 }
1160 break;
1161 default:
1162 return -EINVAL;
1163 }
1164 return 0;
1165}
1166
1167int amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,
1168 u32 eng_clock, u32 mem_clock)
1169{
1170 SET_ENGINE_CLOCK_PS_ALLOCATION args;
1171 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
1172 u32 tmp;
1173
1174 memset(&args, 0, sizeof(args));
1175
1176 tmp = eng_clock & SET_CLOCK_FREQ_MASK;
1177 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
1178
1179 args.ulTargetEngineClock = cpu_to_le32(tmp);
1180 if (mem_clock)
1181 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
1182
1183 return amdgpu_atom_execute_table(ctx: adev->mode_info.atom_context, index,
1184 params: (uint32_t *)&args, params_size: sizeof(args));
1185}
1186
1187void amdgpu_atombios_get_default_voltages(struct amdgpu_device *adev,
1188 u16 *vddc, u16 *vddci, u16 *mvdd)
1189{
1190 struct amdgpu_mode_info *mode_info = &adev->mode_info;
1191 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1192 u8 frev, crev;
1193 u16 data_offset;
1194 union firmware_info *firmware_info;
1195
1196 *vddc = 0;
1197 *vddci = 0;
1198 *mvdd = 0;
1199
1200 if (amdgpu_atom_parse_data_header(ctx: mode_info->atom_context, index, NULL,
1201 frev: &frev, crev: &crev, data_start: &data_offset)) {
1202 firmware_info =
1203 (union firmware_info *)(mode_info->atom_context->bios +
1204 data_offset);
1205 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
1206 if ((frev == 2) && (crev >= 2)) {
1207 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
1208 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
1209 }
1210 }
1211}
1212
1213union set_voltage {
1214 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
1215 struct _SET_VOLTAGE_PARAMETERS v1;
1216 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
1217 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
1218};
1219
1220int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type,
1221 u16 voltage_id, u16 *voltage)
1222{
1223 union set_voltage args;
1224 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1225 u8 frev, crev;
1226
1227 if (!amdgpu_atom_parse_cmd_header(ctx: adev->mode_info.atom_context, index, frev: &frev, crev: &crev))
1228 return -EINVAL;
1229
1230 switch (crev) {
1231 case 1:
1232 return -EINVAL;
1233 case 2:
1234 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
1235 args.v2.ucVoltageMode = 0;
1236 args.v2.usVoltageLevel = 0;
1237
1238 if (amdgpu_atom_execute_table(ctx: adev->mode_info.atom_context,
1239 index, params: (uint32_t *)&args, params_size: sizeof(args)))
1240 return -EINVAL;
1241
1242 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
1243 break;
1244 case 3:
1245 args.v3.ucVoltageType = voltage_type;
1246 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
1247 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
1248
1249 if (amdgpu_atom_execute_table(ctx: adev->mode_info.atom_context,
1250 index, params: (uint32_t *)&args, params_size: sizeof(args)))
1251 return -EINVAL;
1252
1253 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
1254 break;
1255 default:
1256 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1257 return -EINVAL;
1258 }
1259
1260 return 0;
1261}
1262
1263int amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device *adev,
1264 u16 *voltage,
1265 u16 leakage_idx)
1266{
1267 return amdgpu_atombios_get_max_vddc(adev, VOLTAGE_TYPE_VDDC, voltage_id: leakage_idx, voltage);
1268}
1269
1270union voltage_object_info {
1271 struct _ATOM_VOLTAGE_OBJECT_INFO v1;
1272 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
1273 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
1274};
1275
1276union voltage_object {
1277 struct _ATOM_VOLTAGE_OBJECT v1;
1278 struct _ATOM_VOLTAGE_OBJECT_V2 v2;
1279 union _ATOM_VOLTAGE_OBJECT_V3 v3;
1280};
1281
1282
1283static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
1284 u8 voltage_type, u8 voltage_mode)
1285{
1286 u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
1287 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
1288 u8 *start = (u8 *)v3;
1289
1290 while (offset < size) {
1291 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
1292 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
1293 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
1294 return vo;
1295 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
1296 }
1297 return NULL;
1298}
1299
1300int amdgpu_atombios_get_svi2_info(struct amdgpu_device *adev,
1301 u8 voltage_type,
1302 u8 *svd_gpio_id, u8 *svc_gpio_id)
1303{
1304 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1305 u8 frev, crev;
1306 u16 data_offset, size;
1307 union voltage_object_info *voltage_info;
1308 union voltage_object *voltage_object = NULL;
1309
1310 if (amdgpu_atom_parse_data_header(ctx: adev->mode_info.atom_context, index, size: &size,
1311 frev: &frev, crev: &crev, data_start: &data_offset)) {
1312 voltage_info = (union voltage_object_info *)
1313 (adev->mode_info.atom_context->bios + data_offset);
1314
1315 switch (frev) {
1316 case 3:
1317 switch (crev) {
1318 case 1:
1319 voltage_object = (union voltage_object *)
1320 amdgpu_atombios_lookup_voltage_object_v3(v3: &voltage_info->v3,
1321 voltage_type,
1322 VOLTAGE_OBJ_SVID2);
1323 if (voltage_object) {
1324 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
1325 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
1326 } else {
1327 return -EINVAL;
1328 }
1329 break;
1330 default:
1331 DRM_ERROR("unknown voltage object table\n");
1332 return -EINVAL;
1333 }
1334 break;
1335 default:
1336 DRM_ERROR("unknown voltage object table\n");
1337 return -EINVAL;
1338 }
1339
1340 }
1341 return 0;
1342}
1343
1344bool
1345amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev,
1346 u8 voltage_type, u8 voltage_mode)
1347{
1348 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1349 u8 frev, crev;
1350 u16 data_offset, size;
1351 union voltage_object_info *voltage_info;
1352
1353 if (amdgpu_atom_parse_data_header(ctx: adev->mode_info.atom_context, index, size: &size,
1354 frev: &frev, crev: &crev, data_start: &data_offset)) {
1355 voltage_info = (union voltage_object_info *)
1356 (adev->mode_info.atom_context->bios + data_offset);
1357
1358 switch (frev) {
1359 case 3:
1360 switch (crev) {
1361 case 1:
1362 if (amdgpu_atombios_lookup_voltage_object_v3(v3: &voltage_info->v3,
1363 voltage_type, voltage_mode))
1364 return true;
1365 break;
1366 default:
1367 DRM_ERROR("unknown voltage object table\n");
1368 return false;
1369 }
1370 break;
1371 default:
1372 DRM_ERROR("unknown voltage object table\n");
1373 return false;
1374 }
1375
1376 }
1377 return false;
1378}
1379
1380int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev,
1381 u8 voltage_type, u8 voltage_mode,
1382 struct atom_voltage_table *voltage_table)
1383{
1384 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1385 u8 frev, crev;
1386 u16 data_offset, size;
1387 int i;
1388 union voltage_object_info *voltage_info;
1389 union voltage_object *voltage_object = NULL;
1390
1391 if (amdgpu_atom_parse_data_header(ctx: adev->mode_info.atom_context, index, size: &size,
1392 frev: &frev, crev: &crev, data_start: &data_offset)) {
1393 voltage_info = (union voltage_object_info *)
1394 (adev->mode_info.atom_context->bios + data_offset);
1395
1396 switch (frev) {
1397 case 3:
1398 switch (crev) {
1399 case 1:
1400 voltage_object = (union voltage_object *)
1401 amdgpu_atombios_lookup_voltage_object_v3(v3: &voltage_info->v3,
1402 voltage_type, voltage_mode);
1403 if (voltage_object) {
1404 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
1405 &voltage_object->v3.asGpioVoltageObj;
1406 VOLTAGE_LUT_ENTRY_V2 *lut;
1407 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
1408 return -EINVAL;
1409 lut = &gpio->asVolGpioLut[0];
1410 for (i = 0; i < gpio->ucGpioEntryNum; i++) {
1411 voltage_table->entries[i].value =
1412 le16_to_cpu(lut->usVoltageValue);
1413 voltage_table->entries[i].smio_low =
1414 le32_to_cpu(lut->ulVoltageId);
1415 lut = (VOLTAGE_LUT_ENTRY_V2 *)
1416 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
1417 }
1418 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
1419 voltage_table->count = gpio->ucGpioEntryNum;
1420 voltage_table->phase_delay = gpio->ucPhaseDelay;
1421 return 0;
1422 }
1423 break;
1424 default:
1425 DRM_ERROR("unknown voltage object table\n");
1426 return -EINVAL;
1427 }
1428 break;
1429 default:
1430 DRM_ERROR("unknown voltage object table\n");
1431 return -EINVAL;
1432 }
1433 }
1434 return -EINVAL;
1435}
1436
1437union vram_info {
1438 struct _ATOM_VRAM_INFO_V3 v1_3;
1439 struct _ATOM_VRAM_INFO_V4 v1_4;
1440 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
1441};
1442
1443#define MEM_ID_MASK 0xff000000
1444#define MEM_ID_SHIFT 24
1445#define CLOCK_RANGE_MASK 0x00ffffff
1446#define CLOCK_RANGE_SHIFT 0
1447#define LOW_NIBBLE_MASK 0xf
1448#define DATA_EQU_PREV 0
1449#define DATA_FROM_TABLE 4
1450
1451int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev,
1452 u8 module_index,
1453 struct atom_mc_reg_table *reg_table)
1454{
1455 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
1456 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
1457 u32 i = 0, j;
1458 u16 data_offset, size;
1459 union vram_info *vram_info;
1460
1461 memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
1462
1463 if (amdgpu_atom_parse_data_header(ctx: adev->mode_info.atom_context, index, size: &size,
1464 frev: &frev, crev: &crev, data_start: &data_offset)) {
1465 vram_info = (union vram_info *)
1466 (adev->mode_info.atom_context->bios + data_offset);
1467 switch (frev) {
1468 case 1:
1469 DRM_ERROR("old table version %d, %d\n", frev, crev);
1470 return -EINVAL;
1471 case 2:
1472 switch (crev) {
1473 case 1:
1474 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
1475 ATOM_INIT_REG_BLOCK *reg_block =
1476 (ATOM_INIT_REG_BLOCK *)
1477 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
1478 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
1479 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1480 ((u8 *)reg_block + (2 * sizeof(u16)) +
1481 le16_to_cpu(reg_block->usRegIndexTblSize));
1482 ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0];
1483 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
1484 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
1485 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
1486 return -EINVAL;
1487 while (i < num_entries) {
1488 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
1489 break;
1490 reg_table->mc_reg_address[i].s1 =
1491 (u16)(le16_to_cpu(format->usRegIndex));
1492 reg_table->mc_reg_address[i].pre_reg_data =
1493 (u8)(format->ucPreRegDataLength);
1494 i++;
1495 format = (ATOM_INIT_REG_INDEX_FORMAT *)
1496 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
1497 }
1498 reg_table->last = i;
1499 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
1500 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
1501 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
1502 >> MEM_ID_SHIFT);
1503 if (module_index == t_mem_id) {
1504 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
1505 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
1506 >> CLOCK_RANGE_SHIFT);
1507 for (i = 0, j = 1; i < reg_table->last; i++) {
1508 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
1509 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1510 (u32)le32_to_cpu(*((u32 *)reg_data + j));
1511 j++;
1512 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
1513 if (i == 0)
1514 continue;
1515 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1516 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
1517 }
1518 }
1519 num_ranges++;
1520 }
1521 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1522 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
1523 }
1524 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
1525 return -EINVAL;
1526 reg_table->num_entries = num_ranges;
1527 } else
1528 return -EINVAL;
1529 break;
1530 default:
1531 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1532 return -EINVAL;
1533 }
1534 break;
1535 default:
1536 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1537 return -EINVAL;
1538 }
1539 return 0;
1540 }
1541 return -EINVAL;
1542}
1543#endif
1544
1545bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev)
1546{
1547 int index = GetIndexIntoMasterTable(DATA, GPUVirtualizationInfo);
1548 u8 frev, crev;
1549 u16 data_offset, size;
1550
1551 if (amdgpu_atom_parse_data_header(ctx: adev->mode_info.atom_context, index, size: &size,
1552 frev: &frev, crev: &crev, data_start: &data_offset))
1553 return true;
1554
1555 return false;
1556}
1557
1558void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock)
1559{
1560 uint32_t bios_6_scratch;
1561
1562 bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6);
1563
1564 if (lock) {
1565 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1566 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
1567 } else {
1568 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1569 bios_6_scratch |= ATOM_S6_ACC_MODE;
1570 }
1571
1572 WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch);
1573}
1574
1575static void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev)
1576{
1577 uint32_t bios_2_scratch, bios_6_scratch;
1578
1579 adev->bios_scratch_reg_offset = mmBIOS_SCRATCH_0;
1580
1581 bios_2_scratch = RREG32(adev->bios_scratch_reg_offset + 2);
1582 bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6);
1583
1584 /* let the bios control the backlight */
1585 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1586
1587 /* tell the bios not to handle mode switching */
1588 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
1589
1590 /* clear the vbios dpms state */
1591 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
1592
1593 WREG32(adev->bios_scratch_reg_offset + 2, bios_2_scratch);
1594 WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch);
1595}
1596
1597void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev,
1598 bool hung)
1599{
1600 u32 tmp = RREG32(adev->bios_scratch_reg_offset + 3);
1601
1602 if (hung)
1603 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1604 else
1605 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1606
1607 WREG32(adev->bios_scratch_reg_offset + 3, tmp);
1608}
1609
1610void amdgpu_atombios_scratch_regs_set_backlight_level(struct amdgpu_device *adev,
1611 u32 backlight_level)
1612{
1613 u32 tmp = RREG32(adev->bios_scratch_reg_offset + 2);
1614
1615 tmp &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
1616 tmp |= (backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
1617 ATOM_S2_CURRENT_BL_LEVEL_MASK;
1618
1619 WREG32(adev->bios_scratch_reg_offset + 2, tmp);
1620}
1621
1622bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev)
1623{
1624 u32 tmp = RREG32(adev->bios_scratch_reg_offset + 7);
1625
1626 if (tmp & ATOM_S7_ASIC_INIT_COMPLETE_MASK)
1627 return false;
1628 else
1629 return true;
1630}
1631
1632/* Atom needs data in little endian format so swap as appropriate when copying
1633 * data to or from atom. Note that atom operates on dw units.
1634 *
1635 * Use to_le=true when sending data to atom and provide at least
1636 * ALIGN(num_bytes,4) bytes in the dst buffer.
1637 *
1638 * Use to_le=false when receiving data from atom and provide ALIGN(num_bytes,4)
1639 * byes in the src buffer.
1640 */
1641void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
1642{
1643#ifdef __BIG_ENDIAN
1644 u32 src_tmp[5], dst_tmp[5];
1645 int i;
1646 u8 align_num_bytes = ALIGN(num_bytes, 4);
1647
1648 if (to_le) {
1649 memcpy(src_tmp, src, num_bytes);
1650 for (i = 0; i < align_num_bytes / 4; i++)
1651 dst_tmp[i] = cpu_to_le32(src_tmp[i]);
1652 memcpy(dst, dst_tmp, align_num_bytes);
1653 } else {
1654 memcpy(src_tmp, src, align_num_bytes);
1655 for (i = 0; i < align_num_bytes / 4; i++)
1656 dst_tmp[i] = le32_to_cpu(src_tmp[i]);
1657 memcpy(dst, dst_tmp, num_bytes);
1658 }
1659#else
1660 memcpy(dst, src, num_bytes);
1661#endif
1662}
1663
1664static int amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device *adev)
1665{
1666 struct atom_context *ctx = adev->mode_info.atom_context;
1667 int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware);
1668 uint16_t data_offset;
1669 int usage_bytes = 0;
1670 struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage;
1671 u64 start_addr;
1672 u64 size;
1673
1674 if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, data_start: &data_offset)) {
1675 firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset);
1676
1677 DRM_DEBUG("atom firmware requested %08x %dkb\n",
1678 le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware),
1679 le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb));
1680
1681 start_addr = firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware;
1682 size = firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb;
1683
1684 if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
1685 (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
1686 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
1687 /* Firmware request VRAM reservation for SR-IOV */
1688 adev->mman.fw_vram_usage_start_offset = (start_addr &
1689 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
1690 adev->mman.fw_vram_usage_size = size << 10;
1691 /* Use the default scratch size */
1692 usage_bytes = 0;
1693 } else {
1694 usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024;
1695 }
1696 }
1697 ctx->scratch_size_bytes = 0;
1698 if (usage_bytes == 0)
1699 usage_bytes = 20 * 1024;
1700 /* allocate some scratch memory */
1701 ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
1702 if (!ctx->scratch)
1703 return -ENOMEM;
1704 ctx->scratch_size_bytes = usage_bytes;
1705 return 0;
1706}
1707
1708/* ATOM accessor methods */
1709/*
1710 * ATOM is an interpreted byte code stored in tables in the vbios. The
1711 * driver registers callbacks to access registers and the interpreter
1712 * in the driver parses the tables and executes then to program specific
1713 * actions (set display modes, asic init, etc.). See amdgpu_atombios.c,
1714 * atombios.h, and atom.c
1715 */
1716
1717/**
1718 * cail_pll_read - read PLL register
1719 *
1720 * @info: atom card_info pointer
1721 * @reg: PLL register offset
1722 *
1723 * Provides a PLL register accessor for the atom interpreter (r4xx+).
1724 * Returns the value of the PLL register.
1725 */
1726static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
1727{
1728 return 0;
1729}
1730
1731/**
1732 * cail_pll_write - write PLL register
1733 *
1734 * @info: atom card_info pointer
1735 * @reg: PLL register offset
1736 * @val: value to write to the pll register
1737 *
1738 * Provides a PLL register accessor for the atom interpreter (r4xx+).
1739 */
1740static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
1741{
1742
1743}
1744
1745/**
1746 * cail_mc_read - read MC (Memory Controller) register
1747 *
1748 * @info: atom card_info pointer
1749 * @reg: MC register offset
1750 *
1751 * Provides an MC register accessor for the atom interpreter (r4xx+).
1752 * Returns the value of the MC register.
1753 */
1754static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
1755{
1756 return 0;
1757}
1758
1759/**
1760 * cail_mc_write - write MC (Memory Controller) register
1761 *
1762 * @info: atom card_info pointer
1763 * @reg: MC register offset
1764 * @val: value to write to the pll register
1765 *
1766 * Provides a MC register accessor for the atom interpreter (r4xx+).
1767 */
1768static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
1769{
1770
1771}
1772
1773/**
1774 * cail_reg_write - write MMIO register
1775 *
1776 * @info: atom card_info pointer
1777 * @reg: MMIO register offset
1778 * @val: value to write to the pll register
1779 *
1780 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
1781 */
1782static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
1783{
1784 struct amdgpu_device *adev = drm_to_adev(ddev: info->dev);
1785
1786 WREG32(reg, val);
1787}
1788
1789/**
1790 * cail_reg_read - read MMIO register
1791 *
1792 * @info: atom card_info pointer
1793 * @reg: MMIO register offset
1794 *
1795 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
1796 * Returns the value of the MMIO register.
1797 */
1798static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
1799{
1800 struct amdgpu_device *adev = drm_to_adev(ddev: info->dev);
1801 uint32_t r;
1802
1803 r = RREG32(reg);
1804 return r;
1805}
1806
1807static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev,
1808 struct device_attribute *attr,
1809 char *buf)
1810{
1811 struct drm_device *ddev = dev_get_drvdata(dev);
1812 struct amdgpu_device *adev = drm_to_adev(ddev);
1813 struct atom_context *ctx = adev->mode_info.atom_context;
1814
1815 return sysfs_emit(buf, fmt: "%s\n", ctx->vbios_pn);
1816}
1817
1818static ssize_t amdgpu_atombios_get_vbios_build(struct device *dev,
1819 struct device_attribute *attr,
1820 char *buf)
1821{
1822 struct drm_device *ddev = dev_get_drvdata(dev);
1823 struct amdgpu_device *adev = drm_to_adev(ddev);
1824 struct atom_context *ctx = adev->mode_info.atom_context;
1825
1826 return sysfs_emit(buf, fmt: "%s\n", ctx->build_num);
1827}
1828
1829static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version,
1830 NULL);
1831static DEVICE_ATTR(vbios_build, 0444, amdgpu_atombios_get_vbios_build, NULL);
1832
1833static struct attribute *amdgpu_vbios_version_attrs[] = {
1834 &dev_attr_vbios_version.attr, &dev_attr_vbios_build.attr, NULL
1835};
1836
1837static umode_t amdgpu_vbios_version_attrs_is_visible(struct kobject *kobj,
1838 struct attribute *attr,
1839 int index)
1840{
1841 struct device *dev = kobj_to_dev(kobj);
1842 struct drm_device *ddev = dev_get_drvdata(dev);
1843 struct amdgpu_device *adev = drm_to_adev(ddev);
1844 struct atom_context *ctx = adev->mode_info.atom_context;
1845
1846 if (attr == &dev_attr_vbios_build.attr && !strlen(ctx->build_num))
1847 return 0;
1848
1849 return attr->mode;
1850}
1851
1852const struct attribute_group amdgpu_vbios_version_attr_group = {
1853 .attrs = amdgpu_vbios_version_attrs,
1854 .is_visible = amdgpu_vbios_version_attrs_is_visible,
1855};
1856
1857int amdgpu_atombios_sysfs_init(struct amdgpu_device *adev)
1858{
1859 if (adev->mode_info.atom_context)
1860 return devm_device_add_group(dev: adev->dev,
1861 grp: &amdgpu_vbios_version_attr_group);
1862
1863 return 0;
1864}
1865
1866/**
1867 * amdgpu_atombios_fini - free the driver info and callbacks for atombios
1868 *
1869 * @adev: amdgpu_device pointer
1870 *
1871 * Frees the driver info and register access callbacks for the ATOM
1872 * interpreter (r4xx+).
1873 * Called at driver shutdown.
1874 */
1875void amdgpu_atombios_fini(struct amdgpu_device *adev)
1876{
1877 if (adev->mode_info.atom_context) {
1878 kfree(objp: adev->mode_info.atom_context->scratch);
1879 kfree(objp: adev->mode_info.atom_context->iio);
1880 }
1881 kfree(objp: adev->mode_info.atom_context);
1882 adev->mode_info.atom_context = NULL;
1883 kfree(objp: adev->mode_info.atom_card_info);
1884 adev->mode_info.atom_card_info = NULL;
1885}
1886
1887/**
1888 * amdgpu_atombios_init - init the driver info and callbacks for atombios
1889 *
1890 * @adev: amdgpu_device pointer
1891 *
1892 * Initializes the driver info and register access callbacks for the
1893 * ATOM interpreter (r4xx+).
1894 * Returns 0 on sucess, -ENOMEM on failure.
1895 * Called at driver startup.
1896 */
1897int amdgpu_atombios_init(struct amdgpu_device *adev)
1898{
1899 struct card_info *atom_card_info =
1900 kzalloc(sizeof(struct card_info), GFP_KERNEL);
1901
1902 if (!atom_card_info)
1903 return -ENOMEM;
1904
1905 adev->mode_info.atom_card_info = atom_card_info;
1906 atom_card_info->dev = adev_to_drm(adev);
1907 atom_card_info->reg_read = cail_reg_read;
1908 atom_card_info->reg_write = cail_reg_write;
1909 atom_card_info->mc_read = cail_mc_read;
1910 atom_card_info->mc_write = cail_mc_write;
1911 atom_card_info->pll_read = cail_pll_read;
1912 atom_card_info->pll_write = cail_pll_write;
1913
1914 adev->mode_info.atom_context = amdgpu_atom_parse(card: atom_card_info, bios: adev->bios);
1915 if (!adev->mode_info.atom_context) {
1916 amdgpu_atombios_fini(adev);
1917 return -ENOMEM;
1918 }
1919
1920 mutex_init(&adev->mode_info.atom_context->mutex);
1921 if (adev->is_atom_fw) {
1922 amdgpu_atomfirmware_scratch_regs_init(adev);
1923 amdgpu_atomfirmware_allocate_fb_scratch(adev);
1924 /* cached firmware_flags for further usage */
1925 adev->mode_info.firmware_flags =
1926 amdgpu_atomfirmware_query_firmware_capability(adev);
1927 } else {
1928 amdgpu_atombios_scratch_regs_init(adev);
1929 amdgpu_atombios_allocate_fb_scratch(adev);
1930 }
1931
1932 return 0;
1933}
1934
1935int amdgpu_atombios_get_data_table(struct amdgpu_device *adev,
1936 uint32_t table,
1937 uint16_t *size,
1938 uint8_t *frev,
1939 uint8_t *crev,
1940 uint8_t **addr)
1941{
1942 uint16_t data_start;
1943
1944 if (!amdgpu_atom_parse_data_header(ctx: adev->mode_info.atom_context, index: table,
1945 size, frev, crev, data_start: &data_start))
1946 return -EINVAL;
1947
1948 *addr = (uint8_t *)adev->mode_info.atom_context->bios + data_start;
1949
1950 return 0;
1951}
1952

source code of linux/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c