1// SPDX-License-Identifier: GPL-2.0-only
2// Copyright (C) 2015-2017 Broadcom
3
4#include <linux/bitops.h>
5#include <linux/gpio/driver.h>
6#include <linux/gpio/generic.h>
7#include <linux/of.h>
8#include <linux/module.h>
9#include <linux/irqdomain.h>
10#include <linux/irqchip/chained_irq.h>
11#include <linux/interrupt.h>
12#include <linux/platform_device.h>
13#include <linux/string_choices.h>
14
15enum gio_reg_index {
16 GIO_REG_ODEN = 0,
17 GIO_REG_DATA,
18 GIO_REG_IODIR,
19 GIO_REG_EC,
20 GIO_REG_EI,
21 GIO_REG_MASK,
22 GIO_REG_LEVEL,
23 GIO_REG_STAT,
24 NUMBER_OF_GIO_REGISTERS
25};
26
27#define GIO_BANK_SIZE (NUMBER_OF_GIO_REGISTERS * sizeof(u32))
28#define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32)))
29#define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN)
30#define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA)
31#define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR)
32#define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC)
33#define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI)
34#define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK)
35#define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL)
36#define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT)
37
38struct brcmstb_gpio_bank {
39 struct list_head node;
40 int id;
41 struct gpio_generic_chip chip;
42 struct brcmstb_gpio_priv *parent_priv;
43 u32 width;
44 u32 wake_active;
45 u32 saved_regs[GIO_REG_STAT]; /* Don't save and restore GIO_REG_STAT */
46};
47
48struct brcmstb_gpio_priv {
49 struct list_head bank_list;
50 void __iomem *reg_base;
51 struct platform_device *pdev;
52 struct irq_domain *irq_domain;
53 struct irq_chip irq_chip;
54 int parent_irq;
55 int num_gpios;
56 int parent_wake_irq;
57};
58
59#define MAX_GPIO_PER_BANK 32
60#define GPIO_BANK(gpio) ((gpio) >> 5)
61/* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
62#define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1))
63
64static inline struct brcmstb_gpio_priv *
65brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
66{
67 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
68 return bank->parent_priv;
69}
70
71static unsigned long
72__brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
73{
74 void __iomem *reg_base = bank->parent_priv->reg_base;
75
76 return gpio_generic_read_reg(chip: &bank->chip, reg: reg_base + GIO_STAT(bank->id)) &
77 gpio_generic_read_reg(chip: &bank->chip, reg: reg_base + GIO_MASK(bank->id));
78}
79
80static unsigned long
81brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
82{
83 unsigned long status;
84
85 guard(gpio_generic_lock_irqsave)(l: &bank->chip);
86
87 status = __brcmstb_gpio_get_active_irqs(bank);
88
89 return status;
90}
91
92static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq,
93 struct brcmstb_gpio_bank *bank)
94{
95 return hwirq - bank->chip.gc.offset;
96}
97
98static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
99 unsigned int hwirq, bool enable)
100{
101 struct brcmstb_gpio_priv *priv = bank->parent_priv;
102 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank));
103 u32 imask;
104
105 guard(gpio_generic_lock_irqsave)(l: &bank->chip);
106
107 imask = gpio_generic_read_reg(chip: &bank->chip,
108 reg: priv->reg_base + GIO_MASK(bank->id));
109 if (enable)
110 imask |= mask;
111 else
112 imask &= ~mask;
113 gpio_generic_write_reg(chip: &bank->chip,
114 reg: priv->reg_base + GIO_MASK(bank->id), val: imask);
115}
116
117static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
118{
119 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
120 /* gc_offset is relative to this gpio_chip; want real offset */
121 int hwirq = offset + gc->offset;
122
123 if (hwirq >= priv->num_gpios)
124 return -ENXIO;
125 return irq_create_mapping(domain: priv->irq_domain, hwirq);
126}
127
128/* -------------------- IRQ chip functions -------------------- */
129
130static void brcmstb_gpio_irq_mask(struct irq_data *d)
131{
132 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
133 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
134
135 brcmstb_gpio_set_imask(bank, hwirq: d->hwirq, enable: false);
136}
137
138static void brcmstb_gpio_irq_unmask(struct irq_data *d)
139{
140 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
141 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
142
143 brcmstb_gpio_set_imask(bank, hwirq: d->hwirq, enable: true);
144}
145
146static void brcmstb_gpio_irq_ack(struct irq_data *d)
147{
148 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
149 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
150 struct brcmstb_gpio_priv *priv = bank->parent_priv;
151 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
152
153 gpio_generic_write_reg(chip: &bank->chip,
154 reg: priv->reg_base + GIO_STAT(bank->id), val: mask);
155}
156
157static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
158{
159 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
160 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
161 struct brcmstb_gpio_priv *priv = bank->parent_priv;
162 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
163 u32 edge_insensitive, iedge_insensitive;
164 u32 edge_config, iedge_config;
165 u32 level, ilevel;
166
167 switch (type) {
168 case IRQ_TYPE_LEVEL_LOW:
169 level = mask;
170 edge_config = 0;
171 edge_insensitive = 0;
172 break;
173 case IRQ_TYPE_LEVEL_HIGH:
174 level = mask;
175 edge_config = mask;
176 edge_insensitive = 0;
177 break;
178 case IRQ_TYPE_EDGE_FALLING:
179 level = 0;
180 edge_config = 0;
181 edge_insensitive = 0;
182 break;
183 case IRQ_TYPE_EDGE_RISING:
184 level = 0;
185 edge_config = mask;
186 edge_insensitive = 0;
187 break;
188 case IRQ_TYPE_EDGE_BOTH:
189 level = 0;
190 edge_config = 0; /* don't care, but want known value */
191 edge_insensitive = mask;
192 break;
193 default:
194 return -EINVAL;
195 }
196
197 guard(gpio_generic_lock_irqsave)(l: &bank->chip);
198
199 iedge_config = gpio_generic_read_reg(chip: &bank->chip,
200 reg: priv->reg_base + GIO_EC(bank->id)) & ~mask;
201 iedge_insensitive = gpio_generic_read_reg(chip: &bank->chip,
202 reg: priv->reg_base + GIO_EI(bank->id)) & ~mask;
203 ilevel = gpio_generic_read_reg(chip: &bank->chip,
204 reg: priv->reg_base + GIO_LEVEL(bank->id)) & ~mask;
205
206 gpio_generic_write_reg(chip: &bank->chip,
207 reg: priv->reg_base + GIO_EC(bank->id),
208 val: iedge_config | edge_config);
209 gpio_generic_write_reg(chip: &bank->chip,
210 reg: priv->reg_base + GIO_EI(bank->id),
211 val: iedge_insensitive | edge_insensitive);
212 gpio_generic_write_reg(chip: &bank->chip,
213 reg: priv->reg_base + GIO_LEVEL(bank->id),
214 val: ilevel | level);
215
216 return 0;
217}
218
219static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv,
220 unsigned int enable)
221{
222 int ret = 0;
223
224 if (enable)
225 ret = enable_irq_wake(irq: priv->parent_wake_irq);
226 else
227 ret = disable_irq_wake(irq: priv->parent_wake_irq);
228 if (ret)
229 dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n",
230 str_enable_disable(enable));
231 return ret;
232}
233
234static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
235{
236 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
237 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
238 struct brcmstb_gpio_priv *priv = bank->parent_priv;
239 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
240
241 /*
242 * Do not do anything specific for now, suspend/resume callbacks will
243 * configure the interrupt mask appropriately
244 */
245 if (enable)
246 bank->wake_active |= mask;
247 else
248 bank->wake_active &= ~mask;
249
250 return brcmstb_gpio_priv_set_wake(priv, enable);
251}
252
253static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
254{
255 struct brcmstb_gpio_priv *priv = data;
256
257 if (!priv || irq != priv->parent_wake_irq)
258 return IRQ_NONE;
259
260 /* Nothing to do */
261 return IRQ_HANDLED;
262}
263
264static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
265{
266 struct brcmstb_gpio_priv *priv = bank->parent_priv;
267 struct irq_domain *domain = priv->irq_domain;
268 int hwbase = bank->chip.gc.offset;
269 unsigned long status;
270
271 while ((status = brcmstb_gpio_get_active_irqs(bank))) {
272 unsigned int offset;
273
274 for_each_set_bit(offset, &status, 32) {
275 if (offset >= bank->width)
276 dev_warn(&priv->pdev->dev,
277 "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
278 bank->id, offset);
279 generic_handle_domain_irq(domain, hwirq: hwbase + offset);
280 }
281 }
282}
283
284/* Each UPG GIO block has one IRQ for all banks */
285static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
286{
287 struct brcmstb_gpio_priv *priv = irq_desc_get_handler_data(desc);
288 struct irq_chip *chip = irq_desc_get_chip(desc);
289 struct brcmstb_gpio_bank *bank;
290
291 /* Interrupts weren't properly cleared during probe */
292 BUG_ON(!priv || !chip);
293
294 chained_irq_enter(chip, desc);
295 list_for_each_entry(bank, &priv->bank_list, node)
296 brcmstb_gpio_irq_bank_handler(bank);
297 chained_irq_exit(chip, desc);
298}
299
300static struct brcmstb_gpio_bank *brcmstb_gpio_hwirq_to_bank(
301 struct brcmstb_gpio_priv *priv, irq_hw_number_t hwirq)
302{
303 struct brcmstb_gpio_bank *bank;
304
305 list_for_each_entry(bank, &priv->bank_list, node) {
306 if (hwirq >= bank->chip.gc.offset &&
307 hwirq < (bank->chip.gc.offset + bank->chip.gc.ngpio))
308 return bank;
309 }
310 return NULL;
311}
312
313/*
314 * This lock class tells lockdep that GPIO irqs are in a different
315 * category than their parents, so it won't report false recursion.
316 */
317static struct lock_class_key brcmstb_gpio_irq_lock_class;
318static struct lock_class_key brcmstb_gpio_irq_request_class;
319
320
321static int brcmstb_gpio_irq_map(struct irq_domain *d, unsigned int irq,
322 irq_hw_number_t hwirq)
323{
324 struct brcmstb_gpio_priv *priv = d->host_data;
325 struct brcmstb_gpio_bank *bank =
326 brcmstb_gpio_hwirq_to_bank(priv, hwirq);
327 struct platform_device *pdev = priv->pdev;
328 int ret;
329
330 if (!bank)
331 return -EINVAL;
332
333 dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n",
334 irq, (int)hwirq, bank->id);
335 ret = irq_set_chip_data(irq, data: &bank->chip.gc);
336 if (ret < 0)
337 return ret;
338 irq_set_lockdep_class(irq, lock_class: &brcmstb_gpio_irq_lock_class,
339 request_class: &brcmstb_gpio_irq_request_class);
340 irq_set_chip_and_handler(irq, chip: &priv->irq_chip, handle: handle_level_irq);
341 irq_set_noprobe(irq);
342 return 0;
343}
344
345static void brcmstb_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
346{
347 irq_set_chip_and_handler(irq, NULL, NULL);
348 irq_set_chip_data(irq, NULL);
349}
350
351static const struct irq_domain_ops brcmstb_gpio_irq_domain_ops = {
352 .map = brcmstb_gpio_irq_map,
353 .unmap = brcmstb_gpio_irq_unmap,
354 .xlate = irq_domain_xlate_twocell,
355};
356
357/* Make sure that the number of banks matches up between properties */
358static int brcmstb_gpio_sanity_check_banks(struct device *dev,
359 struct device_node *np, struct resource *res)
360{
361 int res_num_banks = resource_size(res) / GIO_BANK_SIZE;
362 int num_banks =
363 of_property_count_u32_elems(np, propname: "brcm,gpio-bank-widths");
364
365 if (res_num_banks != num_banks) {
366 dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
367 res_num_banks, num_banks);
368 return -EINVAL;
369 } else {
370 return 0;
371 }
372}
373
374static void brcmstb_gpio_remove(struct platform_device *pdev)
375{
376 struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
377 struct brcmstb_gpio_bank *bank;
378 int offset, virq;
379
380 if (priv->parent_irq > 0)
381 irq_set_chained_handler_and_data(irq: priv->parent_irq, NULL, NULL);
382
383 /* Remove all IRQ mappings and delete the domain */
384 if (priv->irq_domain) {
385 for (offset = 0; offset < priv->num_gpios; offset++) {
386 virq = irq_find_mapping(domain: priv->irq_domain, hwirq: offset);
387 irq_dispose_mapping(virq);
388 }
389 irq_domain_remove(domain: priv->irq_domain);
390 }
391
392 /*
393 * You can lose return values below, but we report all errors, and it's
394 * more important to actually perform all of the steps.
395 */
396 list_for_each_entry(bank, &priv->bank_list, node)
397 gpiochip_remove(gc: &bank->chip.gc);
398}
399
400static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
401 const struct of_phandle_args *gpiospec, u32 *flags)
402{
403 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
404 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
405 int offset;
406
407 if (gc->of_gpio_n_cells != 2) {
408 WARN_ON(1);
409 return -EINVAL;
410 }
411
412 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
413 return -EINVAL;
414
415 offset = gpiospec->args[0] - bank->chip.gc.offset;
416 if (offset >= gc->ngpio || offset < 0)
417 return -EINVAL;
418
419 if (unlikely(offset >= bank->width)) {
420 dev_warn_ratelimited(&priv->pdev->dev,
421 "Received request for invalid GPIO offset %d\n",
422 gpiospec->args[0]);
423 }
424
425 if (flags)
426 *flags = gpiospec->args[1];
427
428 return offset;
429}
430
431/* priv->parent_irq and priv->num_gpios must be set before calling */
432static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
433 struct brcmstb_gpio_priv *priv)
434{
435 struct device *dev = &pdev->dev;
436 struct device_node *np = dev->of_node;
437 int err;
438
439 priv->irq_domain = irq_domain_create_linear(dev_fwnode(dev), size: priv->num_gpios,
440 ops: &brcmstb_gpio_irq_domain_ops, host_data: priv);
441 if (!priv->irq_domain) {
442 dev_err(dev, "Couldn't allocate IRQ domain\n");
443 return -ENXIO;
444 }
445
446 if (of_property_read_bool(np, propname: "wakeup-source")) {
447 priv->parent_wake_irq = platform_get_irq(pdev, 1);
448 if (priv->parent_wake_irq < 0) {
449 priv->parent_wake_irq = 0;
450 dev_warn(dev,
451 "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
452 } else {
453 /*
454 * Set wakeup capability so we can process boot-time
455 * "wakeups" (e.g., from S5 cold boot)
456 */
457 device_set_wakeup_capable(dev, capable: true);
458 device_wakeup_enable(dev);
459 err = devm_request_irq(dev, irq: priv->parent_wake_irq,
460 handler: brcmstb_gpio_wake_irq_handler,
461 IRQF_SHARED,
462 devname: "brcmstb-gpio-wake", dev_id: priv);
463
464 if (err < 0) {
465 dev_err(dev, "Couldn't request wake IRQ");
466 goto out_free_domain;
467 }
468 }
469 }
470
471 priv->irq_chip.name = dev_name(dev);
472 priv->irq_chip.irq_disable = brcmstb_gpio_irq_mask;
473 priv->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
474 priv->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
475 priv->irq_chip.irq_ack = brcmstb_gpio_irq_ack;
476 priv->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
477
478 if (priv->parent_wake_irq)
479 priv->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
480
481 irq_set_chained_handler_and_data(irq: priv->parent_irq,
482 handle: brcmstb_gpio_irq_handler, data: priv);
483 irq_set_status_flags(irq: priv->parent_irq, set: IRQ_DISABLE_UNLAZY);
484
485 return 0;
486
487out_free_domain:
488 irq_domain_remove(domain: priv->irq_domain);
489
490 return err;
491}
492
493static void brcmstb_gpio_bank_save(struct brcmstb_gpio_priv *priv,
494 struct brcmstb_gpio_bank *bank)
495{
496 unsigned int i;
497
498 for (i = 0; i < GIO_REG_STAT; i++)
499 bank->saved_regs[i] = gpio_generic_read_reg(chip: &bank->chip,
500 reg: priv->reg_base + GIO_BANK_OFF(bank->id, i));
501}
502
503static void brcmstb_gpio_quiesce(struct device *dev, bool save)
504{
505 struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
506 struct brcmstb_gpio_bank *bank;
507 u32 imask;
508
509 /* disable non-wake interrupt */
510 if (priv->parent_irq >= 0)
511 disable_irq(irq: priv->parent_irq);
512
513 list_for_each_entry(bank, &priv->bank_list, node) {
514 if (save)
515 brcmstb_gpio_bank_save(priv, bank);
516
517 /* Unmask GPIOs which have been flagged as wake-up sources */
518 if (priv->parent_wake_irq)
519 imask = bank->wake_active;
520 else
521 imask = 0;
522 gpio_generic_write_reg(chip: &bank->chip,
523 reg: priv->reg_base + GIO_MASK(bank->id),
524 val: imask);
525 }
526}
527
528static void brcmstb_gpio_shutdown(struct platform_device *pdev)
529{
530 /* Enable GPIO for S5 cold boot */
531 brcmstb_gpio_quiesce(dev: &pdev->dev, save: false);
532}
533
534static void brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv *priv,
535 struct brcmstb_gpio_bank *bank)
536{
537 unsigned int i;
538
539 for (i = 0; i < GIO_REG_STAT; i++)
540 gpio_generic_write_reg(chip: &bank->chip,
541 reg: priv->reg_base + GIO_BANK_OFF(bank->id, i),
542 val: bank->saved_regs[i]);
543}
544
545static int brcmstb_gpio_suspend(struct device *dev)
546{
547 brcmstb_gpio_quiesce(dev, save: true);
548 return 0;
549}
550
551static int brcmstb_gpio_resume(struct device *dev)
552{
553 struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
554 struct brcmstb_gpio_bank *bank;
555 bool need_wakeup_event = false;
556
557 list_for_each_entry(bank, &priv->bank_list, node) {
558 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
559 brcmstb_gpio_bank_restore(priv, bank);
560 }
561
562 if (priv->parent_wake_irq && need_wakeup_event)
563 pm_wakeup_event(dev, msec: 0);
564
565 /* enable non-wake interrupt */
566 if (priv->parent_irq >= 0)
567 enable_irq(irq: priv->parent_irq);
568
569 return 0;
570}
571
572static const struct dev_pm_ops brcmstb_gpio_pm_ops = {
573 .suspend_noirq = pm_sleep_ptr(brcmstb_gpio_suspend),
574 .resume_noirq = pm_sleep_ptr(brcmstb_gpio_resume),
575};
576
577static int brcmstb_gpio_probe(struct platform_device *pdev)
578{
579 struct gpio_generic_chip_config config;
580 struct device *dev = &pdev->dev;
581 struct device_node *np = dev->of_node;
582 void __iomem *reg_base;
583 struct brcmstb_gpio_priv *priv;
584 struct resource *res;
585 u32 bank_width;
586 int num_banks = 0;
587 int num_gpios = 0;
588 int err;
589 unsigned long flags = 0;
590 bool need_wakeup_event = false;
591
592 priv = devm_kzalloc(dev, size: sizeof(*priv), GFP_KERNEL);
593 if (!priv)
594 return -ENOMEM;
595 platform_set_drvdata(pdev, data: priv);
596 INIT_LIST_HEAD(list: &priv->bank_list);
597
598 reg_base = devm_platform_get_and_ioremap_resource(pdev, index: 0, res: &res);
599 if (IS_ERR(ptr: reg_base))
600 return PTR_ERR(ptr: reg_base);
601
602 priv->reg_base = reg_base;
603 priv->pdev = pdev;
604
605 if (of_property_read_bool(np, propname: "interrupt-controller")) {
606 priv->parent_irq = platform_get_irq(pdev, 0);
607 if (priv->parent_irq <= 0)
608 return -ENOENT;
609 } else {
610 priv->parent_irq = -ENOENT;
611 }
612
613 if (brcmstb_gpio_sanity_check_banks(dev, np, res))
614 return -EINVAL;
615
616 /*
617 * MIPS endianness is configured by boot strap, which also reverses all
618 * bus endianness (i.e., big-endian CPU + big endian bus ==> native
619 * endian I/O).
620 *
621 * Other architectures (e.g., ARM) either do not support big endian, or
622 * else leave I/O in little endian mode.
623 */
624#if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
625 flags = GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER;
626#endif
627
628 of_property_for_each_u32(np, "brcm,gpio-bank-widths", bank_width) {
629 struct brcmstb_gpio_bank *bank;
630 struct gpio_chip *gc;
631
632 /*
633 * If bank_width is 0, then there is an empty bank in the
634 * register block. Special handling for this case.
635 */
636 if (bank_width == 0) {
637 dev_dbg(dev, "Width 0 found: Empty bank @ %d\n",
638 num_banks);
639 num_banks++;
640 num_gpios += MAX_GPIO_PER_BANK;
641 continue;
642 }
643
644 bank = devm_kzalloc(dev, size: sizeof(*bank), GFP_KERNEL);
645 if (!bank) {
646 err = -ENOMEM;
647 goto fail;
648 }
649
650 bank->parent_priv = priv;
651 bank->id = num_banks;
652 if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) {
653 dev_err(dev, "Invalid bank width %d\n", bank_width);
654 err = -EINVAL;
655 goto fail;
656 } else {
657 bank->width = bank_width;
658 }
659
660 gc = &bank->chip.gc;
661
662 /*
663 * Regs are 4 bytes wide, have data reg, no set/clear regs,
664 * and direction bits have 0 = output and 1 = input
665 */
666
667 config = (struct gpio_generic_chip_config) {
668 .dev = dev,
669 .sz = 4,
670 .dat = reg_base + GIO_DATA(bank->id),
671 .dirin = reg_base + GIO_IODIR(bank->id),
672 .flags = flags,
673 };
674
675 err = gpio_generic_chip_init(chip: &bank->chip, cfg: &config);
676 if (err) {
677 dev_err(dev, "failed to initialize generic GPIO chip\n");
678 goto fail;
679 }
680
681 gc->owner = THIS_MODULE;
682 gc->label = devm_kasprintf(dev, GFP_KERNEL, fmt: "%pOF", np);
683 if (!gc->label) {
684 err = -ENOMEM;
685 goto fail;
686 }
687 gc->of_gpio_n_cells = 2;
688 gc->of_xlate = brcmstb_gpio_of_xlate;
689 /* not all ngpio lines are valid, will use bank width later */
690 gc->ngpio = MAX_GPIO_PER_BANK;
691 gc->offset = bank->id * MAX_GPIO_PER_BANK;
692 gc->request = gpiochip_generic_request;
693 gc->free = gpiochip_generic_free;
694 if (priv->parent_irq > 0)
695 gc->to_irq = brcmstb_gpio_to_irq;
696
697 /*
698 * Mask all interrupts by default, since wakeup interrupts may
699 * be retained from S5 cold boot
700 */
701 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
702 gpio_generic_write_reg(chip: &bank->chip,
703 reg: reg_base + GIO_MASK(bank->id), val: 0);
704
705 err = gpiochip_add_data(gc, bank);
706 if (err) {
707 dev_err(dev, "Could not add gpiochip for bank %d\n",
708 bank->id);
709 goto fail;
710 }
711 num_gpios += gc->ngpio;
712
713 dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
714 gc->base, gc->ngpio, bank->width);
715
716 /* Everything looks good, so add bank to list */
717 list_add(new: &bank->node, head: &priv->bank_list);
718
719 num_banks++;
720 }
721
722 priv->num_gpios = num_gpios;
723 if (priv->parent_irq > 0) {
724 err = brcmstb_gpio_irq_setup(pdev, priv);
725 if (err)
726 goto fail;
727 }
728
729 if (priv->parent_wake_irq && need_wakeup_event)
730 pm_wakeup_event(dev, msec: 0);
731
732 return 0;
733
734fail:
735 (void) brcmstb_gpio_remove(pdev);
736 return err;
737}
738
739static const struct of_device_id brcmstb_gpio_of_match[] = {
740 { .compatible = "brcm,brcmstb-gpio" },
741 {},
742};
743
744MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match);
745
746static struct platform_driver brcmstb_gpio_driver = {
747 .driver = {
748 .name = "brcmstb-gpio",
749 .of_match_table = brcmstb_gpio_of_match,
750 .pm = pm_sleep_ptr(&brcmstb_gpio_pm_ops),
751 },
752 .probe = brcmstb_gpio_probe,
753 .remove = brcmstb_gpio_remove,
754 .shutdown = brcmstb_gpio_shutdown,
755};
756module_platform_driver(brcmstb_gpio_driver);
757
758MODULE_AUTHOR("Gregory Fong");
759MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO");
760MODULE_LICENSE("GPL v2");
761

source code of linux/drivers/gpio/gpio-brcmstb.c