1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2019 American Megatrends International LLC.
4 *
5 * Author: Karthikeyan Mani <karthikeyanm@amiindia.co.in>
6 */
7
8#include <linux/bitfield.h>
9#include <linux/cleanup.h>
10#include <linux/clk.h>
11#include <linux/gpio/driver.h>
12#include <linux/hashtable.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/platform_device.h>
18#include <linux/seq_file.h>
19#include <linux/spinlock.h>
20#include <linux/string.h>
21
22#define ASPEED_SGPIO_CTRL 0x54
23
24#define ASPEED_SGPIO_CLK_DIV_MASK GENMASK(31, 16)
25#define ASPEED_SGPIO_ENABLE BIT(0)
26#define ASPEED_SGPIO_PINS_SHIFT 6
27
28struct aspeed_sgpio_pdata {
29 const u32 pin_mask;
30};
31
32struct aspeed_sgpio {
33 struct gpio_chip chip;
34 struct device *dev;
35 struct clk *pclk;
36 raw_spinlock_t lock;
37 void __iomem *base;
38 int irq;
39};
40
41struct aspeed_sgpio_bank {
42 u16 val_regs;
43 u16 rdata_reg;
44 u16 irq_regs;
45 u16 tolerance_regs;
46 const char names[4][3];
47};
48
49/*
50 * Note: The "value" register returns the input value when the GPIO is
51 * configured as an input.
52 *
53 * The "rdata" register returns the output value when the GPIO is
54 * configured as an output.
55 */
56static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = {
57 {
58 .val_regs = 0x0000,
59 .rdata_reg = 0x0070,
60 .irq_regs = 0x0004,
61 .tolerance_regs = 0x0018,
62 .names = { "A", "B", "C", "D" },
63 },
64 {
65 .val_regs = 0x001C,
66 .rdata_reg = 0x0074,
67 .irq_regs = 0x0020,
68 .tolerance_regs = 0x0034,
69 .names = { "E", "F", "G", "H" },
70 },
71 {
72 .val_regs = 0x0038,
73 .rdata_reg = 0x0078,
74 .irq_regs = 0x003C,
75 .tolerance_regs = 0x0050,
76 .names = { "I", "J", "K", "L" },
77 },
78 {
79 .val_regs = 0x0090,
80 .rdata_reg = 0x007C,
81 .irq_regs = 0x0094,
82 .tolerance_regs = 0x00A8,
83 .names = { "M", "N", "O", "P" },
84 },
85};
86
87enum aspeed_sgpio_reg {
88 reg_val,
89 reg_rdata,
90 reg_irq_enable,
91 reg_irq_type0,
92 reg_irq_type1,
93 reg_irq_type2,
94 reg_irq_status,
95 reg_tolerance,
96};
97
98#define GPIO_VAL_VALUE 0x00
99#define GPIO_IRQ_ENABLE 0x00
100#define GPIO_IRQ_TYPE0 0x04
101#define GPIO_IRQ_TYPE1 0x08
102#define GPIO_IRQ_TYPE2 0x0C
103#define GPIO_IRQ_STATUS 0x10
104
105static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
106 const struct aspeed_sgpio_bank *bank,
107 const enum aspeed_sgpio_reg reg)
108{
109 switch (reg) {
110 case reg_val:
111 return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
112 case reg_rdata:
113 return gpio->base + bank->rdata_reg;
114 case reg_irq_enable:
115 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;
116 case reg_irq_type0:
117 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;
118 case reg_irq_type1:
119 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;
120 case reg_irq_type2:
121 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
122 case reg_irq_status:
123 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
124 case reg_tolerance:
125 return gpio->base + bank->tolerance_regs;
126 default:
127 /* acturally if code runs to here, it's an error case */
128 BUG();
129 }
130}
131
132#define GPIO_BANK(x) ((x) >> 6)
133#define GPIO_OFFSET(x) ((x) & GENMASK(5, 0))
134#define GPIO_BIT(x) BIT(GPIO_OFFSET(x) >> 1)
135
136static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
137{
138 unsigned int bank;
139
140 bank = GPIO_BANK(offset);
141
142 WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
143 return &aspeed_sgpio_banks[bank];
144}
145
146static int aspeed_sgpio_init_valid_mask(struct gpio_chip *gc,
147 unsigned long *valid_mask, unsigned int ngpios)
148{
149 bitmap_set(map: valid_mask, start: 0, nbits: ngpios);
150 return 0;
151}
152
153static void aspeed_sgpio_irq_init_valid_mask(struct gpio_chip *gc,
154 unsigned long *valid_mask, unsigned int ngpios)
155{
156 unsigned int i;
157
158 /* input GPIOs are even bits */
159 for (i = 0; i < ngpios; i++) {
160 if (i % 2)
161 clear_bit(nr: i, addr: valid_mask);
162 }
163}
164
165static bool aspeed_sgpio_is_input(unsigned int offset)
166{
167 return !(offset % 2);
168}
169
170static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
171{
172 struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
173 const struct aspeed_sgpio_bank *bank = to_bank(offset);
174 enum aspeed_sgpio_reg reg;
175 int rc = 0;
176
177 guard(raw_spinlock_irqsave)(l: &gpio->lock);
178
179 reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
180 rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));
181
182 return rc;
183}
184
185static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)
186{
187 struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
188 const struct aspeed_sgpio_bank *bank = to_bank(offset);
189 void __iomem *addr_r, *addr_w;
190 u32 reg = 0;
191
192 if (aspeed_sgpio_is_input(offset))
193 return -EINVAL;
194
195 /* Since this is an output, read the cached value from rdata, then
196 * update val. */
197 addr_r = bank_reg(gpio, bank, reg: reg_rdata);
198 addr_w = bank_reg(gpio, bank, reg: reg_val);
199
200 reg = ioread32(addr_r);
201
202 if (val)
203 reg |= GPIO_BIT(offset);
204 else
205 reg &= ~GPIO_BIT(offset);
206
207 iowrite32(reg, addr_w);
208
209 return 0;
210}
211
212static int aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)
213{
214 struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
215
216 guard(raw_spinlock_irqsave)(l: &gpio->lock);
217
218 return sgpio_set_value(gc, offset, val);
219}
220
221static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
222{
223 return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL;
224}
225
226static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
227{
228 struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
229 int rc;
230
231 /* No special action is required for setting the direction; we'll
232 * error-out in sgpio_set_value if this isn't an output GPIO */
233
234 guard(raw_spinlock_irqsave)(l: &gpio->lock);
235
236 rc = sgpio_set_value(gc, offset, val);
237
238 return rc;
239}
240
241static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset)
242{
243 return !!aspeed_sgpio_is_input(offset);
244}
245
246static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
247 struct aspeed_sgpio **gpio,
248 const struct aspeed_sgpio_bank **bank,
249 u32 *bit, int *offset)
250{
251 struct aspeed_sgpio *internal;
252
253 *offset = irqd_to_hwirq(d);
254 internal = irq_data_get_irq_chip_data(d);
255 WARN_ON(!internal);
256
257 *gpio = internal;
258 *bank = to_bank(offset: *offset);
259 *bit = GPIO_BIT(*offset);
260}
261
262static void aspeed_sgpio_irq_ack(struct irq_data *d)
263{
264 const struct aspeed_sgpio_bank *bank;
265 struct aspeed_sgpio *gpio;
266 void __iomem *status_addr;
267 int offset;
268 u32 bit;
269
270 irqd_to_aspeed_sgpio_data(d, gpio: &gpio, bank: &bank, bit: &bit, offset: &offset);
271
272 status_addr = bank_reg(gpio, bank, reg: reg_irq_status);
273
274 guard(raw_spinlock_irqsave)(l: &gpio->lock);
275
276 iowrite32(bit, status_addr);
277}
278
279static void aspeed_sgpio_irq_set_mask(struct irq_data *d, bool set)
280{
281 const struct aspeed_sgpio_bank *bank;
282 struct aspeed_sgpio *gpio;
283 u32 reg, bit;
284 void __iomem *addr;
285 int offset;
286
287 irqd_to_aspeed_sgpio_data(d, gpio: &gpio, bank: &bank, bit: &bit, offset: &offset);
288 addr = bank_reg(gpio, bank, reg: reg_irq_enable);
289
290 /* Unmasking the IRQ */
291 if (set)
292 gpiochip_enable_irq(gc: &gpio->chip, offset: irqd_to_hwirq(d));
293
294 scoped_guard(raw_spinlock_irqsave, &gpio->lock) {
295 reg = ioread32(addr);
296 if (set)
297 reg |= bit;
298 else
299 reg &= ~bit;
300
301 iowrite32(reg, addr);
302 }
303
304 /* Masking the IRQ */
305 if (!set)
306 gpiochip_disable_irq(gc: &gpio->chip, offset: irqd_to_hwirq(d));
307
308
309}
310
311static void aspeed_sgpio_irq_mask(struct irq_data *d)
312{
313 aspeed_sgpio_irq_set_mask(d, set: false);
314}
315
316static void aspeed_sgpio_irq_unmask(struct irq_data *d)
317{
318 aspeed_sgpio_irq_set_mask(d, set: true);
319}
320
321static int aspeed_sgpio_set_type(struct irq_data *d, unsigned int type)
322{
323 u32 type0 = 0;
324 u32 type1 = 0;
325 u32 type2 = 0;
326 u32 bit, reg;
327 const struct aspeed_sgpio_bank *bank;
328 irq_flow_handler_t handler;
329 struct aspeed_sgpio *gpio;
330 void __iomem *addr;
331 int offset;
332
333 irqd_to_aspeed_sgpio_data(d, gpio: &gpio, bank: &bank, bit: &bit, offset: &offset);
334
335 switch (type & IRQ_TYPE_SENSE_MASK) {
336 case IRQ_TYPE_EDGE_BOTH:
337 type2 |= bit;
338 fallthrough;
339 case IRQ_TYPE_EDGE_RISING:
340 type0 |= bit;
341 fallthrough;
342 case IRQ_TYPE_EDGE_FALLING:
343 handler = handle_edge_irq;
344 break;
345 case IRQ_TYPE_LEVEL_HIGH:
346 type0 |= bit;
347 fallthrough;
348 case IRQ_TYPE_LEVEL_LOW:
349 type1 |= bit;
350 handler = handle_level_irq;
351 break;
352 default:
353 return -EINVAL;
354 }
355
356 scoped_guard(raw_spinlock_irqsave, &gpio->lock) {
357 addr = bank_reg(gpio, bank, reg: reg_irq_type0);
358 reg = ioread32(addr);
359 reg = (reg & ~bit) | type0;
360 iowrite32(reg, addr);
361
362 addr = bank_reg(gpio, bank, reg: reg_irq_type1);
363 reg = ioread32(addr);
364 reg = (reg & ~bit) | type1;
365 iowrite32(reg, addr);
366
367 addr = bank_reg(gpio, bank, reg: reg_irq_type2);
368 reg = ioread32(addr);
369 reg = (reg & ~bit) | type2;
370 iowrite32(reg, addr);
371 }
372
373 irq_set_handler_locked(data: d, handler);
374
375 return 0;
376}
377
378static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
379{
380 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
381 struct irq_chip *ic = irq_desc_get_chip(desc);
382 struct aspeed_sgpio *data = gpiochip_get_data(gc);
383 unsigned int i, p;
384 unsigned long reg;
385
386 chained_irq_enter(chip: ic, desc);
387
388 for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
389 const struct aspeed_sgpio_bank *bank = &aspeed_sgpio_banks[i];
390
391 reg = ioread32(bank_reg(gpio: data, bank, reg: reg_irq_status));
392
393 for_each_set_bit(p, &reg, 32)
394 generic_handle_domain_irq(domain: gc->irq.domain, hwirq: (i * 32 + p) * 2);
395 }
396
397 chained_irq_exit(chip: ic, desc);
398}
399
400static void aspeed_sgpio_irq_print_chip(struct irq_data *d, struct seq_file *p)
401{
402 const struct aspeed_sgpio_bank *bank;
403 struct aspeed_sgpio *gpio;
404 u32 bit;
405 int offset;
406
407 irqd_to_aspeed_sgpio_data(d, gpio: &gpio, bank: &bank, bit: &bit, offset: &offset);
408 seq_puts(m: p, s: dev_name(dev: gpio->dev));
409}
410
411static const struct irq_chip aspeed_sgpio_irq_chip = {
412 .irq_ack = aspeed_sgpio_irq_ack,
413 .irq_mask = aspeed_sgpio_irq_mask,
414 .irq_unmask = aspeed_sgpio_irq_unmask,
415 .irq_set_type = aspeed_sgpio_set_type,
416 .irq_print_chip = aspeed_sgpio_irq_print_chip,
417 .flags = IRQCHIP_IMMUTABLE,
418 GPIOCHIP_IRQ_RESOURCE_HELPERS,
419};
420
421static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
422 struct platform_device *pdev)
423{
424 int rc, i;
425 const struct aspeed_sgpio_bank *bank;
426 struct gpio_irq_chip *irq;
427
428 rc = platform_get_irq(pdev, 0);
429 if (rc < 0)
430 return rc;
431
432 gpio->irq = rc;
433
434 /* Disable IRQ and clear Interrupt status registers for all SGPIO Pins. */
435 for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
436 bank = &aspeed_sgpio_banks[i];
437 /* disable irq enable bits */
438 iowrite32(0x00000000, bank_reg(gpio, bank, reg: reg_irq_enable));
439 /* clear status bits */
440 iowrite32(0xffffffff, bank_reg(gpio, bank, reg: reg_irq_status));
441 }
442
443 irq = &gpio->chip.irq;
444 gpio_irq_chip_set_chip(girq: irq, chip: &aspeed_sgpio_irq_chip);
445 irq->init_valid_mask = aspeed_sgpio_irq_init_valid_mask;
446 irq->handler = handle_bad_irq;
447 irq->default_type = IRQ_TYPE_NONE;
448 irq->parent_handler = aspeed_sgpio_irq_handler;
449 irq->parent_handler_data = gpio;
450 irq->parents = &gpio->irq;
451 irq->num_parents = 1;
452
453 /* Apply default IRQ settings */
454 for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
455 bank = &aspeed_sgpio_banks[i];
456 /* set falling or level-low irq */
457 iowrite32(0x00000000, bank_reg(gpio, bank, reg: reg_irq_type0));
458 /* trigger type is edge */
459 iowrite32(0x00000000, bank_reg(gpio, bank, reg: reg_irq_type1));
460 /* single edge trigger */
461 iowrite32(0x00000000, bank_reg(gpio, bank, reg: reg_irq_type2));
462 }
463
464 return 0;
465}
466
467static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = {
468 .pin_mask = GENMASK(9, 6),
469};
470
471static int aspeed_sgpio_reset_tolerance(struct gpio_chip *chip,
472 unsigned int offset, bool enable)
473{
474 struct aspeed_sgpio *gpio = gpiochip_get_data(gc: chip);
475 void __iomem *reg;
476 u32 val;
477
478 reg = bank_reg(gpio, bank: to_bank(offset), reg: reg_tolerance);
479
480 guard(raw_spinlock_irqsave)(l: &gpio->lock);
481
482 val = readl(addr: reg);
483
484 if (enable)
485 val |= GPIO_BIT(offset);
486 else
487 val &= ~GPIO_BIT(offset);
488
489 writel(val, addr: reg);
490
491 return 0;
492}
493
494static int aspeed_sgpio_set_config(struct gpio_chip *chip, unsigned int offset,
495 unsigned long config)
496{
497 unsigned long param = pinconf_to_config_param(config);
498 u32 arg = pinconf_to_config_argument(config);
499
500 if (param == PIN_CONFIG_PERSIST_STATE)
501 return aspeed_sgpio_reset_tolerance(chip, offset, enable: arg);
502
503 return -ENOTSUPP;
504}
505
506static const struct aspeed_sgpio_pdata ast2600_sgpiom_pdata = {
507 .pin_mask = GENMASK(10, 6),
508};
509
510static const struct of_device_id aspeed_sgpio_of_table[] = {
511 { .compatible = "aspeed,ast2400-sgpio", .data = &ast2400_sgpio_pdata, },
512 { .compatible = "aspeed,ast2500-sgpio", .data = &ast2400_sgpio_pdata, },
513 { .compatible = "aspeed,ast2600-sgpiom", .data = &ast2600_sgpiom_pdata, },
514 {}
515};
516
517MODULE_DEVICE_TABLE(of, aspeed_sgpio_of_table);
518
519static int __init aspeed_sgpio_probe(struct platform_device *pdev)
520{
521 u32 nr_gpios, sgpio_freq, sgpio_clk_div, gpio_cnt_regval, pin_mask;
522 const struct aspeed_sgpio_pdata *pdata;
523 struct aspeed_sgpio *gpio;
524 unsigned long apb_freq;
525 int rc;
526
527 gpio = devm_kzalloc(dev: &pdev->dev, size: sizeof(*gpio), GFP_KERNEL);
528 if (!gpio)
529 return -ENOMEM;
530
531 gpio->base = devm_platform_ioremap_resource(pdev, index: 0);
532 if (IS_ERR(ptr: gpio->base))
533 return PTR_ERR(ptr: gpio->base);
534
535 gpio->dev = &pdev->dev;
536
537 pdata = device_get_match_data(dev: &pdev->dev);
538 if (!pdata)
539 return -EINVAL;
540
541 pin_mask = pdata->pin_mask;
542
543 rc = device_property_read_u32(dev: &pdev->dev, propname: "ngpios", val: &nr_gpios);
544 if (rc < 0) {
545 dev_err(&pdev->dev, "Could not read ngpios property\n");
546 return -EINVAL;
547 } else if (nr_gpios % 8) {
548 dev_err(&pdev->dev, "Number of GPIOs not multiple of 8: %d\n",
549 nr_gpios);
550 return -EINVAL;
551 }
552
553 rc = device_property_read_u32(dev: &pdev->dev, propname: "bus-frequency", val: &sgpio_freq);
554 if (rc < 0) {
555 dev_err(&pdev->dev, "Could not read bus-frequency property\n");
556 return -EINVAL;
557 }
558
559 gpio->pclk = devm_clk_get(dev: &pdev->dev, NULL);
560 if (IS_ERR(ptr: gpio->pclk)) {
561 dev_err(&pdev->dev, "devm_clk_get failed\n");
562 return PTR_ERR(ptr: gpio->pclk);
563 }
564
565 apb_freq = clk_get_rate(clk: gpio->pclk);
566
567 /*
568 * From the datasheet,
569 * SGPIO period = 1/PCLK * 2 * (GPIO254[31:16] + 1)
570 * period = 2 * (GPIO254[31:16] + 1) / PCLK
571 * frequency = 1 / (2 * (GPIO254[31:16] + 1) / PCLK)
572 * frequency = PCLK / (2 * (GPIO254[31:16] + 1))
573 * frequency * 2 * (GPIO254[31:16] + 1) = PCLK
574 * GPIO254[31:16] = PCLK / (frequency * 2) - 1
575 */
576 if (sgpio_freq == 0)
577 return -EINVAL;
578
579 sgpio_clk_div = (apb_freq / (sgpio_freq * 2)) - 1;
580
581 if (sgpio_clk_div > (1 << 16) - 1)
582 return -EINVAL;
583
584 gpio_cnt_regval = ((nr_gpios / 8) << ASPEED_SGPIO_PINS_SHIFT) & pin_mask;
585 iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) | gpio_cnt_regval |
586 ASPEED_SGPIO_ENABLE, gpio->base + ASPEED_SGPIO_CTRL);
587
588 raw_spin_lock_init(&gpio->lock);
589
590 gpio->chip.parent = &pdev->dev;
591 gpio->chip.ngpio = nr_gpios * 2;
592 gpio->chip.init_valid_mask = aspeed_sgpio_init_valid_mask;
593 gpio->chip.direction_input = aspeed_sgpio_dir_in;
594 gpio->chip.direction_output = aspeed_sgpio_dir_out;
595 gpio->chip.get_direction = aspeed_sgpio_get_direction;
596 gpio->chip.request = NULL;
597 gpio->chip.free = NULL;
598 gpio->chip.get = aspeed_sgpio_get;
599 gpio->chip.set = aspeed_sgpio_set;
600 gpio->chip.set_config = aspeed_sgpio_set_config;
601 gpio->chip.label = dev_name(dev: &pdev->dev);
602 gpio->chip.base = -1;
603
604 aspeed_sgpio_setup_irqs(gpio, pdev);
605
606 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
607 if (rc < 0)
608 return rc;
609
610 return 0;
611}
612
613static struct platform_driver aspeed_sgpio_driver = {
614 .driver = {
615 .name = KBUILD_MODNAME,
616 .of_match_table = aspeed_sgpio_of_table,
617 },
618};
619
620module_platform_driver_probe(aspeed_sgpio_driver, aspeed_sgpio_probe);
621MODULE_DESCRIPTION("Aspeed Serial GPIO Driver");
622

source code of linux/drivers/gpio/gpio-aspeed-sgpio.c