1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2013 Altera Corporation
4 * Based on gpio-mpc8xxx.c
5 */
6
7#include <linux/bitops.h>
8#include <linux/device.h>
9#include <linux/err.h>
10#include <linux/io.h>
11#include <linux/irq.h>
12#include <linux/mod_devicetable.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/property.h>
16#include <linux/spinlock.h>
17#include <linux/types.h>
18
19#include <linux/gpio/driver.h>
20
21#define ALTERA_GPIO_MAX_NGPIO 32
22#define ALTERA_GPIO_DATA 0x0
23#define ALTERA_GPIO_DIR 0x4
24#define ALTERA_GPIO_IRQ_MASK 0x8
25#define ALTERA_GPIO_EDGE_CAP 0xc
26
27/**
28* struct altera_gpio_chip
29* @gc : GPIO chip structure.
30* @regs : memory mapped IO address for the controller registers.
31* @gpio_lock : synchronization lock so that new irq/set/get requests
32* will be blocked until the current one completes.
33* @interrupt_trigger : specifies the hardware configured IRQ trigger type
34* (rising, falling, both, high)
35*/
36struct altera_gpio_chip {
37 struct gpio_chip gc;
38 void __iomem *regs;
39 raw_spinlock_t gpio_lock;
40 int interrupt_trigger;
41};
42
43static void altera_gpio_irq_unmask(struct irq_data *d)
44{
45 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
46 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
47 unsigned long flags;
48 u32 intmask;
49
50 gpiochip_enable_irq(gc, offset: irqd_to_hwirq(d));
51
52 raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
53 intmask = readl(addr: altera_gc->regs + ALTERA_GPIO_IRQ_MASK);
54 /* Set ALTERA_GPIO_IRQ_MASK bit to unmask */
55 intmask |= BIT(irqd_to_hwirq(d));
56 writel(val: intmask, addr: altera_gc->regs + ALTERA_GPIO_IRQ_MASK);
57 raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
58}
59
60static void altera_gpio_irq_mask(struct irq_data *d)
61{
62 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
63 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
64 unsigned long flags;
65 u32 intmask;
66
67 raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
68 intmask = readl(addr: altera_gc->regs + ALTERA_GPIO_IRQ_MASK);
69 /* Clear ALTERA_GPIO_IRQ_MASK bit to mask */
70 intmask &= ~BIT(irqd_to_hwirq(d));
71 writel(val: intmask, addr: altera_gc->regs + ALTERA_GPIO_IRQ_MASK);
72 raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
73
74 gpiochip_disable_irq(gc, offset: irqd_to_hwirq(d));
75}
76
77/*
78 * This controller's IRQ type is synthesized in hardware, so this function
79 * just checks if the requested set_type matches the synthesized IRQ type
80 */
81static int altera_gpio_irq_set_type(struct irq_data *d,
82 unsigned int type)
83{
84 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
85 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
86
87 if (type == IRQ_TYPE_NONE) {
88 irq_set_handler_locked(data: d, handler: handle_bad_irq);
89 return 0;
90 }
91 if (type == altera_gc->interrupt_trigger) {
92 if (type == IRQ_TYPE_LEVEL_HIGH)
93 irq_set_handler_locked(data: d, handler: handle_level_irq);
94 else
95 irq_set_handler_locked(data: d, handler: handle_simple_irq);
96 return 0;
97 }
98 irq_set_handler_locked(data: d, handler: handle_bad_irq);
99 return -EINVAL;
100}
101
102static unsigned int altera_gpio_irq_startup(struct irq_data *d)
103{
104 altera_gpio_irq_unmask(d);
105
106 return 0;
107}
108
109static int altera_gpio_get(struct gpio_chip *gc, unsigned offset)
110{
111 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
112
113 return !!(readl(addr: altera_gc->regs + ALTERA_GPIO_DATA) & BIT(offset));
114}
115
116static int altera_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
117{
118 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
119 unsigned long flags;
120 unsigned int data_reg;
121
122 raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
123 data_reg = readl(addr: altera_gc->regs + ALTERA_GPIO_DATA);
124 if (value)
125 data_reg |= BIT(offset);
126 else
127 data_reg &= ~BIT(offset);
128 writel(val: data_reg, addr: altera_gc->regs + ALTERA_GPIO_DATA);
129 raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
130
131 return 0;
132}
133
134static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
135{
136 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
137 unsigned long flags;
138 unsigned int gpio_ddr;
139
140 raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
141 /* Set pin as input, assumes software controlled IP */
142 gpio_ddr = readl(addr: altera_gc->regs + ALTERA_GPIO_DIR);
143 gpio_ddr &= ~BIT(offset);
144 writel(val: gpio_ddr, addr: altera_gc->regs + ALTERA_GPIO_DIR);
145 raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
146
147 return 0;
148}
149
150static int altera_gpio_direction_output(struct gpio_chip *gc,
151 unsigned offset, int value)
152{
153 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
154 unsigned long flags;
155 unsigned int data_reg, gpio_ddr;
156
157 raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
158 /* Sets the GPIO value */
159 data_reg = readl(addr: altera_gc->regs + ALTERA_GPIO_DATA);
160 if (value)
161 data_reg |= BIT(offset);
162 else
163 data_reg &= ~BIT(offset);
164 writel(val: data_reg, addr: altera_gc->regs + ALTERA_GPIO_DATA);
165
166 /* Set pin as output, assumes software controlled IP */
167 gpio_ddr = readl(addr: altera_gc->regs + ALTERA_GPIO_DIR);
168 gpio_ddr |= BIT(offset);
169 writel(val: gpio_ddr, addr: altera_gc->regs + ALTERA_GPIO_DIR);
170 raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
171
172 return 0;
173}
174
175static void altera_gpio_irq_edge_handler(struct irq_desc *desc)
176{
177 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
178 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
179 struct irq_domain *irqdomain = gc->irq.domain;
180 struct irq_chip *chip;
181 unsigned long status;
182 int i;
183
184 chip = irq_desc_get_chip(desc);
185
186 chained_irq_enter(chip, desc);
187
188 while ((status =
189 (readl(addr: altera_gc->regs + ALTERA_GPIO_EDGE_CAP) &
190 readl(addr: altera_gc->regs + ALTERA_GPIO_IRQ_MASK)))) {
191 writel(val: status, addr: altera_gc->regs + ALTERA_GPIO_EDGE_CAP);
192 for_each_set_bit(i, &status, gc->ngpio)
193 generic_handle_domain_irq(domain: irqdomain, hwirq: i);
194 }
195
196 chained_irq_exit(chip, desc);
197}
198
199static void altera_gpio_irq_leveL_high_handler(struct irq_desc *desc)
200{
201 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
202 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
203 struct irq_domain *irqdomain = gc->irq.domain;
204 struct irq_chip *chip;
205 unsigned long status;
206 int i;
207
208 chip = irq_desc_get_chip(desc);
209
210 chained_irq_enter(chip, desc);
211
212 status = readl(addr: altera_gc->regs + ALTERA_GPIO_DATA);
213 status &= readl(addr: altera_gc->regs + ALTERA_GPIO_IRQ_MASK);
214
215 for_each_set_bit(i, &status, gc->ngpio)
216 generic_handle_domain_irq(domain: irqdomain, hwirq: i);
217
218 chained_irq_exit(chip, desc);
219}
220
221static const struct irq_chip altera_gpio_irq_chip = {
222 .name = "altera-gpio",
223 .irq_mask = altera_gpio_irq_mask,
224 .irq_unmask = altera_gpio_irq_unmask,
225 .irq_set_type = altera_gpio_irq_set_type,
226 .irq_startup = altera_gpio_irq_startup,
227 .irq_shutdown = altera_gpio_irq_mask,
228 .flags = IRQCHIP_IMMUTABLE,
229 GPIOCHIP_IRQ_RESOURCE_HELPERS,
230};
231
232static int altera_gpio_probe(struct platform_device *pdev)
233{
234 struct device *dev = &pdev->dev;
235 int reg, ret;
236 struct altera_gpio_chip *altera_gc;
237 struct gpio_irq_chip *girq;
238 int mapped_irq;
239
240 altera_gc = devm_kzalloc(dev: &pdev->dev, size: sizeof(*altera_gc), GFP_KERNEL);
241 if (!altera_gc)
242 return -ENOMEM;
243
244 raw_spin_lock_init(&altera_gc->gpio_lock);
245
246 if (device_property_read_u32(dev, propname: "altr,ngpio", val: &reg))
247 /* By default assume maximum ngpio */
248 altera_gc->gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
249 else
250 altera_gc->gc.ngpio = reg;
251
252 if (altera_gc->gc.ngpio > ALTERA_GPIO_MAX_NGPIO) {
253 dev_warn(&pdev->dev,
254 "ngpio is greater than %d, defaulting to %d\n",
255 ALTERA_GPIO_MAX_NGPIO, ALTERA_GPIO_MAX_NGPIO);
256 altera_gc->gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
257 }
258
259 altera_gc->gc.direction_input = altera_gpio_direction_input;
260 altera_gc->gc.direction_output = altera_gpio_direction_output;
261 altera_gc->gc.get = altera_gpio_get;
262 altera_gc->gc.set = altera_gpio_set;
263 altera_gc->gc.owner = THIS_MODULE;
264 altera_gc->gc.parent = &pdev->dev;
265 altera_gc->gc.base = -1;
266
267 altera_gc->gc.label = devm_kasprintf(dev, GFP_KERNEL, fmt: "%pfw", dev_fwnode(dev));
268 if (!altera_gc->gc.label)
269 return -ENOMEM;
270
271 altera_gc->regs = devm_platform_ioremap_resource(pdev, index: 0);
272 if (IS_ERR(ptr: altera_gc->regs))
273 return dev_err_probe(dev, err: PTR_ERR(ptr: altera_gc->regs), fmt: "failed to ioremap memory resource\n");
274
275 mapped_irq = platform_get_irq_optional(pdev, 0);
276 if (mapped_irq < 0)
277 goto skip_irq;
278
279 if (device_property_read_u32(dev, propname: "altr,interrupt-type", val: &reg)) {
280 dev_err(&pdev->dev,
281 "altr,interrupt-type value not set in device tree\n");
282 return -EINVAL;
283 }
284 altera_gc->interrupt_trigger = reg;
285
286 girq = &altera_gc->gc.irq;
287 gpio_irq_chip_set_chip(girq, chip: &altera_gpio_irq_chip);
288
289 if (altera_gc->interrupt_trigger == IRQ_TYPE_LEVEL_HIGH)
290 girq->parent_handler = altera_gpio_irq_leveL_high_handler;
291 else
292 girq->parent_handler = altera_gpio_irq_edge_handler;
293 girq->num_parents = 1;
294 girq->parents = devm_kcalloc(dev: &pdev->dev, n: 1, size: sizeof(*girq->parents),
295 GFP_KERNEL);
296 if (!girq->parents)
297 return -ENOMEM;
298 girq->default_type = IRQ_TYPE_NONE;
299 girq->handler = handle_bad_irq;
300 girq->parents[0] = mapped_irq;
301
302skip_irq:
303 ret = devm_gpiochip_add_data(dev, &altera_gc->gc, altera_gc);
304 if (ret) {
305 dev_err(&pdev->dev, "Failed adding memory mapped gpiochip\n");
306 return ret;
307 }
308
309 return 0;
310}
311
312static const struct of_device_id altera_gpio_of_match[] = {
313 { .compatible = "altr,pio-1.0", },
314 {},
315};
316MODULE_DEVICE_TABLE(of, altera_gpio_of_match);
317
318static struct platform_driver altera_gpio_driver = {
319 .driver = {
320 .name = "altera_gpio",
321 .of_match_table = altera_gpio_of_match,
322 },
323 .probe = altera_gpio_probe,
324};
325
326static int __init altera_gpio_init(void)
327{
328 return platform_driver_register(&altera_gpio_driver);
329}
330subsys_initcall(altera_gpio_init);
331
332static void __exit altera_gpio_exit(void)
333{
334 platform_driver_unregister(&altera_gpio_driver);
335}
336module_exit(altera_gpio_exit);
337
338MODULE_AUTHOR("Tien Hock Loh <thloh@altera.com>");
339MODULE_DESCRIPTION("Altera GPIO driver");
340MODULE_LICENSE("GPL");
341

source code of linux/drivers/gpio/gpio-altera.c