1// SPDX-License-Identifier: GPL-2.0
2// Copyright 2014-2015 Freescale
3// Copyright 2018 NXP
4
5/*
6 * Driver for NXP Layerscape Queue Direct Memory Access Controller
7 *
8 * Author:
9 * Wen He <wen.he_1@nxp.com>
10 * Jiaheng Fan <jiaheng.fan@nxp.com>
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/delay.h>
16#include <linux/of.h>
17#include <linux/of_dma.h>
18#include <linux/dma-mapping.h>
19#include <linux/platform_device.h>
20
21#include "virt-dma.h"
22#include "fsldma.h"
23
24/* Register related definition */
25#define FSL_QDMA_DMR 0x0
26#define FSL_QDMA_DSR 0x4
27#define FSL_QDMA_DEIER 0xe00
28#define FSL_QDMA_DEDR 0xe04
29#define FSL_QDMA_DECFDW0R 0xe10
30#define FSL_QDMA_DECFDW1R 0xe14
31#define FSL_QDMA_DECFDW2R 0xe18
32#define FSL_QDMA_DECFDW3R 0xe1c
33#define FSL_QDMA_DECFQIDR 0xe30
34#define FSL_QDMA_DECBR 0xe34
35
36#define FSL_QDMA_BCQMR(x) (0xc0 + 0x100 * (x))
37#define FSL_QDMA_BCQSR(x) (0xc4 + 0x100 * (x))
38#define FSL_QDMA_BCQEDPA_SADDR(x) (0xc8 + 0x100 * (x))
39#define FSL_QDMA_BCQDPA_SADDR(x) (0xcc + 0x100 * (x))
40#define FSL_QDMA_BCQEEPA_SADDR(x) (0xd0 + 0x100 * (x))
41#define FSL_QDMA_BCQEPA_SADDR(x) (0xd4 + 0x100 * (x))
42#define FSL_QDMA_BCQIER(x) (0xe0 + 0x100 * (x))
43#define FSL_QDMA_BCQIDR(x) (0xe4 + 0x100 * (x))
44
45#define FSL_QDMA_SQDPAR 0x80c
46#define FSL_QDMA_SQEPAR 0x814
47#define FSL_QDMA_BSQMR 0x800
48#define FSL_QDMA_BSQSR 0x804
49#define FSL_QDMA_BSQICR 0x828
50#define FSL_QDMA_CQMR 0xa00
51#define FSL_QDMA_CQDSCR1 0xa08
52#define FSL_QDMA_CQDSCR2 0xa0c
53#define FSL_QDMA_CQIER 0xa10
54#define FSL_QDMA_CQEDR 0xa14
55#define FSL_QDMA_SQCCMR 0xa20
56
57/* Registers for bit and genmask */
58#define FSL_QDMA_CQIDR_SQT BIT(15)
59#define QDMA_CCDF_FORMAT BIT(29)
60#define QDMA_CCDF_SER BIT(30)
61#define QDMA_SG_FIN BIT(30)
62#define QDMA_SG_LEN_MASK GENMASK(29, 0)
63#define QDMA_CCDF_MASK GENMASK(28, 20)
64
65#define FSL_QDMA_DEDR_CLEAR GENMASK(31, 0)
66#define FSL_QDMA_BCQIDR_CLEAR GENMASK(31, 0)
67#define FSL_QDMA_DEIER_CLEAR GENMASK(31, 0)
68
69#define FSL_QDMA_BCQIER_CQTIE BIT(15)
70#define FSL_QDMA_BCQIER_CQPEIE BIT(23)
71#define FSL_QDMA_BSQICR_ICEN BIT(31)
72
73#define FSL_QDMA_BSQICR_ICST(x) ((x) << 16)
74#define FSL_QDMA_CQIER_MEIE BIT(31)
75#define FSL_QDMA_CQIER_TEIE BIT(0)
76#define FSL_QDMA_SQCCMR_ENTER_WM BIT(21)
77
78#define FSL_QDMA_BCQMR_EN BIT(31)
79#define FSL_QDMA_BCQMR_EI BIT(30)
80#define FSL_QDMA_BCQMR_CD_THLD(x) ((x) << 20)
81#define FSL_QDMA_BCQMR_CQ_SIZE(x) ((x) << 16)
82
83#define FSL_QDMA_BCQSR_QF BIT(16)
84#define FSL_QDMA_BCQSR_XOFF BIT(0)
85
86#define FSL_QDMA_BSQMR_EN BIT(31)
87#define FSL_QDMA_BSQMR_DI BIT(30)
88#define FSL_QDMA_BSQMR_CQ_SIZE(x) ((x) << 16)
89
90#define FSL_QDMA_BSQSR_QE BIT(17)
91
92#define FSL_QDMA_DMR_DQD BIT(30)
93#define FSL_QDMA_DSR_DB BIT(31)
94
95/* Size related definition */
96#define FSL_QDMA_QUEUE_MAX 8
97#define FSL_QDMA_COMMAND_BUFFER_SIZE 64
98#define FSL_QDMA_DESCRIPTOR_BUFFER_SIZE 32
99#define FSL_QDMA_CIRCULAR_DESC_SIZE_MIN 64
100#define FSL_QDMA_CIRCULAR_DESC_SIZE_MAX 16384
101#define FSL_QDMA_QUEUE_NUM_MAX 8
102
103/* Field definition for CMD */
104#define FSL_QDMA_CMD_RWTTYPE 0x4
105#define FSL_QDMA_CMD_LWC 0x2
106#define FSL_QDMA_CMD_RWTTYPE_OFFSET 28
107#define FSL_QDMA_CMD_NS_OFFSET 27
108#define FSL_QDMA_CMD_DQOS_OFFSET 24
109#define FSL_QDMA_CMD_WTHROTL_OFFSET 20
110#define FSL_QDMA_CMD_DSEN_OFFSET 19
111#define FSL_QDMA_CMD_LWC_OFFSET 16
112#define FSL_QDMA_CMD_PF BIT(17)
113
114/* Field definition for Descriptor status */
115#define QDMA_CCDF_STATUS_RTE BIT(5)
116#define QDMA_CCDF_STATUS_WTE BIT(4)
117#define QDMA_CCDF_STATUS_CDE BIT(2)
118#define QDMA_CCDF_STATUS_SDE BIT(1)
119#define QDMA_CCDF_STATUS_DDE BIT(0)
120#define QDMA_CCDF_STATUS_MASK (QDMA_CCDF_STATUS_RTE | \
121 QDMA_CCDF_STATUS_WTE | \
122 QDMA_CCDF_STATUS_CDE | \
123 QDMA_CCDF_STATUS_SDE | \
124 QDMA_CCDF_STATUS_DDE)
125
126/* Field definition for Descriptor offset */
127#define QDMA_CCDF_OFFSET 20
128#define QDMA_SDDF_CMD(x) (((u64)(x)) << 32)
129
130/* Field definition for safe loop count*/
131#define FSL_QDMA_HALT_COUNT 1500
132#define FSL_QDMA_MAX_SIZE 16385
133#define FSL_QDMA_COMP_TIMEOUT 1000
134#define FSL_COMMAND_QUEUE_OVERFLLOW 10
135
136#define FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma_engine, x) \
137 (((fsl_qdma_engine)->block_offset) * (x))
138
139/**
140 * struct fsl_qdma_format - This is the struct holding describing compound
141 * descriptor format with qDMA.
142 * @status: Command status and enqueue status notification.
143 * @cfg: Frame offset and frame format.
144 * @addr_lo: Holding the compound descriptor of the lower
145 * 32-bits address in memory 40-bit address.
146 * @addr_hi: Same as above member, but point high 8-bits in
147 * memory 40-bit address.
148 * @__reserved1: Reserved field.
149 * @cfg8b_w1: Compound descriptor command queue origin produced
150 * by qDMA and dynamic debug field.
151 * @__reserved2: Reserved field.
152 * @cmd: Command for QDMA (see FSL_QDMA_CMD_RWTTYPE and
153 * others).
154 * @data: Pointer to the memory 40-bit address, describes DMA
155 * source information and DMA destination information.
156 */
157struct fsl_qdma_format {
158 __le32 status;
159 __le32 cfg;
160 union {
161 struct {
162 __le32 addr_lo;
163 u8 addr_hi;
164 u8 __reserved1[2];
165 u8 cfg8b_w1;
166 } __packed;
167 struct {
168 __le32 __reserved2;
169 __le32 cmd;
170 } __packed;
171 __le64 data;
172 };
173} __packed;
174
175/* qDMA status notification pre information */
176struct fsl_pre_status {
177 u64 addr;
178 u8 queue;
179};
180
181static DEFINE_PER_CPU(struct fsl_pre_status, pre);
182
183struct fsl_qdma_chan {
184 struct virt_dma_chan vchan;
185 struct virt_dma_desc vdesc;
186 enum dma_status status;
187 struct fsl_qdma_engine *qdma;
188 struct fsl_qdma_queue *queue;
189};
190
191struct fsl_qdma_queue {
192 struct fsl_qdma_format *virt_head;
193 struct fsl_qdma_format *virt_tail;
194 struct list_head comp_used;
195 struct list_head comp_free;
196 struct dma_pool *comp_pool;
197 struct dma_pool *desc_pool;
198 spinlock_t queue_lock;
199 dma_addr_t bus_addr;
200 u32 n_cq;
201 u32 id;
202 struct fsl_qdma_format *cq;
203 void __iomem *block_base;
204};
205
206struct fsl_qdma_comp {
207 dma_addr_t bus_addr;
208 dma_addr_t desc_bus_addr;
209 struct fsl_qdma_format *virt_addr;
210 struct fsl_qdma_format *desc_virt_addr;
211 struct fsl_qdma_chan *qchan;
212 struct virt_dma_desc vdesc;
213 struct list_head list;
214};
215
216struct fsl_qdma_engine {
217 struct dma_device dma_dev;
218 void __iomem *ctrl_base;
219 void __iomem *status_base;
220 void __iomem *block_base;
221 u32 n_chans;
222 u32 n_queues;
223 struct mutex fsl_qdma_mutex;
224 int error_irq;
225 int *queue_irq;
226 u32 feature;
227 struct fsl_qdma_queue *queue;
228 struct fsl_qdma_queue **status;
229 struct fsl_qdma_chan *chans;
230 int block_number;
231 int block_offset;
232 int irq_base;
233 int desc_allocated;
234
235};
236
237static inline u64
238qdma_ccdf_addr_get64(const struct fsl_qdma_format *ccdf)
239{
240 return le64_to_cpu(ccdf->data) & (U64_MAX >> 24);
241}
242
243static inline void
244qdma_desc_addr_set64(struct fsl_qdma_format *ccdf, u64 addr)
245{
246 ccdf->addr_hi = upper_32_bits(addr);
247 ccdf->addr_lo = cpu_to_le32(lower_32_bits(addr));
248}
249
250static inline u8
251qdma_ccdf_get_queue(const struct fsl_qdma_format *ccdf)
252{
253 return ccdf->cfg8b_w1 & U8_MAX;
254}
255
256static inline int
257qdma_ccdf_get_offset(const struct fsl_qdma_format *ccdf)
258{
259 return (le32_to_cpu(ccdf->cfg) & QDMA_CCDF_MASK) >> QDMA_CCDF_OFFSET;
260}
261
262static inline void
263qdma_ccdf_set_format(struct fsl_qdma_format *ccdf, int offset)
264{
265 ccdf->cfg = cpu_to_le32(QDMA_CCDF_FORMAT |
266 (offset << QDMA_CCDF_OFFSET));
267}
268
269static inline int
270qdma_ccdf_get_status(const struct fsl_qdma_format *ccdf)
271{
272 return (le32_to_cpu(ccdf->status) & QDMA_CCDF_STATUS_MASK);
273}
274
275static inline void
276qdma_ccdf_set_ser(struct fsl_qdma_format *ccdf, int status)
277{
278 ccdf->status = cpu_to_le32(QDMA_CCDF_SER | status);
279}
280
281static inline void qdma_csgf_set_len(struct fsl_qdma_format *csgf, int len)
282{
283 csgf->cfg = cpu_to_le32(len & QDMA_SG_LEN_MASK);
284}
285
286static inline void qdma_csgf_set_f(struct fsl_qdma_format *csgf, int len)
287{
288 csgf->cfg = cpu_to_le32(QDMA_SG_FIN | (len & QDMA_SG_LEN_MASK));
289}
290
291static u32 qdma_readl(struct fsl_qdma_engine *qdma, void __iomem *addr)
292{
293 return FSL_DMA_IN(qdma, addr, 32);
294}
295
296static void qdma_writel(struct fsl_qdma_engine *qdma, u32 val,
297 void __iomem *addr)
298{
299 FSL_DMA_OUT(qdma, addr, val, 32);
300}
301
302static struct fsl_qdma_chan *to_fsl_qdma_chan(struct dma_chan *chan)
303{
304 return container_of(chan, struct fsl_qdma_chan, vchan.chan);
305}
306
307static struct fsl_qdma_comp *to_fsl_qdma_comp(struct virt_dma_desc *vd)
308{
309 return container_of(vd, struct fsl_qdma_comp, vdesc);
310}
311
312static void fsl_qdma_free_chan_resources(struct dma_chan *chan)
313{
314 struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
315 struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
316 struct fsl_qdma_engine *fsl_qdma = fsl_chan->qdma;
317 struct fsl_qdma_comp *comp_temp, *_comp_temp;
318 unsigned long flags;
319 LIST_HEAD(head);
320
321 spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
322 vchan_get_all_descriptors(vc: &fsl_chan->vchan, head: &head);
323 spin_unlock_irqrestore(lock: &fsl_chan->vchan.lock, flags);
324
325 vchan_dma_desc_free_list(vc: &fsl_chan->vchan, head: &head);
326
327 if (!fsl_queue->comp_pool && !fsl_queue->desc_pool)
328 return;
329
330 list_for_each_entry_safe(comp_temp, _comp_temp,
331 &fsl_queue->comp_used, list) {
332 dma_pool_free(pool: fsl_queue->comp_pool,
333 vaddr: comp_temp->virt_addr,
334 addr: comp_temp->bus_addr);
335 dma_pool_free(pool: fsl_queue->desc_pool,
336 vaddr: comp_temp->desc_virt_addr,
337 addr: comp_temp->desc_bus_addr);
338 list_del(entry: &comp_temp->list);
339 kfree(objp: comp_temp);
340 }
341
342 list_for_each_entry_safe(comp_temp, _comp_temp,
343 &fsl_queue->comp_free, list) {
344 dma_pool_free(pool: fsl_queue->comp_pool,
345 vaddr: comp_temp->virt_addr,
346 addr: comp_temp->bus_addr);
347 dma_pool_free(pool: fsl_queue->desc_pool,
348 vaddr: comp_temp->desc_virt_addr,
349 addr: comp_temp->desc_bus_addr);
350 list_del(entry: &comp_temp->list);
351 kfree(objp: comp_temp);
352 }
353
354 dma_pool_destroy(pool: fsl_queue->comp_pool);
355 dma_pool_destroy(pool: fsl_queue->desc_pool);
356
357 fsl_qdma->desc_allocated--;
358 fsl_queue->comp_pool = NULL;
359 fsl_queue->desc_pool = NULL;
360}
361
362static void fsl_qdma_comp_fill_memcpy(struct fsl_qdma_comp *fsl_comp,
363 dma_addr_t dst, dma_addr_t src, u32 len)
364{
365 struct fsl_qdma_format *sdf, *ddf;
366 struct fsl_qdma_format *ccdf, *csgf_desc, *csgf_src, *csgf_dest;
367
368 ccdf = fsl_comp->virt_addr;
369 csgf_desc = fsl_comp->virt_addr + 1;
370 csgf_src = fsl_comp->virt_addr + 2;
371 csgf_dest = fsl_comp->virt_addr + 3;
372 sdf = fsl_comp->desc_virt_addr;
373 ddf = fsl_comp->desc_virt_addr + 1;
374
375 memset(fsl_comp->virt_addr, 0, FSL_QDMA_COMMAND_BUFFER_SIZE);
376 memset(fsl_comp->desc_virt_addr, 0, FSL_QDMA_DESCRIPTOR_BUFFER_SIZE);
377 /* Head Command Descriptor(Frame Descriptor) */
378 qdma_desc_addr_set64(ccdf, addr: fsl_comp->bus_addr + 16);
379 qdma_ccdf_set_format(ccdf, offset: qdma_ccdf_get_offset(ccdf));
380 qdma_ccdf_set_ser(ccdf, status: qdma_ccdf_get_status(ccdf));
381 /* Status notification is enqueued to status queue. */
382 /* Compound Command Descriptor(Frame List Table) */
383 qdma_desc_addr_set64(ccdf: csgf_desc, addr: fsl_comp->desc_bus_addr);
384 /* It must be 32 as Compound S/G Descriptor */
385 qdma_csgf_set_len(csgf: csgf_desc, len: 32);
386 qdma_desc_addr_set64(ccdf: csgf_src, addr: src);
387 qdma_csgf_set_len(csgf: csgf_src, len);
388 qdma_desc_addr_set64(ccdf: csgf_dest, addr: dst);
389 qdma_csgf_set_len(csgf: csgf_dest, len);
390 /* This entry is the last entry. */
391 qdma_csgf_set_f(csgf: csgf_dest, len);
392 /* Descriptor Buffer */
393 sdf->cmd = cpu_to_le32((FSL_QDMA_CMD_RWTTYPE << FSL_QDMA_CMD_RWTTYPE_OFFSET) |
394 FSL_QDMA_CMD_PF);
395
396 ddf->cmd = cpu_to_le32((FSL_QDMA_CMD_RWTTYPE << FSL_QDMA_CMD_RWTTYPE_OFFSET) |
397 (FSL_QDMA_CMD_LWC << FSL_QDMA_CMD_LWC_OFFSET));
398}
399
400/*
401 * Pre-request full command descriptor for enqueue.
402 */
403static int fsl_qdma_pre_request_enqueue_desc(struct fsl_qdma_queue *queue)
404{
405 int i;
406 struct fsl_qdma_comp *comp_temp, *_comp_temp;
407
408 for (i = 0; i < queue->n_cq + FSL_COMMAND_QUEUE_OVERFLLOW; i++) {
409 comp_temp = kzalloc(sizeof(*comp_temp), GFP_KERNEL);
410 if (!comp_temp)
411 goto err_alloc;
412 comp_temp->virt_addr =
413 dma_pool_alloc(pool: queue->comp_pool, GFP_KERNEL,
414 handle: &comp_temp->bus_addr);
415 if (!comp_temp->virt_addr)
416 goto err_dma_alloc;
417
418 comp_temp->desc_virt_addr =
419 dma_pool_alloc(pool: queue->desc_pool, GFP_KERNEL,
420 handle: &comp_temp->desc_bus_addr);
421 if (!comp_temp->desc_virt_addr)
422 goto err_desc_dma_alloc;
423
424 list_add_tail(new: &comp_temp->list, head: &queue->comp_free);
425 }
426
427 return 0;
428
429err_desc_dma_alloc:
430 dma_pool_free(pool: queue->comp_pool, vaddr: comp_temp->virt_addr,
431 addr: comp_temp->bus_addr);
432
433err_dma_alloc:
434 kfree(objp: comp_temp);
435
436err_alloc:
437 list_for_each_entry_safe(comp_temp, _comp_temp,
438 &queue->comp_free, list) {
439 if (comp_temp->virt_addr)
440 dma_pool_free(pool: queue->comp_pool,
441 vaddr: comp_temp->virt_addr,
442 addr: comp_temp->bus_addr);
443 if (comp_temp->desc_virt_addr)
444 dma_pool_free(pool: queue->desc_pool,
445 vaddr: comp_temp->desc_virt_addr,
446 addr: comp_temp->desc_bus_addr);
447
448 list_del(entry: &comp_temp->list);
449 kfree(objp: comp_temp);
450 }
451
452 return -ENOMEM;
453}
454
455/*
456 * Request a command descriptor for enqueue.
457 */
458static struct fsl_qdma_comp
459*fsl_qdma_request_enqueue_desc(struct fsl_qdma_chan *fsl_chan)
460{
461 unsigned long flags;
462 struct fsl_qdma_comp *comp_temp;
463 int timeout = FSL_QDMA_COMP_TIMEOUT;
464 struct fsl_qdma_queue *queue = fsl_chan->queue;
465
466 while (timeout--) {
467 spin_lock_irqsave(&queue->queue_lock, flags);
468 if (!list_empty(head: &queue->comp_free)) {
469 comp_temp = list_first_entry(&queue->comp_free,
470 struct fsl_qdma_comp,
471 list);
472 list_del(entry: &comp_temp->list);
473
474 spin_unlock_irqrestore(lock: &queue->queue_lock, flags);
475 comp_temp->qchan = fsl_chan;
476 return comp_temp;
477 }
478 spin_unlock_irqrestore(lock: &queue->queue_lock, flags);
479 udelay(usec: 1);
480 }
481
482 return NULL;
483}
484
485static struct fsl_qdma_queue
486*fsl_qdma_alloc_queue_resources(struct platform_device *pdev,
487 struct fsl_qdma_engine *fsl_qdma)
488{
489 int ret, len, i, j;
490 int queue_num, block_number;
491 unsigned int queue_size[FSL_QDMA_QUEUE_MAX];
492 struct fsl_qdma_queue *queue_head, *queue_temp;
493
494 queue_num = fsl_qdma->n_queues;
495 block_number = fsl_qdma->block_number;
496
497 if (queue_num > FSL_QDMA_QUEUE_MAX)
498 queue_num = FSL_QDMA_QUEUE_MAX;
499 len = sizeof(*queue_head) * queue_num * block_number;
500 queue_head = devm_kzalloc(dev: &pdev->dev, size: len, GFP_KERNEL);
501 if (!queue_head)
502 return NULL;
503
504 ret = device_property_read_u32_array(dev: &pdev->dev, propname: "queue-sizes",
505 val: queue_size, nval: queue_num);
506 if (ret) {
507 dev_err(&pdev->dev, "Can't get queue-sizes.\n");
508 return NULL;
509 }
510 for (j = 0; j < block_number; j++) {
511 for (i = 0; i < queue_num; i++) {
512 if (queue_size[i] > FSL_QDMA_CIRCULAR_DESC_SIZE_MAX ||
513 queue_size[i] < FSL_QDMA_CIRCULAR_DESC_SIZE_MIN) {
514 dev_err(&pdev->dev,
515 "Get wrong queue-sizes.\n");
516 return NULL;
517 }
518 queue_temp = queue_head + i + (j * queue_num);
519
520 queue_temp->cq =
521 dmam_alloc_coherent(dev: &pdev->dev,
522 size: sizeof(struct fsl_qdma_format) *
523 queue_size[i],
524 dma_handle: &queue_temp->bus_addr,
525 GFP_KERNEL);
526 if (!queue_temp->cq)
527 return NULL;
528 queue_temp->block_base = fsl_qdma->block_base +
529 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);
530 queue_temp->n_cq = queue_size[i];
531 queue_temp->id = i;
532 queue_temp->virt_head = queue_temp->cq;
533 queue_temp->virt_tail = queue_temp->cq;
534 /*
535 * List for queue command buffer
536 */
537 INIT_LIST_HEAD(list: &queue_temp->comp_used);
538 spin_lock_init(&queue_temp->queue_lock);
539 }
540 }
541 return queue_head;
542}
543
544static struct fsl_qdma_queue
545*fsl_qdma_prep_status_queue(struct platform_device *pdev)
546{
547 int ret;
548 unsigned int status_size;
549 struct fsl_qdma_queue *status_head;
550 struct device_node *np = pdev->dev.of_node;
551
552 ret = of_property_read_u32(np, propname: "status-sizes", out_value: &status_size);
553 if (ret) {
554 dev_err(&pdev->dev, "Can't get status-sizes.\n");
555 return NULL;
556 }
557 if (status_size > FSL_QDMA_CIRCULAR_DESC_SIZE_MAX ||
558 status_size < FSL_QDMA_CIRCULAR_DESC_SIZE_MIN) {
559 dev_err(&pdev->dev, "Get wrong status_size.\n");
560 return NULL;
561 }
562 status_head = devm_kzalloc(dev: &pdev->dev,
563 size: sizeof(*status_head), GFP_KERNEL);
564 if (!status_head)
565 return NULL;
566
567 /*
568 * Buffer for queue command
569 */
570 status_head->cq = dmam_alloc_coherent(dev: &pdev->dev,
571 size: sizeof(struct fsl_qdma_format) *
572 status_size,
573 dma_handle: &status_head->bus_addr,
574 GFP_KERNEL);
575 if (!status_head->cq)
576 return NULL;
577
578 status_head->n_cq = status_size;
579 status_head->virt_head = status_head->cq;
580 status_head->virt_tail = status_head->cq;
581 status_head->comp_pool = NULL;
582
583 return status_head;
584}
585
586static int fsl_qdma_halt(struct fsl_qdma_engine *fsl_qdma)
587{
588 u32 reg;
589 int i, j, count = FSL_QDMA_HALT_COUNT;
590 void __iomem *block, *ctrl = fsl_qdma->ctrl_base;
591
592 /* Disable the command queue and wait for idle state. */
593 reg = qdma_readl(qdma: fsl_qdma, addr: ctrl + FSL_QDMA_DMR);
594 reg |= FSL_QDMA_DMR_DQD;
595 qdma_writel(qdma: fsl_qdma, val: reg, addr: ctrl + FSL_QDMA_DMR);
596 for (j = 0; j < fsl_qdma->block_number; j++) {
597 block = fsl_qdma->block_base +
598 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);
599 for (i = 0; i < FSL_QDMA_QUEUE_NUM_MAX; i++)
600 qdma_writel(qdma: fsl_qdma, val: 0, addr: block + FSL_QDMA_BCQMR(i));
601 }
602 while (1) {
603 reg = qdma_readl(qdma: fsl_qdma, addr: ctrl + FSL_QDMA_DSR);
604 if (!(reg & FSL_QDMA_DSR_DB))
605 break;
606 if (count-- < 0)
607 return -EBUSY;
608 udelay(usec: 100);
609 }
610
611 for (j = 0; j < fsl_qdma->block_number; j++) {
612 block = fsl_qdma->block_base +
613 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);
614
615 /* Disable status queue. */
616 qdma_writel(qdma: fsl_qdma, val: 0, addr: block + FSL_QDMA_BSQMR);
617
618 /*
619 * clear the command queue interrupt detect register for
620 * all queues.
621 */
622 qdma_writel(qdma: fsl_qdma, FSL_QDMA_BCQIDR_CLEAR,
623 addr: block + FSL_QDMA_BCQIDR(0));
624 }
625
626 return 0;
627}
628
629static int
630fsl_qdma_queue_transfer_complete(struct fsl_qdma_engine *fsl_qdma,
631 __iomem void *block,
632 int id)
633{
634 bool duplicate;
635 u32 reg, i, count;
636 u8 completion_status;
637 struct fsl_qdma_queue *temp_queue;
638 struct fsl_qdma_format *status_addr;
639 struct fsl_qdma_comp *fsl_comp = NULL;
640 struct fsl_qdma_queue *fsl_queue = fsl_qdma->queue;
641 struct fsl_qdma_queue *fsl_status = fsl_qdma->status[id];
642
643 count = FSL_QDMA_MAX_SIZE;
644
645 while (count--) {
646 duplicate = 0;
647 reg = qdma_readl(qdma: fsl_qdma, addr: block + FSL_QDMA_BSQSR);
648 if (reg & FSL_QDMA_BSQSR_QE)
649 return 0;
650
651 status_addr = fsl_status->virt_head;
652
653 if (qdma_ccdf_get_queue(ccdf: status_addr) ==
654 __this_cpu_read(pre.queue) &&
655 qdma_ccdf_addr_get64(ccdf: status_addr) ==
656 __this_cpu_read(pre.addr))
657 duplicate = 1;
658 i = qdma_ccdf_get_queue(ccdf: status_addr) +
659 id * fsl_qdma->n_queues;
660 __this_cpu_write(pre.addr, qdma_ccdf_addr_get64(status_addr));
661 __this_cpu_write(pre.queue, qdma_ccdf_get_queue(status_addr));
662 temp_queue = fsl_queue + i;
663
664 spin_lock(lock: &temp_queue->queue_lock);
665 if (list_empty(head: &temp_queue->comp_used)) {
666 if (!duplicate) {
667 spin_unlock(lock: &temp_queue->queue_lock);
668 return -EAGAIN;
669 }
670 } else {
671 fsl_comp = list_first_entry(&temp_queue->comp_used,
672 struct fsl_qdma_comp, list);
673 if (fsl_comp->bus_addr + 16 !=
674 __this_cpu_read(pre.addr)) {
675 if (!duplicate) {
676 spin_unlock(lock: &temp_queue->queue_lock);
677 return -EAGAIN;
678 }
679 }
680 }
681
682 if (duplicate) {
683 reg = qdma_readl(qdma: fsl_qdma, addr: block + FSL_QDMA_BSQMR);
684 reg |= FSL_QDMA_BSQMR_DI;
685 qdma_desc_addr_set64(ccdf: status_addr, addr: 0x0);
686 fsl_status->virt_head++;
687 if (fsl_status->virt_head == fsl_status->cq
688 + fsl_status->n_cq)
689 fsl_status->virt_head = fsl_status->cq;
690 qdma_writel(qdma: fsl_qdma, val: reg, addr: block + FSL_QDMA_BSQMR);
691 spin_unlock(lock: &temp_queue->queue_lock);
692 continue;
693 }
694 list_del(entry: &fsl_comp->list);
695
696 completion_status = qdma_ccdf_get_status(ccdf: status_addr);
697
698 reg = qdma_readl(qdma: fsl_qdma, addr: block + FSL_QDMA_BSQMR);
699 reg |= FSL_QDMA_BSQMR_DI;
700 qdma_desc_addr_set64(ccdf: status_addr, addr: 0x0);
701 fsl_status->virt_head++;
702 if (fsl_status->virt_head == fsl_status->cq + fsl_status->n_cq)
703 fsl_status->virt_head = fsl_status->cq;
704 qdma_writel(qdma: fsl_qdma, val: reg, addr: block + FSL_QDMA_BSQMR);
705 spin_unlock(lock: &temp_queue->queue_lock);
706
707 /* The completion_status is evaluated here
708 * (outside of spin lock)
709 */
710 if (completion_status) {
711 /* A completion error occurred! */
712 if (completion_status & QDMA_CCDF_STATUS_WTE) {
713 /* Write transaction error */
714 fsl_comp->vdesc.tx_result.result =
715 DMA_TRANS_WRITE_FAILED;
716 } else if (completion_status & QDMA_CCDF_STATUS_RTE) {
717 /* Read transaction error */
718 fsl_comp->vdesc.tx_result.result =
719 DMA_TRANS_READ_FAILED;
720 } else {
721 /* Command/source/destination
722 * description error
723 */
724 fsl_comp->vdesc.tx_result.result =
725 DMA_TRANS_ABORTED;
726 dev_err(fsl_qdma->dma_dev.dev,
727 "DMA status descriptor error %x\n",
728 completion_status);
729 }
730 }
731
732 spin_lock(lock: &fsl_comp->qchan->vchan.lock);
733 vchan_cookie_complete(vd: &fsl_comp->vdesc);
734 fsl_comp->qchan->status = DMA_COMPLETE;
735 spin_unlock(lock: &fsl_comp->qchan->vchan.lock);
736 }
737
738 return 0;
739}
740
741static irqreturn_t fsl_qdma_error_handler(int irq, void *dev_id)
742{
743 unsigned int intr;
744 struct fsl_qdma_engine *fsl_qdma = dev_id;
745 void __iomem *status = fsl_qdma->status_base;
746 unsigned int decfdw0r;
747 unsigned int decfdw1r;
748 unsigned int decfdw2r;
749 unsigned int decfdw3r;
750
751 intr = qdma_readl(qdma: fsl_qdma, addr: status + FSL_QDMA_DEDR);
752
753 if (intr) {
754 decfdw0r = qdma_readl(qdma: fsl_qdma, addr: status + FSL_QDMA_DECFDW0R);
755 decfdw1r = qdma_readl(qdma: fsl_qdma, addr: status + FSL_QDMA_DECFDW1R);
756 decfdw2r = qdma_readl(qdma: fsl_qdma, addr: status + FSL_QDMA_DECFDW2R);
757 decfdw3r = qdma_readl(qdma: fsl_qdma, addr: status + FSL_QDMA_DECFDW3R);
758 dev_err(fsl_qdma->dma_dev.dev,
759 "DMA transaction error! (%x: %x-%x-%x-%x)\n",
760 intr, decfdw0r, decfdw1r, decfdw2r, decfdw3r);
761 }
762
763 qdma_writel(qdma: fsl_qdma, FSL_QDMA_DEDR_CLEAR, addr: status + FSL_QDMA_DEDR);
764 return IRQ_HANDLED;
765}
766
767static irqreturn_t fsl_qdma_queue_handler(int irq, void *dev_id)
768{
769 int id;
770 unsigned int intr, reg;
771 struct fsl_qdma_engine *fsl_qdma = dev_id;
772 void __iomem *block, *ctrl = fsl_qdma->ctrl_base;
773
774 id = irq - fsl_qdma->irq_base;
775 if (id < 0 && id > fsl_qdma->block_number) {
776 dev_err(fsl_qdma->dma_dev.dev,
777 "irq %d is wrong irq_base is %d\n",
778 irq, fsl_qdma->irq_base);
779 }
780
781 block = fsl_qdma->block_base +
782 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, id);
783
784 intr = qdma_readl(qdma: fsl_qdma, addr: block + FSL_QDMA_BCQIDR(0));
785
786 if ((intr & FSL_QDMA_CQIDR_SQT) != 0)
787 intr = fsl_qdma_queue_transfer_complete(fsl_qdma, block, id);
788
789 if (intr != 0) {
790 reg = qdma_readl(qdma: fsl_qdma, addr: ctrl + FSL_QDMA_DMR);
791 reg |= FSL_QDMA_DMR_DQD;
792 qdma_writel(qdma: fsl_qdma, val: reg, addr: ctrl + FSL_QDMA_DMR);
793 qdma_writel(qdma: fsl_qdma, val: 0, addr: block + FSL_QDMA_BCQIER(0));
794 dev_err(fsl_qdma->dma_dev.dev, "QDMA: status err!\n");
795 }
796
797 /* Clear all detected events and interrupts. */
798 qdma_writel(qdma: fsl_qdma, FSL_QDMA_BCQIDR_CLEAR,
799 addr: block + FSL_QDMA_BCQIDR(0));
800
801 return IRQ_HANDLED;
802}
803
804static int
805fsl_qdma_irq_init(struct platform_device *pdev,
806 struct fsl_qdma_engine *fsl_qdma)
807{
808 int i;
809 int cpu;
810 int ret;
811 char irq_name[32];
812
813 fsl_qdma->error_irq =
814 platform_get_irq_byname(pdev, "qdma-error");
815 if (fsl_qdma->error_irq < 0)
816 return fsl_qdma->error_irq;
817
818 ret = devm_request_irq(dev: &pdev->dev, irq: fsl_qdma->error_irq,
819 handler: fsl_qdma_error_handler, irqflags: 0,
820 devname: "qDMA error", dev_id: fsl_qdma);
821 if (ret) {
822 dev_err(&pdev->dev, "Can't register qDMA controller IRQ.\n");
823 return ret;
824 }
825
826 for (i = 0; i < fsl_qdma->block_number; i++) {
827 sprintf(buf: irq_name, fmt: "qdma-queue%d", i);
828 fsl_qdma->queue_irq[i] =
829 platform_get_irq_byname(pdev, irq_name);
830
831 if (fsl_qdma->queue_irq[i] < 0)
832 return fsl_qdma->queue_irq[i];
833
834 ret = devm_request_irq(dev: &pdev->dev,
835 irq: fsl_qdma->queue_irq[i],
836 handler: fsl_qdma_queue_handler,
837 irqflags: 0,
838 devname: "qDMA queue",
839 dev_id: fsl_qdma);
840 if (ret) {
841 dev_err(&pdev->dev,
842 "Can't register qDMA queue IRQ.\n");
843 return ret;
844 }
845
846 cpu = i % num_online_cpus();
847 ret = irq_set_affinity_hint(irq: fsl_qdma->queue_irq[i],
848 m: get_cpu_mask(cpu));
849 if (ret) {
850 dev_err(&pdev->dev,
851 "Can't set cpu %d affinity to IRQ %d.\n",
852 cpu,
853 fsl_qdma->queue_irq[i]);
854 return ret;
855 }
856 }
857
858 return 0;
859}
860
861static void fsl_qdma_irq_exit(struct platform_device *pdev,
862 struct fsl_qdma_engine *fsl_qdma)
863{
864 int i;
865
866 devm_free_irq(dev: &pdev->dev, irq: fsl_qdma->error_irq, dev_id: fsl_qdma);
867 for (i = 0; i < fsl_qdma->block_number; i++)
868 devm_free_irq(dev: &pdev->dev, irq: fsl_qdma->queue_irq[i], dev_id: fsl_qdma);
869}
870
871static int fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma)
872{
873 u32 reg;
874 int i, j, ret;
875 struct fsl_qdma_queue *temp;
876 void __iomem *status = fsl_qdma->status_base;
877 void __iomem *block, *ctrl = fsl_qdma->ctrl_base;
878 struct fsl_qdma_queue *fsl_queue = fsl_qdma->queue;
879
880 /* Try to halt the qDMA engine first. */
881 ret = fsl_qdma_halt(fsl_qdma);
882 if (ret) {
883 dev_err(fsl_qdma->dma_dev.dev, "DMA halt failed!");
884 return ret;
885 }
886
887 for (i = 0; i < fsl_qdma->block_number; i++) {
888 /*
889 * Clear the command queue interrupt detect register for
890 * all queues.
891 */
892
893 block = fsl_qdma->block_base +
894 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, i);
895 qdma_writel(qdma: fsl_qdma, FSL_QDMA_BCQIDR_CLEAR,
896 addr: block + FSL_QDMA_BCQIDR(0));
897 }
898
899 for (j = 0; j < fsl_qdma->block_number; j++) {
900 block = fsl_qdma->block_base +
901 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);
902 for (i = 0; i < fsl_qdma->n_queues; i++) {
903 temp = fsl_queue + i + (j * fsl_qdma->n_queues);
904 /*
905 * Initialize Command Queue registers to
906 * point to the first
907 * command descriptor in memory.
908 * Dequeue Pointer Address Registers
909 * Enqueue Pointer Address Registers
910 */
911
912 qdma_writel(qdma: fsl_qdma, val: temp->bus_addr,
913 addr: block + FSL_QDMA_BCQDPA_SADDR(i));
914 qdma_writel(qdma: fsl_qdma, val: temp->bus_addr,
915 addr: block + FSL_QDMA_BCQEPA_SADDR(i));
916
917 /* Initialize the queue mode. */
918 reg = FSL_QDMA_BCQMR_EN;
919 reg |= FSL_QDMA_BCQMR_CD_THLD(ilog2(temp->n_cq) - 4);
920 reg |= FSL_QDMA_BCQMR_CQ_SIZE(ilog2(temp->n_cq) - 6);
921 qdma_writel(qdma: fsl_qdma, val: reg, addr: block + FSL_QDMA_BCQMR(i));
922 }
923
924 /*
925 * Workaround for erratum: ERR010812.
926 * We must enable XOFF to avoid the enqueue rejection occurs.
927 * Setting SQCCMR ENTER_WM to 0x20.
928 */
929
930 qdma_writel(qdma: fsl_qdma, FSL_QDMA_SQCCMR_ENTER_WM,
931 addr: block + FSL_QDMA_SQCCMR);
932
933 /*
934 * Initialize status queue registers to point to the first
935 * command descriptor in memory.
936 * Dequeue Pointer Address Registers
937 * Enqueue Pointer Address Registers
938 */
939
940 qdma_writel(qdma: fsl_qdma, val: fsl_qdma->status[j]->bus_addr,
941 addr: block + FSL_QDMA_SQEPAR);
942 qdma_writel(qdma: fsl_qdma, val: fsl_qdma->status[j]->bus_addr,
943 addr: block + FSL_QDMA_SQDPAR);
944 /* Initialize status queue interrupt. */
945 qdma_writel(qdma: fsl_qdma, FSL_QDMA_BCQIER_CQTIE,
946 addr: block + FSL_QDMA_BCQIER(0));
947 qdma_writel(qdma: fsl_qdma, FSL_QDMA_BSQICR_ICEN |
948 FSL_QDMA_BSQICR_ICST(5) | 0x8000,
949 addr: block + FSL_QDMA_BSQICR);
950 qdma_writel(qdma: fsl_qdma, FSL_QDMA_CQIER_MEIE |
951 FSL_QDMA_CQIER_TEIE,
952 addr: block + FSL_QDMA_CQIER);
953
954 /* Initialize the status queue mode. */
955 reg = FSL_QDMA_BSQMR_EN;
956 reg |= FSL_QDMA_BSQMR_CQ_SIZE(ilog2
957 (fsl_qdma->status[j]->n_cq) - 6);
958
959 qdma_writel(qdma: fsl_qdma, val: reg, addr: block + FSL_QDMA_BSQMR);
960 reg = qdma_readl(qdma: fsl_qdma, addr: block + FSL_QDMA_BSQMR);
961 }
962
963 /* Initialize controller interrupt register. */
964 qdma_writel(qdma: fsl_qdma, FSL_QDMA_DEDR_CLEAR, addr: status + FSL_QDMA_DEDR);
965 qdma_writel(qdma: fsl_qdma, FSL_QDMA_DEIER_CLEAR, addr: status + FSL_QDMA_DEIER);
966
967 reg = qdma_readl(qdma: fsl_qdma, addr: ctrl + FSL_QDMA_DMR);
968 reg &= ~FSL_QDMA_DMR_DQD;
969 qdma_writel(qdma: fsl_qdma, val: reg, addr: ctrl + FSL_QDMA_DMR);
970
971 return 0;
972}
973
974static struct dma_async_tx_descriptor *
975fsl_qdma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst,
976 dma_addr_t src, size_t len, unsigned long flags)
977{
978 struct fsl_qdma_comp *fsl_comp;
979 struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
980
981 fsl_comp = fsl_qdma_request_enqueue_desc(fsl_chan);
982
983 if (!fsl_comp)
984 return NULL;
985
986 fsl_qdma_comp_fill_memcpy(fsl_comp, dst, src, len);
987
988 return vchan_tx_prep(vc: &fsl_chan->vchan, vd: &fsl_comp->vdesc, tx_flags: flags);
989}
990
991static void fsl_qdma_enqueue_desc(struct fsl_qdma_chan *fsl_chan)
992{
993 u32 reg;
994 struct virt_dma_desc *vdesc;
995 struct fsl_qdma_comp *fsl_comp;
996 struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
997 void __iomem *block = fsl_queue->block_base;
998
999 reg = qdma_readl(qdma: fsl_chan->qdma, addr: block + FSL_QDMA_BCQSR(fsl_queue->id));
1000 if (reg & (FSL_QDMA_BCQSR_QF | FSL_QDMA_BCQSR_XOFF))
1001 return;
1002 vdesc = vchan_next_desc(vc: &fsl_chan->vchan);
1003 if (!vdesc)
1004 return;
1005 list_del(entry: &vdesc->node);
1006 fsl_comp = to_fsl_qdma_comp(vd: vdesc);
1007
1008 memcpy(fsl_queue->virt_head++,
1009 fsl_comp->virt_addr, sizeof(struct fsl_qdma_format));
1010 if (fsl_queue->virt_head == fsl_queue->cq + fsl_queue->n_cq)
1011 fsl_queue->virt_head = fsl_queue->cq;
1012
1013 list_add_tail(new: &fsl_comp->list, head: &fsl_queue->comp_used);
1014 barrier();
1015 reg = qdma_readl(qdma: fsl_chan->qdma, addr: block + FSL_QDMA_BCQMR(fsl_queue->id));
1016 reg |= FSL_QDMA_BCQMR_EI;
1017 qdma_writel(qdma: fsl_chan->qdma, val: reg, addr: block + FSL_QDMA_BCQMR(fsl_queue->id));
1018 fsl_chan->status = DMA_IN_PROGRESS;
1019}
1020
1021static void fsl_qdma_free_desc(struct virt_dma_desc *vdesc)
1022{
1023 unsigned long flags;
1024 struct fsl_qdma_comp *fsl_comp;
1025 struct fsl_qdma_queue *fsl_queue;
1026
1027 fsl_comp = to_fsl_qdma_comp(vd: vdesc);
1028 fsl_queue = fsl_comp->qchan->queue;
1029
1030 spin_lock_irqsave(&fsl_queue->queue_lock, flags);
1031 list_add_tail(new: &fsl_comp->list, head: &fsl_queue->comp_free);
1032 spin_unlock_irqrestore(lock: &fsl_queue->queue_lock, flags);
1033}
1034
1035static void fsl_qdma_issue_pending(struct dma_chan *chan)
1036{
1037 unsigned long flags;
1038 struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
1039 struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
1040
1041 spin_lock_irqsave(&fsl_queue->queue_lock, flags);
1042 spin_lock(lock: &fsl_chan->vchan.lock);
1043 if (vchan_issue_pending(vc: &fsl_chan->vchan))
1044 fsl_qdma_enqueue_desc(fsl_chan);
1045 spin_unlock(lock: &fsl_chan->vchan.lock);
1046 spin_unlock_irqrestore(lock: &fsl_queue->queue_lock, flags);
1047}
1048
1049static void fsl_qdma_synchronize(struct dma_chan *chan)
1050{
1051 struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
1052
1053 vchan_synchronize(vc: &fsl_chan->vchan);
1054}
1055
1056static int fsl_qdma_terminate_all(struct dma_chan *chan)
1057{
1058 LIST_HEAD(head);
1059 unsigned long flags;
1060 struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
1061
1062 spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
1063 vchan_get_all_descriptors(vc: &fsl_chan->vchan, head: &head);
1064 spin_unlock_irqrestore(lock: &fsl_chan->vchan.lock, flags);
1065 vchan_dma_desc_free_list(vc: &fsl_chan->vchan, head: &head);
1066 return 0;
1067}
1068
1069static int fsl_qdma_alloc_chan_resources(struct dma_chan *chan)
1070{
1071 int ret;
1072 struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
1073 struct fsl_qdma_engine *fsl_qdma = fsl_chan->qdma;
1074 struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
1075
1076 if (fsl_queue->comp_pool && fsl_queue->desc_pool)
1077 return fsl_qdma->desc_allocated;
1078
1079 INIT_LIST_HEAD(list: &fsl_queue->comp_free);
1080
1081 /*
1082 * The dma pool for queue command buffer
1083 */
1084 fsl_queue->comp_pool =
1085 dma_pool_create(name: "comp_pool",
1086 dev: chan->device->dev,
1087 FSL_QDMA_COMMAND_BUFFER_SIZE,
1088 align: 64, boundary: 0);
1089 if (!fsl_queue->comp_pool)
1090 return -ENOMEM;
1091
1092 /*
1093 * The dma pool for Descriptor(SD/DD) buffer
1094 */
1095 fsl_queue->desc_pool =
1096 dma_pool_create(name: "desc_pool",
1097 dev: chan->device->dev,
1098 FSL_QDMA_DESCRIPTOR_BUFFER_SIZE,
1099 align: 32, boundary: 0);
1100 if (!fsl_queue->desc_pool)
1101 goto err_desc_pool;
1102
1103 ret = fsl_qdma_pre_request_enqueue_desc(queue: fsl_queue);
1104 if (ret) {
1105 dev_err(chan->device->dev,
1106 "failed to alloc dma buffer for S/G descriptor\n");
1107 goto err_mem;
1108 }
1109
1110 fsl_qdma->desc_allocated++;
1111 return fsl_qdma->desc_allocated;
1112
1113err_mem:
1114 dma_pool_destroy(pool: fsl_queue->desc_pool);
1115err_desc_pool:
1116 dma_pool_destroy(pool: fsl_queue->comp_pool);
1117 return -ENOMEM;
1118}
1119
1120static int fsl_qdma_probe(struct platform_device *pdev)
1121{
1122 int ret, i;
1123 int blk_num, blk_off;
1124 u32 len, chans, queues;
1125 struct fsl_qdma_chan *fsl_chan;
1126 struct fsl_qdma_engine *fsl_qdma;
1127 struct device_node *np = pdev->dev.of_node;
1128
1129 ret = of_property_read_u32(np, propname: "dma-channels", out_value: &chans);
1130 if (ret) {
1131 dev_err(&pdev->dev, "Can't get dma-channels.\n");
1132 return ret;
1133 }
1134
1135 ret = of_property_read_u32(np, propname: "block-offset", out_value: &blk_off);
1136 if (ret) {
1137 dev_err(&pdev->dev, "Can't get block-offset.\n");
1138 return ret;
1139 }
1140
1141 ret = of_property_read_u32(np, propname: "block-number", out_value: &blk_num);
1142 if (ret) {
1143 dev_err(&pdev->dev, "Can't get block-number.\n");
1144 return ret;
1145 }
1146
1147 blk_num = min_t(int, blk_num, num_online_cpus());
1148
1149 len = sizeof(*fsl_qdma);
1150 fsl_qdma = devm_kzalloc(dev: &pdev->dev, size: len, GFP_KERNEL);
1151 if (!fsl_qdma)
1152 return -ENOMEM;
1153
1154 len = sizeof(*fsl_chan) * chans;
1155 fsl_qdma->chans = devm_kzalloc(dev: &pdev->dev, size: len, GFP_KERNEL);
1156 if (!fsl_qdma->chans)
1157 return -ENOMEM;
1158
1159 len = sizeof(struct fsl_qdma_queue *) * blk_num;
1160 fsl_qdma->status = devm_kzalloc(dev: &pdev->dev, size: len, GFP_KERNEL);
1161 if (!fsl_qdma->status)
1162 return -ENOMEM;
1163
1164 len = sizeof(int) * blk_num;
1165 fsl_qdma->queue_irq = devm_kzalloc(dev: &pdev->dev, size: len, GFP_KERNEL);
1166 if (!fsl_qdma->queue_irq)
1167 return -ENOMEM;
1168
1169 ret = of_property_read_u32(np, propname: "fsl,dma-queues", out_value: &queues);
1170 if (ret) {
1171 dev_err(&pdev->dev, "Can't get queues.\n");
1172 return ret;
1173 }
1174
1175 fsl_qdma->desc_allocated = 0;
1176 fsl_qdma->n_chans = chans;
1177 fsl_qdma->n_queues = queues;
1178 fsl_qdma->block_number = blk_num;
1179 fsl_qdma->block_offset = blk_off;
1180
1181 mutex_init(&fsl_qdma->fsl_qdma_mutex);
1182
1183 for (i = 0; i < fsl_qdma->block_number; i++) {
1184 fsl_qdma->status[i] = fsl_qdma_prep_status_queue(pdev);
1185 if (!fsl_qdma->status[i])
1186 return -ENOMEM;
1187 }
1188 fsl_qdma->ctrl_base = devm_platform_ioremap_resource(pdev, index: 0);
1189 if (IS_ERR(ptr: fsl_qdma->ctrl_base))
1190 return PTR_ERR(ptr: fsl_qdma->ctrl_base);
1191
1192 fsl_qdma->status_base = devm_platform_ioremap_resource(pdev, index: 1);
1193 if (IS_ERR(ptr: fsl_qdma->status_base))
1194 return PTR_ERR(ptr: fsl_qdma->status_base);
1195
1196 fsl_qdma->block_base = devm_platform_ioremap_resource(pdev, index: 2);
1197 if (IS_ERR(ptr: fsl_qdma->block_base))
1198 return PTR_ERR(ptr: fsl_qdma->block_base);
1199 fsl_qdma->queue = fsl_qdma_alloc_queue_resources(pdev, fsl_qdma);
1200 if (!fsl_qdma->queue)
1201 return -ENOMEM;
1202
1203 fsl_qdma->irq_base = platform_get_irq_byname(pdev, "qdma-queue0");
1204 if (fsl_qdma->irq_base < 0)
1205 return fsl_qdma->irq_base;
1206
1207 fsl_qdma->feature = of_property_read_bool(np, propname: "big-endian");
1208 INIT_LIST_HEAD(list: &fsl_qdma->dma_dev.channels);
1209
1210 for (i = 0; i < fsl_qdma->n_chans; i++) {
1211 struct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[i];
1212
1213 fsl_chan->qdma = fsl_qdma;
1214 fsl_chan->queue = fsl_qdma->queue + i % (fsl_qdma->n_queues *
1215 fsl_qdma->block_number);
1216 fsl_chan->vchan.desc_free = fsl_qdma_free_desc;
1217 vchan_init(vc: &fsl_chan->vchan, dmadev: &fsl_qdma->dma_dev);
1218 }
1219
1220 dma_cap_set(DMA_MEMCPY, fsl_qdma->dma_dev.cap_mask);
1221
1222 fsl_qdma->dma_dev.dev = &pdev->dev;
1223 fsl_qdma->dma_dev.device_free_chan_resources =
1224 fsl_qdma_free_chan_resources;
1225 fsl_qdma->dma_dev.device_alloc_chan_resources =
1226 fsl_qdma_alloc_chan_resources;
1227 fsl_qdma->dma_dev.device_tx_status = dma_cookie_status;
1228 fsl_qdma->dma_dev.device_prep_dma_memcpy = fsl_qdma_prep_memcpy;
1229 fsl_qdma->dma_dev.device_issue_pending = fsl_qdma_issue_pending;
1230 fsl_qdma->dma_dev.device_synchronize = fsl_qdma_synchronize;
1231 fsl_qdma->dma_dev.device_terminate_all = fsl_qdma_terminate_all;
1232
1233 ret = dma_set_mask(dev: &pdev->dev, DMA_BIT_MASK(40));
1234 if (ret) {
1235 dev_err(&pdev->dev, "dma_set_mask failure.\n");
1236 return ret;
1237 }
1238
1239 platform_set_drvdata(pdev, data: fsl_qdma);
1240
1241 ret = fsl_qdma_reg_init(fsl_qdma);
1242 if (ret) {
1243 dev_err(&pdev->dev, "Can't Initialize the qDMA engine.\n");
1244 return ret;
1245 }
1246
1247 ret = fsl_qdma_irq_init(pdev, fsl_qdma);
1248 if (ret)
1249 return ret;
1250
1251 ret = dma_async_device_register(device: &fsl_qdma->dma_dev);
1252 if (ret) {
1253 dev_err(&pdev->dev, "Can't register NXP Layerscape qDMA engine.\n");
1254 return ret;
1255 }
1256
1257 return 0;
1258}
1259
1260static void fsl_qdma_cleanup_vchan(struct dma_device *dmadev)
1261{
1262 struct fsl_qdma_chan *chan, *_chan;
1263
1264 list_for_each_entry_safe(chan, _chan,
1265 &dmadev->channels, vchan.chan.device_node) {
1266 list_del(entry: &chan->vchan.chan.device_node);
1267 tasklet_kill(t: &chan->vchan.task);
1268 }
1269}
1270
1271static void fsl_qdma_remove(struct platform_device *pdev)
1272{
1273 struct device_node *np = pdev->dev.of_node;
1274 struct fsl_qdma_engine *fsl_qdma = platform_get_drvdata(pdev);
1275
1276 fsl_qdma_irq_exit(pdev, fsl_qdma);
1277 fsl_qdma_cleanup_vchan(dmadev: &fsl_qdma->dma_dev);
1278 of_dma_controller_free(np);
1279 dma_async_device_unregister(device: &fsl_qdma->dma_dev);
1280}
1281
1282static const struct of_device_id fsl_qdma_dt_ids[] = {
1283 { .compatible = "fsl,ls1021a-qdma", },
1284 { /* sentinel */ }
1285};
1286MODULE_DEVICE_TABLE(of, fsl_qdma_dt_ids);
1287
1288static struct platform_driver fsl_qdma_driver = {
1289 .driver = {
1290 .name = "fsl-qdma",
1291 .of_match_table = fsl_qdma_dt_ids,
1292 },
1293 .probe = fsl_qdma_probe,
1294 .remove = fsl_qdma_remove,
1295};
1296
1297module_platform_driver(fsl_qdma_driver);
1298
1299MODULE_LICENSE("GPL v2");
1300MODULE_DESCRIPTION("NXP Layerscape qDMA engine driver");
1301

source code of linux/drivers/dma/fsl-qdma.c