| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright(c) 2023 Huawei |
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| 4 | * CXL Specification rev 3.0 Setion 8.2.7 (CPMU Register Interface) |
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| 5 | */ |
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| 6 | #ifndef CXL_PMU_H |
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| 7 | #define CXL_PMU_H |
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| 8 | #include <linux/device.h> |
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| 9 | |
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| 10 | enum cxl_pmu_type { |
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| 11 | CXL_PMU_MEMDEV, |
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| 12 | }; |
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| 13 | |
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| 14 | #define CXL_PMU_REGMAP_SIZE 0xe00 /* Table 8-32 CXL 3.0 specification */ |
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| 15 | struct cxl_pmu { |
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| 16 | struct device dev; |
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| 17 | void __iomem *base; |
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| 18 | int assoc_id; |
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| 19 | int index; |
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| 20 | enum cxl_pmu_type type; |
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| 21 | }; |
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| 22 | |
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| 23 | #define to_cxl_pmu(dev) container_of(dev, struct cxl_pmu, dev) |
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| 24 | struct cxl_pmu_regs; |
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| 25 | int devm_cxl_pmu_add(struct device *parent, struct cxl_pmu_regs *regs, |
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| 26 | int assoc_id, int idx, enum cxl_pmu_type type); |
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| 27 | |
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| 28 | #endif |
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| 29 | |
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