1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright(c) 2020 Intel Corporation. All rights reserved. */
3#ifndef __CXL_PCI_H__
4#define __CXL_PCI_H__
5#include <linux/pci.h>
6#include "cxl.h"
7
8#define CXL_MEMORY_PROGIF 0x10
9
10/*
11 * See section 8.1 Configuration Space Registers in the CXL 2.0
12 * Specification. Names are taken straight from the specification with "CXL" and
13 * "DVSEC" redundancies removed. When obvious, abbreviations may be used.
14 */
15#define PCI_DVSEC_HEADER1_LENGTH_MASK GENMASK(31, 20)
16
17/* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */
18#define CXL_DVSEC_PCIE_DEVICE 0
19#define CXL_DVSEC_CAP_OFFSET 0xA
20#define CXL_DVSEC_MEM_CAPABLE BIT(2)
21#define CXL_DVSEC_HDM_COUNT_MASK GENMASK(5, 4)
22#define CXL_DVSEC_CTRL_OFFSET 0xC
23#define CXL_DVSEC_MEM_ENABLE BIT(2)
24#define CXL_DVSEC_RANGE_SIZE_HIGH(i) (0x18 + (i * 0x10))
25#define CXL_DVSEC_RANGE_SIZE_LOW(i) (0x1C + (i * 0x10))
26#define CXL_DVSEC_MEM_INFO_VALID BIT(0)
27#define CXL_DVSEC_MEM_ACTIVE BIT(1)
28#define CXL_DVSEC_MEM_SIZE_LOW_MASK GENMASK(31, 28)
29#define CXL_DVSEC_RANGE_BASE_HIGH(i) (0x20 + (i * 0x10))
30#define CXL_DVSEC_RANGE_BASE_LOW(i) (0x24 + (i * 0x10))
31#define CXL_DVSEC_MEM_BASE_LOW_MASK GENMASK(31, 28)
32
33#define CXL_DVSEC_RANGE_MAX 2
34
35/* CXL 2.0 8.1.4: Non-CXL Function Map DVSEC */
36#define CXL_DVSEC_FUNCTION_MAP 2
37
38/* CXL 2.0 8.1.5: CXL 2.0 Extensions DVSEC for Ports */
39#define CXL_DVSEC_PORT_EXTENSIONS 3
40
41/* CXL 2.0 8.1.6: GPF DVSEC for CXL Port */
42#define CXL_DVSEC_PORT_GPF 4
43#define CXL_DVSEC_PORT_GPF_PHASE_1_CONTROL_OFFSET 0x0C
44#define CXL_DVSEC_PORT_GPF_PHASE_1_TMO_BASE_MASK GENMASK(3, 0)
45#define CXL_DVSEC_PORT_GPF_PHASE_1_TMO_SCALE_MASK GENMASK(11, 8)
46#define CXL_DVSEC_PORT_GPF_PHASE_2_CONTROL_OFFSET 0xE
47#define CXL_DVSEC_PORT_GPF_PHASE_2_TMO_BASE_MASK GENMASK(3, 0)
48#define CXL_DVSEC_PORT_GPF_PHASE_2_TMO_SCALE_MASK GENMASK(11, 8)
49
50/* CXL 2.0 8.1.7: GPF DVSEC for CXL Device */
51#define CXL_DVSEC_DEVICE_GPF 5
52
53/* CXL 2.0 8.1.8: PCIe DVSEC for Flex Bus Port */
54#define CXL_DVSEC_PCIE_FLEXBUS_PORT 7
55
56/* CXL 2.0 8.1.9: Register Locator DVSEC */
57#define CXL_DVSEC_REG_LOCATOR 8
58#define CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET 0xC
59#define CXL_DVSEC_REG_LOCATOR_BIR_MASK GENMASK(2, 0)
60#define CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK GENMASK(15, 8)
61#define CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK GENMASK(31, 16)
62
63/*
64 * NOTE: Currently all the functions which are enabled for CXL require their
65 * vectors to be in the first 16. Use this as the default max.
66 */
67#define CXL_PCI_DEFAULT_MAX_VECTORS 16
68
69/* Register Block Identifier (RBI) */
70enum cxl_regloc_type {
71 CXL_REGLOC_RBI_EMPTY = 0,
72 CXL_REGLOC_RBI_COMPONENT,
73 CXL_REGLOC_RBI_VIRT,
74 CXL_REGLOC_RBI_MEMDEV,
75 CXL_REGLOC_RBI_PMU,
76 CXL_REGLOC_RBI_TYPES
77};
78
79/*
80 * Table Access DOE, CDAT Read Entry Response
81 *
82 * Spec refs:
83 *
84 * CXL 3.1 8.1.11, Table 8-14: Read Entry Response
85 * CDAT Specification 1.03: 2 CDAT Data Structures
86 */
87
88struct cdat_header {
89 __le32 length;
90 u8 revision;
91 u8 checksum;
92 u8 reserved[6];
93 __le32 sequence;
94} __packed;
95
96struct cdat_entry_header {
97 u8 type;
98 u8 reserved;
99 __le16 length;
100} __packed;
101
102/*
103 * The DOE CDAT read response contains a CDAT read entry (either the
104 * CDAT header or a structure).
105 */
106union cdat_data {
107 struct cdat_header header;
108 struct cdat_entry_header entry;
109} __packed;
110
111/* There is an additional CDAT response header of 4 bytes. */
112struct cdat_doe_rsp {
113 __le32 doe_header;
114 u8 data[];
115} __packed;
116
117/*
118 * CXL v3.0 6.2.3 Table 6-4
119 * The table indicates that if PCIe Flit Mode is set, then CXL is in 256B flits
120 * mode, otherwise it's 68B flits mode.
121 */
122static inline bool cxl_pci_flit_256(struct pci_dev *pdev)
123{
124 u16 lnksta2;
125
126 pcie_capability_read_word(dev: pdev, PCI_EXP_LNKSTA2, val: &lnksta2);
127 return lnksta2 & PCI_EXP_LNKSTA2_FLIT;
128}
129
130struct cxl_dev_state;
131void read_cdat_data(struct cxl_port *port);
132void cxl_cor_error_detected(struct pci_dev *pdev);
133pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
134 pci_channel_state_t state);
135#endif /* __CXL_PCI_H__ */
136

source code of linux/drivers/cxl/cxlpci.h