1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (c) 2019 HiSilicon Limited. */
3#include <asm/page.h>
4#include <linux/acpi.h>
5#include <linux/bitmap.h>
6#include <linux/dma-mapping.h>
7#include <linux/idr.h>
8#include <linux/io.h>
9#include <linux/irqreturn.h>
10#include <linux/log2.h>
11#include <linux/pm_runtime.h>
12#include <linux/seq_file.h>
13#include <linux/slab.h>
14#include <linux/uacce.h>
15#include <linux/uaccess.h>
16#include <uapi/misc/uacce/hisi_qm.h>
17#include <linux/hisi_acc_qm.h>
18#include "qm_common.h"
19
20/* eq/aeq irq enable */
21#define QM_VF_AEQ_INT_SOURCE 0x0
22#define QM_VF_AEQ_INT_MASK 0x4
23#define QM_VF_EQ_INT_SOURCE 0x8
24#define QM_VF_EQ_INT_MASK 0xc
25
26#define QM_IRQ_VECTOR_MASK GENMASK(15, 0)
27#define QM_IRQ_TYPE_MASK GENMASK(15, 0)
28#define QM_IRQ_TYPE_SHIFT 16
29#define QM_ABN_IRQ_TYPE_MASK GENMASK(7, 0)
30
31/* mailbox */
32#define QM_MB_PING_ALL_VFS 0xffff
33#define QM_MB_STATUS_MASK GENMASK(12, 9)
34
35/* sqc shift */
36#define QM_SQ_HOP_NUM_SHIFT 0
37#define QM_SQ_PAGE_SIZE_SHIFT 4
38#define QM_SQ_BUF_SIZE_SHIFT 8
39#define QM_SQ_SQE_SIZE_SHIFT 12
40#define QM_SQ_PRIORITY_SHIFT 0
41#define QM_SQ_ORDERS_SHIFT 4
42#define QM_SQ_TYPE_SHIFT 8
43#define QM_QC_PASID_ENABLE 0x1
44#define QM_QC_PASID_ENABLE_SHIFT 7
45
46#define QM_SQ_TYPE_MASK GENMASK(3, 0)
47#define QM_SQ_TAIL_IDX(sqc) ((le16_to_cpu((sqc).w11) >> 6) & 0x1)
48#define QM_SQC_DISABLE_QP (1U << 6)
49#define QM_XQC_RANDOM_DATA 0xaaaa
50
51/* cqc shift */
52#define QM_CQ_HOP_NUM_SHIFT 0
53#define QM_CQ_PAGE_SIZE_SHIFT 4
54#define QM_CQ_BUF_SIZE_SHIFT 8
55#define QM_CQ_CQE_SIZE_SHIFT 12
56#define QM_CQ_PHASE_SHIFT 0
57#define QM_CQ_FLAG_SHIFT 1
58
59#define QM_CQE_PHASE(cqe) (le16_to_cpu((cqe)->w7) & 0x1)
60#define QM_QC_CQE_SIZE 4
61#define QM_CQ_TAIL_IDX(cqc) ((le16_to_cpu((cqc).w11) >> 6) & 0x1)
62
63/* eqc shift */
64#define QM_EQE_AEQE_SIZE (2UL << 12)
65#define QM_EQC_PHASE_SHIFT 16
66
67#define QM_EQE_PHASE(dw0) (((dw0) >> 16) & 0x1)
68#define QM_EQE_CQN_MASK GENMASK(15, 0)
69
70#define QM_AEQE_PHASE(dw0) (((dw0) >> 16) & 0x1)
71#define QM_AEQE_TYPE_SHIFT 17
72#define QM_AEQE_TYPE_MASK 0xf
73#define QM_AEQE_CQN_MASK GENMASK(15, 0)
74#define QM_CQ_OVERFLOW 0
75#define QM_EQ_OVERFLOW 1
76#define QM_CQE_ERROR 2
77
78#define QM_XQ_DEPTH_SHIFT 16
79#define QM_XQ_DEPTH_MASK GENMASK(15, 0)
80
81#define QM_DOORBELL_CMD_SQ 0
82#define QM_DOORBELL_CMD_CQ 1
83#define QM_DOORBELL_CMD_EQ 2
84#define QM_DOORBELL_CMD_AEQ 3
85
86#define QM_DOORBELL_BASE_V1 0x340
87#define QM_DB_CMD_SHIFT_V1 16
88#define QM_DB_INDEX_SHIFT_V1 32
89#define QM_DB_PRIORITY_SHIFT_V1 48
90#define QM_PAGE_SIZE 0x0034
91#define QM_QP_DB_INTERVAL 0x10000
92#define QM_DB_TIMEOUT_CFG 0x100074
93#define QM_DB_TIMEOUT_SET 0x1fffff
94
95#define QM_MEM_START_INIT 0x100040
96#define QM_MEM_INIT_DONE 0x100044
97#define QM_VFT_CFG_RDY 0x10006c
98#define QM_VFT_CFG_OP_WR 0x100058
99#define QM_VFT_CFG_TYPE 0x10005c
100#define QM_VFT_CFG 0x100060
101#define QM_VFT_CFG_OP_ENABLE 0x100054
102#define QM_PM_CTRL 0x100148
103#define QM_IDLE_DISABLE BIT(9)
104
105#define QM_SUB_VERSION_ID 0x210
106
107#define QM_VFT_CFG_DATA_L 0x100064
108#define QM_VFT_CFG_DATA_H 0x100068
109#define QM_SQC_VFT_BUF_SIZE (7ULL << 8)
110#define QM_SQC_VFT_SQC_SIZE (5ULL << 12)
111#define QM_SQC_VFT_INDEX_NUMBER (1ULL << 16)
112#define QM_SQC_VFT_START_SQN_SHIFT 28
113#define QM_SQC_VFT_VALID (1ULL << 44)
114#define QM_SQC_VFT_SQN_SHIFT 45
115#define QM_CQC_VFT_BUF_SIZE (7ULL << 8)
116#define QM_CQC_VFT_SQC_SIZE (5ULL << 12)
117#define QM_CQC_VFT_INDEX_NUMBER (1ULL << 16)
118#define QM_CQC_VFT_VALID (1ULL << 28)
119
120#define QM_SQC_VFT_BASE_SHIFT_V2 28
121#define QM_SQC_VFT_BASE_MASK_V2 GENMASK(15, 0)
122#define QM_SQC_VFT_NUM_SHIFT_V2 45
123#define QM_SQC_VFT_NUM_MASK_V2 GENMASK(9, 0)
124#define QM_MAX_QC_TYPE 2
125
126#define QM_ABNORMAL_INT_SOURCE 0x100000
127#define QM_ABNORMAL_INT_MASK 0x100004
128#define QM_ABNORMAL_INT_MASK_VALUE 0x7fff
129#define QM_ABNORMAL_INT_STATUS 0x100008
130#define QM_ABNORMAL_INT_SET 0x10000c
131#define QM_ABNORMAL_INF00 0x100010
132#define QM_FIFO_OVERFLOW_TYPE 0xc0
133#define QM_FIFO_OVERFLOW_TYPE_SHIFT 6
134#define QM_FIFO_OVERFLOW_VF 0x3f
135#define QM_FIFO_OVERFLOW_QP_SHIFT 16
136#define QM_ABNORMAL_INF01 0x100014
137#define QM_DB_TIMEOUT_TYPE 0xc0
138#define QM_DB_TIMEOUT_TYPE_SHIFT 6
139#define QM_DB_TIMEOUT_VF 0x3f
140#define QM_DB_TIMEOUT_QP_SHIFT 16
141#define QM_ABNORMAL_INF02 0x100018
142#define QM_AXI_POISON_ERR BIT(22)
143#define QM_RAS_CE_ENABLE 0x1000ec
144#define QM_RAS_FE_ENABLE 0x1000f0
145#define QM_RAS_NFE_ENABLE 0x1000f4
146#define QM_RAS_CE_THRESHOLD 0x1000f8
147#define QM_RAS_CE_TIMES_PER_IRQ 1
148#define QM_OOO_SHUTDOWN_SEL 0x1040f8
149#define QM_AXI_RRESP_ERR BIT(0)
150#define QM_DB_TIMEOUT BIT(10)
151#define QM_OF_FIFO_OF BIT(11)
152#define QM_RAS_AXI_ERROR (BIT(0) | BIT(1) | BIT(12))
153
154#define QM_RESET_WAIT_TIMEOUT 400
155#define QM_PEH_VENDOR_ID 0x1000d8
156#define ACC_VENDOR_ID_VALUE 0x5a5a
157#define QM_PEH_DFX_INFO0 0x1000fc
158#define QM_PEH_DFX_INFO1 0x100100
159#define QM_PEH_DFX_MASK (BIT(0) | BIT(2))
160#define QM_PEH_MSI_FINISH_MASK GENMASK(19, 16)
161#define ACC_PEH_SRIOV_CTRL_VF_MSE_SHIFT 3
162#define ACC_PEH_MSI_DISABLE GENMASK(31, 0)
163#define ACC_MASTER_GLOBAL_CTRL_SHUTDOWN 0x1
164#define ACC_MASTER_TRANS_RETURN_RW 3
165#define ACC_MASTER_TRANS_RETURN 0x300150
166#define ACC_MASTER_GLOBAL_CTRL 0x300000
167#define ACC_AM_CFG_PORT_WR_EN 0x30001c
168#define ACC_AM_ROB_ECC_INT_STS 0x300104
169#define ACC_ROB_ECC_ERR_MULTPL BIT(1)
170#define QM_MSI_CAP_ENABLE BIT(16)
171
172/* interfunction communication */
173#define QM_IFC_READY_STATUS 0x100128
174#define QM_IFC_INT_SET_P 0x100130
175#define QM_IFC_INT_CFG 0x100134
176#define QM_IFC_INT_SOURCE_P 0x100138
177#define QM_IFC_INT_SOURCE_V 0x0020
178#define QM_IFC_INT_MASK 0x0024
179#define QM_IFC_INT_STATUS 0x0028
180#define QM_IFC_INT_SET_V 0x002C
181#define QM_PF2VF_PF_W 0x104700
182#define QM_VF2PF_PF_R 0x104800
183#define QM_VF2PF_VF_W 0x320
184#define QM_PF2VF_VF_R 0x380
185#define QM_IFC_SEND_ALL_VFS GENMASK(6, 0)
186#define QM_IFC_INT_SOURCE_CLR GENMASK(63, 0)
187#define QM_IFC_INT_SOURCE_MASK BIT(0)
188#define QM_IFC_INT_DISABLE BIT(0)
189#define QM_IFC_INT_STATUS_MASK BIT(0)
190#define QM_IFC_INT_SET_MASK BIT(0)
191#define QM_WAIT_DST_ACK 10
192#define QM_MAX_PF_WAIT_COUNT 10
193#define QM_MAX_VF_WAIT_COUNT 40
194#define QM_VF_RESET_WAIT_US 20000
195#define QM_VF_RESET_WAIT_CNT 3000
196#define QM_VF2PF_REG_SIZE 4
197#define QM_IFC_CMD_MASK GENMASK(31, 0)
198#define QM_IFC_DATA_SHIFT 32
199#define QM_VF_RESET_WAIT_TIMEOUT_US \
200 (QM_VF_RESET_WAIT_US * QM_VF_RESET_WAIT_CNT)
201
202#define POLL_PERIOD 10
203#define POLL_TIMEOUT 1000
204#define WAIT_PERIOD_US_MAX 200
205#define WAIT_PERIOD_US_MIN 100
206#define MAX_WAIT_COUNTS 1000
207#define QM_CACHE_WB_START 0x204
208#define QM_CACHE_WB_DONE 0x208
209#define QM_FUNC_CAPS_REG 0x3100
210#define QM_CAPBILITY_VERSION GENMASK(7, 0)
211
212#define PCI_BAR_2 2
213#define PCI_BAR_4 4
214#define QMC_ALIGN(sz) ALIGN(sz, 32)
215
216#define QM_DBG_READ_LEN 256
217#define QM_PCI_COMMAND_INVALID ~0
218#define QM_RESET_STOP_TX_OFFSET 1
219#define QM_RESET_STOP_RX_OFFSET 2
220
221#define WAIT_PERIOD 20
222#define REMOVE_WAIT_DELAY 10
223
224#define QM_QOS_PARAM_NUM 2
225#define QM_QOS_MAX_VAL 1000
226#define QM_QOS_RATE 100
227#define QM_QOS_EXPAND_RATE 1000
228#define QM_SHAPER_CIR_B_MASK GENMASK(7, 0)
229#define QM_SHAPER_CIR_U_MASK GENMASK(10, 8)
230#define QM_SHAPER_CIR_S_MASK GENMASK(14, 11)
231#define QM_SHAPER_FACTOR_CIR_U_SHIFT 8
232#define QM_SHAPER_FACTOR_CIR_S_SHIFT 11
233#define QM_SHAPER_FACTOR_CBS_B_SHIFT 15
234#define QM_SHAPER_FACTOR_CBS_S_SHIFT 19
235#define QM_SHAPER_CBS_B 1
236#define QM_SHAPER_VFT_OFFSET 6
237#define QM_QOS_MIN_ERROR_RATE 5
238#define QM_SHAPER_MIN_CBS_S 8
239#define QM_QOS_TICK 0x300U
240#define QM_QOS_DIVISOR_CLK 0x1f40U
241#define QM_QOS_MAX_CIR_B 200
242#define QM_QOS_MIN_CIR_B 100
243#define QM_QOS_MAX_CIR_U 6
244#define QM_AUTOSUSPEND_DELAY 3000
245
246 /* abnormal status value for stopping queue */
247#define QM_STOP_QUEUE_FAIL 1
248#define QM_DUMP_SQC_FAIL 3
249#define QM_DUMP_CQC_FAIL 4
250#define QM_FINISH_WAIT 5
251
252#define QM_MK_CQC_DW3_V1(hop_num, pg_sz, buf_sz, cqe_sz) \
253 (((hop_num) << QM_CQ_HOP_NUM_SHIFT) | \
254 ((pg_sz) << QM_CQ_PAGE_SIZE_SHIFT) | \
255 ((buf_sz) << QM_CQ_BUF_SIZE_SHIFT) | \
256 ((cqe_sz) << QM_CQ_CQE_SIZE_SHIFT))
257
258#define QM_MK_CQC_DW3_V2(cqe_sz, cq_depth) \
259 ((((u32)cq_depth) - 1) | ((cqe_sz) << QM_CQ_CQE_SIZE_SHIFT))
260
261#define QM_MK_SQC_W13(priority, orders, alg_type) \
262 (((priority) << QM_SQ_PRIORITY_SHIFT) | \
263 ((orders) << QM_SQ_ORDERS_SHIFT) | \
264 (((alg_type) & QM_SQ_TYPE_MASK) << QM_SQ_TYPE_SHIFT))
265
266#define QM_MK_SQC_DW3_V1(hop_num, pg_sz, buf_sz, sqe_sz) \
267 (((hop_num) << QM_SQ_HOP_NUM_SHIFT) | \
268 ((pg_sz) << QM_SQ_PAGE_SIZE_SHIFT) | \
269 ((buf_sz) << QM_SQ_BUF_SIZE_SHIFT) | \
270 ((u32)ilog2(sqe_sz) << QM_SQ_SQE_SIZE_SHIFT))
271
272#define QM_MK_SQC_DW3_V2(sqe_sz, sq_depth) \
273 ((((u32)sq_depth) - 1) | ((u32)ilog2(sqe_sz) << QM_SQ_SQE_SIZE_SHIFT))
274
275enum vft_type {
276 SQC_VFT = 0,
277 CQC_VFT,
278 SHAPER_VFT,
279};
280
281enum qm_alg_type {
282 ALG_TYPE_0,
283 ALG_TYPE_1,
284};
285
286enum qm_ifc_cmd {
287 QM_PF_FLR_PREPARE = 0x01,
288 QM_PF_SRST_PREPARE,
289 QM_PF_RESET_DONE,
290 QM_VF_PREPARE_DONE,
291 QM_VF_PREPARE_FAIL,
292 QM_VF_START_DONE,
293 QM_VF_START_FAIL,
294 QM_PF_SET_QOS,
295 QM_VF_GET_QOS,
296};
297
298enum qm_basic_type {
299 QM_TOTAL_QP_NUM_CAP = 0x0,
300 QM_FUNC_MAX_QP_CAP,
301 QM_XEQ_DEPTH_CAP,
302 QM_QP_DEPTH_CAP,
303 QM_EQ_IRQ_TYPE_CAP,
304 QM_AEQ_IRQ_TYPE_CAP,
305 QM_ABN_IRQ_TYPE_CAP,
306 QM_PF2VF_IRQ_TYPE_CAP,
307 QM_PF_IRQ_NUM_CAP,
308 QM_VF_IRQ_NUM_CAP,
309};
310
311enum qm_cap_table_type {
312 QM_CAP_VF = 0x0,
313 QM_AEQE_NUM,
314 QM_SCQE_NUM,
315 QM_EQ_IRQ,
316 QM_AEQ_IRQ,
317 QM_ABNORMAL_IRQ,
318 QM_MB_IRQ,
319 MAX_IRQ_NUM,
320 EXT_BAR_INDEX,
321};
322
323static const struct hisi_qm_cap_query_info qm_cap_query_info[] = {
324 {QM_CAP_VF, "QM_CAP_VF ", 0x3100, 0x0, 0x0, 0x6F01},
325 {QM_AEQE_NUM, "QM_AEQE_NUM ", 0x3104, 0x800, 0x4000800, 0x4000800},
326 {QM_SCQE_NUM, "QM_SCQE_NUM ",
327 0x3108, 0x4000400, 0x4000400, 0x4000400},
328 {QM_EQ_IRQ, "QM_EQ_IRQ ", 0x310c, 0x10000, 0x10000, 0x10000},
329 {QM_AEQ_IRQ, "QM_AEQ_IRQ ", 0x3110, 0x0, 0x10001, 0x10001},
330 {QM_ABNORMAL_IRQ, "QM_ABNORMAL_IRQ ", 0x3114, 0x0, 0x10003, 0x10003},
331 {QM_MB_IRQ, "QM_MB_IRQ ", 0x3118, 0x0, 0x0, 0x10002},
332 {MAX_IRQ_NUM, "MAX_IRQ_NUM ", 0x311c, 0x10001, 0x40002, 0x40003},
333 {EXT_BAR_INDEX, "EXT_BAR_INDEX ", 0x3120, 0x0, 0x0, 0x14},
334};
335
336static const struct hisi_qm_cap_info qm_cap_info_comm[] = {
337 {QM_SUPPORT_DB_ISOLATION, 0x30, 0, BIT(0), 0x0, 0x0, 0x0},
338 {QM_SUPPORT_FUNC_QOS, 0x3100, 0, BIT(8), 0x0, 0x0, 0x1},
339 {QM_SUPPORT_STOP_QP, 0x3100, 0, BIT(9), 0x0, 0x0, 0x1},
340 {QM_SUPPORT_STOP_FUNC, 0x3100, 0, BIT(10), 0x0, 0x0, 0x1},
341 {QM_SUPPORT_MB_COMMAND, 0x3100, 0, BIT(11), 0x0, 0x0, 0x1},
342 {QM_SUPPORT_SVA_PREFETCH, 0x3100, 0, BIT(14), 0x0, 0x0, 0x1},
343 {QM_SUPPORT_DAE, 0x3100, 0, BIT(15), 0x0, 0x0, 0x0},
344};
345
346static const struct hisi_qm_cap_info qm_cap_info_pf[] = {
347 {QM_SUPPORT_RPM, 0x3100, 0, BIT(13), 0x0, 0x0, 0x1},
348};
349
350static const struct hisi_qm_cap_info qm_cap_info_vf[] = {
351 {QM_SUPPORT_RPM, 0x3100, 0, BIT(12), 0x0, 0x0, 0x0},
352};
353
354static const struct hisi_qm_cap_info qm_basic_info[] = {
355 {QM_TOTAL_QP_NUM_CAP, 0x100158, 0, GENMASK(10, 0), 0x1000, 0x400, 0x400},
356 {QM_FUNC_MAX_QP_CAP, 0x100158, 11, GENMASK(10, 0), 0x1000, 0x400, 0x400},
357 {QM_XEQ_DEPTH_CAP, 0x3104, 0, GENMASK(31, 0), 0x800, 0x4000800, 0x4000800},
358 {QM_QP_DEPTH_CAP, 0x3108, 0, GENMASK(31, 0), 0x4000400, 0x4000400, 0x4000400},
359 {QM_EQ_IRQ_TYPE_CAP, 0x310c, 0, GENMASK(31, 0), 0x10000, 0x10000, 0x10000},
360 {QM_AEQ_IRQ_TYPE_CAP, 0x3110, 0, GENMASK(31, 0), 0x0, 0x10001, 0x10001},
361 {QM_ABN_IRQ_TYPE_CAP, 0x3114, 0, GENMASK(31, 0), 0x0, 0x10003, 0x10003},
362 {QM_PF2VF_IRQ_TYPE_CAP, 0x3118, 0, GENMASK(31, 0), 0x0, 0x0, 0x10002},
363 {QM_PF_IRQ_NUM_CAP, 0x311c, 16, GENMASK(15, 0), 0x1, 0x4, 0x4},
364 {QM_VF_IRQ_NUM_CAP, 0x311c, 0, GENMASK(15, 0), 0x1, 0x2, 0x3},
365};
366
367struct qm_mailbox {
368 __le16 w0;
369 __le16 queue_num;
370 __le32 base_l;
371 __le32 base_h;
372 __le32 rsvd;
373};
374
375struct qm_doorbell {
376 __le16 queue_num;
377 __le16 cmd;
378 __le16 index;
379 __le16 priority;
380};
381
382struct hisi_qm_resource {
383 struct hisi_qm *qm;
384 int distance;
385 struct list_head list;
386};
387
388/**
389 * struct qm_hw_err - Structure describing the device errors
390 * @list: hardware error list
391 * @timestamp: timestamp when the error occurred
392 */
393struct qm_hw_err {
394 struct list_head list;
395 unsigned long long timestamp;
396};
397
398struct hisi_qm_hw_ops {
399 int (*get_vft)(struct hisi_qm *qm, u32 *base, u32 *number);
400 void (*qm_db)(struct hisi_qm *qm, u16 qn,
401 u8 cmd, u16 index, u8 priority);
402 int (*debug_init)(struct hisi_qm *qm);
403 void (*hw_error_init)(struct hisi_qm *qm);
404 void (*hw_error_uninit)(struct hisi_qm *qm);
405 enum acc_err_result (*hw_error_handle)(struct hisi_qm *qm);
406 int (*set_msi)(struct hisi_qm *qm, bool set);
407
408 /* (u64)msg = (u32)data << 32 | (enum qm_ifc_cmd)cmd */
409 int (*set_ifc_begin)(struct hisi_qm *qm, enum qm_ifc_cmd cmd, u32 data, u32 fun_num);
410 void (*set_ifc_end)(struct hisi_qm *qm);
411 int (*get_ifc)(struct hisi_qm *qm, enum qm_ifc_cmd *cmd, u32 *data, u32 fun_num);
412};
413
414struct hisi_qm_hw_error {
415 u32 int_msk;
416 const char *msg;
417};
418
419static const struct hisi_qm_hw_error qm_hw_error[] = {
420 { .int_msk = BIT(0), .msg = "qm_axi_rresp" },
421 { .int_msk = BIT(1), .msg = "qm_axi_bresp" },
422 { .int_msk = BIT(2), .msg = "qm_ecc_mbit" },
423 { .int_msk = BIT(3), .msg = "qm_ecc_1bit" },
424 { .int_msk = BIT(4), .msg = "qm_acc_get_task_timeout" },
425 { .int_msk = BIT(5), .msg = "qm_acc_do_task_timeout" },
426 { .int_msk = BIT(6), .msg = "qm_acc_wb_not_ready_timeout" },
427 { .int_msk = BIT(7), .msg = "qm_sq_cq_vf_invalid" },
428 { .int_msk = BIT(8), .msg = "qm_cq_vf_invalid" },
429 { .int_msk = BIT(9), .msg = "qm_sq_vf_invalid" },
430 { .int_msk = BIT(10), .msg = "qm_db_timeout" },
431 { .int_msk = BIT(11), .msg = "qm_of_fifo_of" },
432 { .int_msk = BIT(12), .msg = "qm_db_random_invalid" },
433 { .int_msk = BIT(13), .msg = "qm_mailbox_timeout" },
434 { .int_msk = BIT(14), .msg = "qm_flr_timeout" },
435};
436
437static const char * const qm_db_timeout[] = {
438 "sq", "cq", "eq", "aeq",
439};
440
441static const char * const qm_fifo_overflow[] = {
442 "cq", "eq", "aeq",
443};
444
445struct qm_typical_qos_table {
446 u32 start;
447 u32 end;
448 u32 val;
449};
450
451/* the qos step is 100 */
452static struct qm_typical_qos_table shaper_cir_s[] = {
453 {100, 100, 4},
454 {200, 200, 3},
455 {300, 500, 2},
456 {600, 1000, 1},
457 {1100, 100000, 0},
458};
459
460static struct qm_typical_qos_table shaper_cbs_s[] = {
461 {100, 200, 9},
462 {300, 500, 11},
463 {600, 1000, 12},
464 {1100, 10000, 16},
465 {10100, 25000, 17},
466 {25100, 50000, 18},
467 {50100, 100000, 19}
468};
469
470static void qm_irqs_unregister(struct hisi_qm *qm);
471static int qm_reset_device(struct hisi_qm *qm);
472int hisi_qm_q_num_set(const char *val, const struct kernel_param *kp,
473 unsigned int device)
474{
475 struct pci_dev *pdev;
476 u32 n, q_num;
477 int ret;
478
479 if (!val)
480 return -EINVAL;
481
482 pdev = pci_get_device(PCI_VENDOR_ID_HUAWEI, device, NULL);
483 if (!pdev) {
484 q_num = min_t(u32, QM_QNUM_V1, QM_QNUM_V2);
485 pr_info("No device found currently, suppose queue number is %u\n",
486 q_num);
487 } else {
488 if (pdev->revision == QM_HW_V1)
489 q_num = QM_QNUM_V1;
490 else
491 q_num = QM_QNUM_V2;
492
493 pci_dev_put(dev: pdev);
494 }
495
496 ret = kstrtou32(s: val, base: 10, res: &n);
497 if (ret || n < QM_MIN_QNUM || n > q_num)
498 return -EINVAL;
499
500 return param_set_int(val, kp);
501}
502EXPORT_SYMBOL_GPL(hisi_qm_q_num_set);
503
504static u32 qm_get_hw_error_status(struct hisi_qm *qm)
505{
506 return readl(addr: qm->io_base + QM_ABNORMAL_INT_STATUS);
507}
508
509static u32 qm_get_dev_err_status(struct hisi_qm *qm)
510{
511 return qm->err_ini->get_dev_hw_err_status(qm);
512}
513
514/* Check if the error causes the master ooo block */
515static bool qm_check_dev_error(struct hisi_qm *qm)
516{
517 struct hisi_qm *pf_qm = pci_get_drvdata(pdev: pci_physfn(dev: qm->pdev));
518 u32 err_status;
519
520 if (pf_qm->fun_type == QM_HW_VF)
521 return false;
522
523 err_status = qm_get_hw_error_status(qm: pf_qm);
524 if (err_status & pf_qm->err_info.qm_err.shutdown_mask)
525 return true;
526
527 if (pf_qm->err_ini->dev_is_abnormal)
528 return pf_qm->err_ini->dev_is_abnormal(pf_qm);
529
530 return false;
531}
532
533static int qm_wait_reset_finish(struct hisi_qm *qm)
534{
535 int delay = 0;
536
537 /* All reset requests need to be queued for processing */
538 while (test_and_set_bit(nr: QM_RESETTING, addr: &qm->misc_ctl)) {
539 msleep(msecs: ++delay);
540 if (delay > QM_RESET_WAIT_TIMEOUT)
541 return -EBUSY;
542 }
543
544 return 0;
545}
546
547static int qm_reset_prepare_ready(struct hisi_qm *qm)
548{
549 struct pci_dev *pdev = qm->pdev;
550 struct hisi_qm *pf_qm = pci_get_drvdata(pdev: pci_physfn(dev: pdev));
551
552 /*
553 * PF and VF on host doesnot support resetting at the
554 * same time on Kunpeng920.
555 */
556 if (qm->ver < QM_HW_V3)
557 return qm_wait_reset_finish(qm: pf_qm);
558
559 return qm_wait_reset_finish(qm);
560}
561
562static void qm_reset_bit_clear(struct hisi_qm *qm)
563{
564 struct pci_dev *pdev = qm->pdev;
565 struct hisi_qm *pf_qm = pci_get_drvdata(pdev: pci_physfn(dev: pdev));
566
567 if (qm->ver < QM_HW_V3)
568 clear_bit(nr: QM_RESETTING, addr: &pf_qm->misc_ctl);
569
570 clear_bit(nr: QM_RESETTING, addr: &qm->misc_ctl);
571}
572
573static void qm_mb_pre_init(struct qm_mailbox *mailbox, u8 cmd,
574 u64 base, u16 queue, bool op)
575{
576 mailbox->w0 = cpu_to_le16((cmd) |
577 ((op) ? 0x1 << QM_MB_OP_SHIFT : 0) |
578 (0x1 << QM_MB_BUSY_SHIFT));
579 mailbox->queue_num = cpu_to_le16(queue);
580 mailbox->base_l = cpu_to_le32(lower_32_bits(base));
581 mailbox->base_h = cpu_to_le32(upper_32_bits(base));
582 mailbox->rsvd = 0;
583}
584
585/* return 0 mailbox ready, -ETIMEDOUT hardware timeout */
586int hisi_qm_wait_mb_ready(struct hisi_qm *qm)
587{
588 u32 val;
589
590 return readl_relaxed_poll_timeout(qm->io_base + QM_MB_CMD_SEND_BASE,
591 val, !((val >> QM_MB_BUSY_SHIFT) &
592 0x1), POLL_PERIOD, POLL_TIMEOUT);
593}
594EXPORT_SYMBOL_GPL(hisi_qm_wait_mb_ready);
595
596/* 128 bit should be written to hardware at one time to trigger a mailbox */
597static void qm_mb_write(struct hisi_qm *qm, const void *src)
598{
599 void __iomem *fun_base = qm->io_base + QM_MB_CMD_SEND_BASE;
600
601#if IS_ENABLED(CONFIG_ARM64)
602 unsigned long tmp0 = 0, tmp1 = 0;
603#endif
604
605 if (!IS_ENABLED(CONFIG_ARM64)) {
606 memcpy_toio(fun_base, src, 16);
607 dma_wmb();
608 return;
609 }
610
611#if IS_ENABLED(CONFIG_ARM64)
612 asm volatile("ldp %0, %1, %3\n"
613 "stp %0, %1, %2\n"
614 "dmb oshst\n"
615 : "=&r" (tmp0),
616 "=&r" (tmp1),
617 "+Q" (*((char __iomem *)fun_base))
618 : "Q" (*((char *)src))
619 : "memory");
620#endif
621}
622
623static int qm_mb_nolock(struct hisi_qm *qm, struct qm_mailbox *mailbox)
624{
625 int ret;
626 u32 val;
627
628 if (unlikely(hisi_qm_wait_mb_ready(qm))) {
629 dev_err(&qm->pdev->dev, "QM mailbox is busy to start!\n");
630 ret = -EBUSY;
631 goto mb_busy;
632 }
633
634 qm_mb_write(qm, src: mailbox);
635
636 if (unlikely(hisi_qm_wait_mb_ready(qm))) {
637 dev_err(&qm->pdev->dev, "QM mailbox operation timeout!\n");
638 ret = -ETIMEDOUT;
639 goto mb_busy;
640 }
641
642 val = readl(addr: qm->io_base + QM_MB_CMD_SEND_BASE);
643 if (val & QM_MB_STATUS_MASK) {
644 dev_err(&qm->pdev->dev, "QM mailbox operation failed!\n");
645 ret = -EIO;
646 goto mb_busy;
647 }
648
649 return 0;
650
651mb_busy:
652 atomic64_inc(v: &qm->debug.dfx.mb_err_cnt);
653 return ret;
654}
655
656int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,
657 bool op)
658{
659 struct qm_mailbox mailbox;
660 int ret;
661
662 qm_mb_pre_init(mailbox: &mailbox, cmd, base: dma_addr, queue, op);
663
664 mutex_lock(&qm->mailbox_lock);
665 ret = qm_mb_nolock(qm, mailbox: &mailbox);
666 mutex_unlock(lock: &qm->mailbox_lock);
667
668 return ret;
669}
670EXPORT_SYMBOL_GPL(hisi_qm_mb);
671
672/* op 0: set xqc information to hardware, 1: get xqc information from hardware. */
673int qm_set_and_get_xqc(struct hisi_qm *qm, u8 cmd, void *xqc, u32 qp_id, bool op)
674{
675 struct qm_mailbox mailbox;
676 dma_addr_t xqc_dma;
677 void *tmp_xqc;
678 size_t size;
679 int ret;
680
681 switch (cmd) {
682 case QM_MB_CMD_SQC:
683 size = sizeof(struct qm_sqc);
684 tmp_xqc = qm->xqc_buf.sqc;
685 xqc_dma = qm->xqc_buf.sqc_dma;
686 break;
687 case QM_MB_CMD_CQC:
688 size = sizeof(struct qm_cqc);
689 tmp_xqc = qm->xqc_buf.cqc;
690 xqc_dma = qm->xqc_buf.cqc_dma;
691 break;
692 case QM_MB_CMD_EQC:
693 size = sizeof(struct qm_eqc);
694 tmp_xqc = qm->xqc_buf.eqc;
695 xqc_dma = qm->xqc_buf.eqc_dma;
696 break;
697 case QM_MB_CMD_AEQC:
698 size = sizeof(struct qm_aeqc);
699 tmp_xqc = qm->xqc_buf.aeqc;
700 xqc_dma = qm->xqc_buf.aeqc_dma;
701 break;
702 default:
703 dev_err(&qm->pdev->dev, "unknown mailbox cmd %u\n", cmd);
704 return -EINVAL;
705 }
706
707 /* Setting xqc will fail if master OOO is blocked. */
708 if (qm_check_dev_error(qm)) {
709 dev_err(&qm->pdev->dev, "failed to send mailbox since qm is stop!\n");
710 return -EIO;
711 }
712
713 mutex_lock(&qm->mailbox_lock);
714 if (!op)
715 memcpy(tmp_xqc, xqc, size);
716
717 qm_mb_pre_init(mailbox: &mailbox, cmd, base: xqc_dma, queue: qp_id, op);
718 ret = qm_mb_nolock(qm, mailbox: &mailbox);
719 if (!ret && op)
720 memcpy(xqc, tmp_xqc, size);
721
722 mutex_unlock(lock: &qm->mailbox_lock);
723
724 return ret;
725}
726
727static void qm_db_v1(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority)
728{
729 u64 doorbell;
730
731 doorbell = qn | ((u64)cmd << QM_DB_CMD_SHIFT_V1) |
732 ((u64)index << QM_DB_INDEX_SHIFT_V1) |
733 ((u64)priority << QM_DB_PRIORITY_SHIFT_V1);
734
735 writeq(val: doorbell, addr: qm->io_base + QM_DOORBELL_BASE_V1);
736}
737
738static void qm_db_v2(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority)
739{
740 void __iomem *io_base = qm->io_base;
741 u16 randata = 0;
742 u64 doorbell;
743
744 if (cmd == QM_DOORBELL_CMD_SQ || cmd == QM_DOORBELL_CMD_CQ)
745 io_base = qm->db_io_base + (u64)qn * qm->db_interval +
746 QM_DOORBELL_SQ_CQ_BASE_V2;
747 else
748 io_base += QM_DOORBELL_EQ_AEQ_BASE_V2;
749
750 doorbell = qn | ((u64)cmd << QM_DB_CMD_SHIFT_V2) |
751 ((u64)randata << QM_DB_RAND_SHIFT_V2) |
752 ((u64)index << QM_DB_INDEX_SHIFT_V2) |
753 ((u64)priority << QM_DB_PRIORITY_SHIFT_V2);
754
755 writeq(val: doorbell, addr: io_base);
756}
757
758static void qm_db(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority)
759{
760 dev_dbg(&qm->pdev->dev, "QM doorbell request: qn=%u, cmd=%u, index=%u\n",
761 qn, cmd, index);
762
763 qm->ops->qm_db(qm, qn, cmd, index, priority);
764}
765
766static void qm_disable_clock_gate(struct hisi_qm *qm)
767{
768 u32 val;
769
770 /* if qm enables clock gating in Kunpeng930, qos will be inaccurate. */
771 if (qm->ver < QM_HW_V3)
772 return;
773
774 val = readl(addr: qm->io_base + QM_PM_CTRL);
775 val |= QM_IDLE_DISABLE;
776 writel(val, addr: qm->io_base + QM_PM_CTRL);
777}
778
779static int qm_dev_mem_reset(struct hisi_qm *qm)
780{
781 u32 val;
782
783 writel(val: 0x1, addr: qm->io_base + QM_MEM_START_INIT);
784 return readl_relaxed_poll_timeout(qm->io_base + QM_MEM_INIT_DONE, val,
785 val & BIT(0), POLL_PERIOD,
786 POLL_TIMEOUT);
787}
788
789/**
790 * hisi_qm_get_hw_info() - Get device information.
791 * @qm: The qm which want to get information.
792 * @info_table: Array for storing device information.
793 * @index: Index in info_table.
794 * @is_read: Whether read from reg, 0: not support read from reg.
795 *
796 * This function returns device information the caller needs.
797 */
798u32 hisi_qm_get_hw_info(struct hisi_qm *qm,
799 const struct hisi_qm_cap_info *info_table,
800 u32 index, bool is_read)
801{
802 u32 val;
803
804 switch (qm->ver) {
805 case QM_HW_V1:
806 return info_table[index].v1_val;
807 case QM_HW_V2:
808 return info_table[index].v2_val;
809 default:
810 if (!is_read)
811 return info_table[index].v3_val;
812
813 val = readl(addr: qm->io_base + info_table[index].offset);
814 return (val >> info_table[index].shift) & info_table[index].mask;
815 }
816}
817EXPORT_SYMBOL_GPL(hisi_qm_get_hw_info);
818
819u32 hisi_qm_get_cap_value(struct hisi_qm *qm,
820 const struct hisi_qm_cap_query_info *info_table,
821 u32 index, bool is_read)
822{
823 u32 val;
824
825 switch (qm->ver) {
826 case QM_HW_V1:
827 return info_table[index].v1_val;
828 case QM_HW_V2:
829 return info_table[index].v2_val;
830 default:
831 if (!is_read)
832 return info_table[index].v3_val;
833
834 val = readl(addr: qm->io_base + info_table[index].offset);
835 return val;
836 }
837}
838EXPORT_SYMBOL_GPL(hisi_qm_get_cap_value);
839
840static void qm_get_xqc_depth(struct hisi_qm *qm, u16 *low_bits,
841 u16 *high_bits, enum qm_basic_type type)
842{
843 u32 depth;
844
845 depth = hisi_qm_get_hw_info(qm, qm_basic_info, type, qm->cap_ver);
846 *low_bits = depth & QM_XQ_DEPTH_MASK;
847 *high_bits = (depth >> QM_XQ_DEPTH_SHIFT) & QM_XQ_DEPTH_MASK;
848}
849
850int hisi_qm_set_algs(struct hisi_qm *qm, u64 alg_msk, const struct qm_dev_alg *dev_algs,
851 u32 dev_algs_size)
852{
853 struct device *dev = &qm->pdev->dev;
854 char *algs, *ptr;
855 int i;
856
857 if (!qm->uacce)
858 return 0;
859
860 if (dev_algs_size >= QM_DEV_ALG_MAX_LEN) {
861 dev_err(dev, "algs size %u is equal or larger than %d.\n",
862 dev_algs_size, QM_DEV_ALG_MAX_LEN);
863 return -EINVAL;
864 }
865
866 algs = devm_kzalloc(dev, QM_DEV_ALG_MAX_LEN, GFP_KERNEL);
867 if (!algs)
868 return -ENOMEM;
869
870 for (i = 0; i < dev_algs_size; i++)
871 if (alg_msk & dev_algs[i].alg_msk)
872 strcat(p: algs, q: dev_algs[i].alg);
873
874 ptr = strrchr(algs, '\n');
875 if (ptr)
876 *ptr = '\0';
877
878 qm->uacce->algs = algs;
879
880 return 0;
881}
882EXPORT_SYMBOL_GPL(hisi_qm_set_algs);
883
884static u32 qm_get_irq_num(struct hisi_qm *qm)
885{
886 if (qm->fun_type == QM_HW_PF)
887 return hisi_qm_get_hw_info(qm, qm_basic_info, QM_PF_IRQ_NUM_CAP, qm->cap_ver);
888
889 return hisi_qm_get_hw_info(qm, qm_basic_info, QM_VF_IRQ_NUM_CAP, qm->cap_ver);
890}
891
892static int qm_pm_get_sync(struct hisi_qm *qm)
893{
894 struct device *dev = &qm->pdev->dev;
895 int ret;
896
897 if (!test_bit(QM_SUPPORT_RPM, &qm->caps))
898 return 0;
899
900 ret = pm_runtime_resume_and_get(dev);
901 if (ret < 0) {
902 dev_err(dev, "failed to get_sync(%d).\n", ret);
903 return ret;
904 }
905
906 return 0;
907}
908
909static void qm_pm_put_sync(struct hisi_qm *qm)
910{
911 struct device *dev = &qm->pdev->dev;
912
913 if (!test_bit(QM_SUPPORT_RPM, &qm->caps))
914 return;
915
916 pm_runtime_put_autosuspend(dev);
917}
918
919static void qm_cq_head_update(struct hisi_qp *qp)
920{
921 if (qp->qp_status.cq_head == qp->cq_depth - 1) {
922 qp->qp_status.cqc_phase = !qp->qp_status.cqc_phase;
923 qp->qp_status.cq_head = 0;
924 } else {
925 qp->qp_status.cq_head++;
926 }
927}
928
929static void qm_poll_req_cb(struct hisi_qp *qp)
930{
931 struct qm_cqe *cqe = qp->cqe + qp->qp_status.cq_head;
932 struct hisi_qm *qm = qp->qm;
933
934 while (QM_CQE_PHASE(cqe) == qp->qp_status.cqc_phase) {
935 dma_rmb();
936 qp->req_cb(qp, qp->sqe + qm->sqe_size *
937 le16_to_cpu(cqe->sq_head));
938 qm_cq_head_update(qp);
939 cqe = qp->cqe + qp->qp_status.cq_head;
940 qm_db(qm, qn: qp->qp_id, QM_DOORBELL_CMD_CQ,
941 index: qp->qp_status.cq_head, priority: 0);
942 atomic_dec(v: &qp->qp_status.used);
943
944 cond_resched();
945 }
946
947 /* set c_flag */
948 qm_db(qm, qn: qp->qp_id, QM_DOORBELL_CMD_CQ, index: qp->qp_status.cq_head, priority: 1);
949}
950
951static void qm_work_process(struct work_struct *work)
952{
953 struct hisi_qm_poll_data *poll_data =
954 container_of(work, struct hisi_qm_poll_data, work);
955 struct hisi_qm *qm = poll_data->qm;
956 u16 eqe_num = poll_data->eqe_num;
957 struct hisi_qp *qp;
958 int i;
959
960 for (i = eqe_num - 1; i >= 0; i--) {
961 qp = &qm->qp_array[poll_data->qp_finish_id[i]];
962 if (unlikely(atomic_read(&qp->qp_status.flags) == QP_STOP))
963 continue;
964
965 if (qp->event_cb) {
966 qp->event_cb(qp);
967 continue;
968 }
969
970 if (likely(qp->req_cb))
971 qm_poll_req_cb(qp);
972 }
973}
974
975static void qm_get_complete_eqe_num(struct hisi_qm *qm)
976{
977 struct qm_eqe *eqe = qm->eqe + qm->status.eq_head;
978 struct hisi_qm_poll_data *poll_data = NULL;
979 u32 dw0 = le32_to_cpu(eqe->dw0);
980 u16 eq_depth = qm->eq_depth;
981 u16 cqn, eqe_num = 0;
982
983 if (QM_EQE_PHASE(dw0) != qm->status.eqc_phase) {
984 atomic64_inc(v: &qm->debug.dfx.err_irq_cnt);
985 qm_db(qm, qn: 0, QM_DOORBELL_CMD_EQ, index: qm->status.eq_head, priority: 0);
986 return;
987 }
988
989 cqn = dw0 & QM_EQE_CQN_MASK;
990 if (unlikely(cqn >= qm->qp_num))
991 return;
992 poll_data = &qm->poll_data[cqn];
993
994 do {
995 poll_data->qp_finish_id[eqe_num] = dw0 & QM_EQE_CQN_MASK;
996 eqe_num++;
997
998 if (qm->status.eq_head == eq_depth - 1) {
999 qm->status.eqc_phase = !qm->status.eqc_phase;
1000 eqe = qm->eqe;
1001 qm->status.eq_head = 0;
1002 } else {
1003 eqe++;
1004 qm->status.eq_head++;
1005 }
1006
1007 dw0 = le32_to_cpu(eqe->dw0);
1008 if (QM_EQE_PHASE(dw0) != qm->status.eqc_phase)
1009 break;
1010 } while (eqe_num < (eq_depth >> 1) - 1);
1011
1012 poll_data->eqe_num = eqe_num;
1013 queue_work(wq: qm->wq, work: &poll_data->work);
1014 qm_db(qm, qn: 0, QM_DOORBELL_CMD_EQ, index: qm->status.eq_head, priority: 0);
1015}
1016
1017static irqreturn_t qm_eq_irq(int irq, void *data)
1018{
1019 struct hisi_qm *qm = data;
1020
1021 /* Get qp id of completed tasks and re-enable the interrupt */
1022 qm_get_complete_eqe_num(qm);
1023
1024 return IRQ_HANDLED;
1025}
1026
1027static irqreturn_t qm_mb_cmd_irq(int irq, void *data)
1028{
1029 struct hisi_qm *qm = data;
1030 u32 val;
1031
1032 val = readl(addr: qm->io_base + QM_IFC_INT_STATUS);
1033 val &= QM_IFC_INT_STATUS_MASK;
1034 if (!val)
1035 return IRQ_NONE;
1036
1037 if (test_bit(QM_DRIVER_REMOVING, &qm->misc_ctl)) {
1038 dev_warn(&qm->pdev->dev, "Driver is down, message cannot be processed!\n");
1039 return IRQ_HANDLED;
1040 }
1041
1042 schedule_work(work: &qm->cmd_process);
1043
1044 return IRQ_HANDLED;
1045}
1046
1047static void qm_set_qp_disable(struct hisi_qp *qp, int offset)
1048{
1049 u32 *addr;
1050
1051 if (qp->is_in_kernel)
1052 return;
1053
1054 addr = (u32 *)(qp->qdma.va + qp->qdma.size) - offset;
1055 *addr = 1;
1056
1057 /* make sure setup is completed */
1058 smp_wmb();
1059}
1060
1061static void qm_disable_qp(struct hisi_qm *qm, u32 qp_id)
1062{
1063 struct hisi_qp *qp = &qm->qp_array[qp_id];
1064
1065 qm_set_qp_disable(qp, QM_RESET_STOP_TX_OFFSET);
1066 hisi_qm_stop_qp(qp);
1067 qm_set_qp_disable(qp, QM_RESET_STOP_RX_OFFSET);
1068}
1069
1070static void qm_reset_function(struct hisi_qm *qm)
1071{
1072 struct device *dev = &qm->pdev->dev;
1073 int ret;
1074
1075 if (qm_check_dev_error(qm))
1076 return;
1077
1078 ret = qm_reset_prepare_ready(qm);
1079 if (ret) {
1080 dev_err(dev, "reset function not ready\n");
1081 return;
1082 }
1083
1084 ret = hisi_qm_stop(qm, r: QM_DOWN);
1085 if (ret) {
1086 dev_err(dev, "failed to stop qm when reset function\n");
1087 goto clear_bit;
1088 }
1089
1090 ret = hisi_qm_start(qm);
1091 if (ret)
1092 dev_err(dev, "failed to start qm when reset function\n");
1093
1094clear_bit:
1095 qm_reset_bit_clear(qm);
1096}
1097
1098static irqreturn_t qm_aeq_thread(int irq, void *data)
1099{
1100 struct hisi_qm *qm = data;
1101 struct qm_aeqe *aeqe = qm->aeqe + qm->status.aeq_head;
1102 u32 dw0 = le32_to_cpu(aeqe->dw0);
1103 u16 aeq_depth = qm->aeq_depth;
1104 u32 type, qp_id;
1105
1106 atomic64_inc(v: &qm->debug.dfx.aeq_irq_cnt);
1107
1108 while (QM_AEQE_PHASE(dw0) == qm->status.aeqc_phase) {
1109 type = (dw0 >> QM_AEQE_TYPE_SHIFT) & QM_AEQE_TYPE_MASK;
1110 qp_id = dw0 & QM_AEQE_CQN_MASK;
1111
1112 switch (type) {
1113 case QM_EQ_OVERFLOW:
1114 dev_err(&qm->pdev->dev, "eq overflow, reset function\n");
1115 qm_reset_function(qm);
1116 return IRQ_HANDLED;
1117 case QM_CQ_OVERFLOW:
1118 dev_err(&qm->pdev->dev, "cq overflow, stop qp(%u)\n",
1119 qp_id);
1120 fallthrough;
1121 case QM_CQE_ERROR:
1122 qm_disable_qp(qm, qp_id);
1123 break;
1124 default:
1125 dev_err(&qm->pdev->dev, "unknown error type %u\n",
1126 type);
1127 break;
1128 }
1129
1130 if (qm->status.aeq_head == aeq_depth - 1) {
1131 qm->status.aeqc_phase = !qm->status.aeqc_phase;
1132 aeqe = qm->aeqe;
1133 qm->status.aeq_head = 0;
1134 } else {
1135 aeqe++;
1136 qm->status.aeq_head++;
1137 }
1138 dw0 = le32_to_cpu(aeqe->dw0);
1139 }
1140
1141 qm_db(qm, qn: 0, QM_DOORBELL_CMD_AEQ, index: qm->status.aeq_head, priority: 0);
1142
1143 return IRQ_HANDLED;
1144}
1145
1146static void qm_init_qp_status(struct hisi_qp *qp)
1147{
1148 struct hisi_qp_status *qp_status = &qp->qp_status;
1149
1150 qp_status->sq_tail = 0;
1151 qp_status->cq_head = 0;
1152 qp_status->cqc_phase = true;
1153 atomic_set(v: &qp_status->used, i: 0);
1154}
1155
1156static void qm_init_prefetch(struct hisi_qm *qm)
1157{
1158 struct device *dev = &qm->pdev->dev;
1159 u32 page_type = 0x0;
1160
1161 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))
1162 return;
1163
1164 switch (PAGE_SIZE) {
1165 case SZ_4K:
1166 page_type = 0x0;
1167 break;
1168 case SZ_16K:
1169 page_type = 0x1;
1170 break;
1171 case SZ_64K:
1172 page_type = 0x2;
1173 break;
1174 default:
1175 dev_err(dev, "system page size is not support: %lu, default set to 4KB",
1176 PAGE_SIZE);
1177 }
1178
1179 writel(val: page_type, addr: qm->io_base + QM_PAGE_SIZE);
1180}
1181
1182/*
1183 * acc_shaper_para_calc() Get the IR value by the qos formula, the return value
1184 * is the expected qos calculated.
1185 * the formula:
1186 * IR = X Mbps if ir = 1 means IR = 100 Mbps, if ir = 10000 means = 10Gbps
1187 *
1188 * IR_b * (2 ^ IR_u) * 8000
1189 * IR(Mbps) = -------------------------
1190 * Tick * (2 ^ IR_s)
1191 */
1192static u32 acc_shaper_para_calc(u64 cir_b, u64 cir_u, u64 cir_s)
1193{
1194 return ((cir_b * QM_QOS_DIVISOR_CLK) * (1 << cir_u)) /
1195 (QM_QOS_TICK * (1 << cir_s));
1196}
1197
1198static u32 acc_shaper_calc_cbs_s(u32 ir)
1199{
1200 int table_size = ARRAY_SIZE(shaper_cbs_s);
1201 int i;
1202
1203 for (i = 0; i < table_size; i++) {
1204 if (ir >= shaper_cbs_s[i].start && ir <= shaper_cbs_s[i].end)
1205 return shaper_cbs_s[i].val;
1206 }
1207
1208 return QM_SHAPER_MIN_CBS_S;
1209}
1210
1211static u32 acc_shaper_calc_cir_s(u32 ir)
1212{
1213 int table_size = ARRAY_SIZE(shaper_cir_s);
1214 int i;
1215
1216 for (i = 0; i < table_size; i++) {
1217 if (ir >= shaper_cir_s[i].start && ir <= shaper_cir_s[i].end)
1218 return shaper_cir_s[i].val;
1219 }
1220
1221 return 0;
1222}
1223
1224static int qm_get_shaper_para(u32 ir, struct qm_shaper_factor *factor)
1225{
1226 u32 cir_b, cir_u, cir_s, ir_calc;
1227 u32 error_rate;
1228
1229 factor->cbs_s = acc_shaper_calc_cbs_s(ir);
1230 cir_s = acc_shaper_calc_cir_s(ir);
1231
1232 for (cir_b = QM_QOS_MIN_CIR_B; cir_b <= QM_QOS_MAX_CIR_B; cir_b++) {
1233 for (cir_u = 0; cir_u <= QM_QOS_MAX_CIR_U; cir_u++) {
1234 ir_calc = acc_shaper_para_calc(cir_b, cir_u, cir_s);
1235
1236 error_rate = QM_QOS_EXPAND_RATE * (u32)abs(ir_calc - ir) / ir;
1237 if (error_rate <= QM_QOS_MIN_ERROR_RATE) {
1238 factor->cir_b = cir_b;
1239 factor->cir_u = cir_u;
1240 factor->cir_s = cir_s;
1241 return 0;
1242 }
1243 }
1244 }
1245
1246 return -EINVAL;
1247}
1248
1249static void qm_vft_data_cfg(struct hisi_qm *qm, enum vft_type type, u32 base,
1250 u32 number, struct qm_shaper_factor *factor)
1251{
1252 u64 tmp = 0;
1253
1254 if (number > 0) {
1255 switch (type) {
1256 case SQC_VFT:
1257 if (qm->ver == QM_HW_V1) {
1258 tmp = QM_SQC_VFT_BUF_SIZE |
1259 QM_SQC_VFT_SQC_SIZE |
1260 QM_SQC_VFT_INDEX_NUMBER |
1261 QM_SQC_VFT_VALID |
1262 (u64)base << QM_SQC_VFT_START_SQN_SHIFT;
1263 } else {
1264 tmp = (u64)base << QM_SQC_VFT_START_SQN_SHIFT |
1265 QM_SQC_VFT_VALID |
1266 (u64)(number - 1) << QM_SQC_VFT_SQN_SHIFT;
1267 }
1268 break;
1269 case CQC_VFT:
1270 if (qm->ver == QM_HW_V1) {
1271 tmp = QM_CQC_VFT_BUF_SIZE |
1272 QM_CQC_VFT_SQC_SIZE |
1273 QM_CQC_VFT_INDEX_NUMBER |
1274 QM_CQC_VFT_VALID;
1275 } else {
1276 tmp = QM_CQC_VFT_VALID;
1277 }
1278 break;
1279 case SHAPER_VFT:
1280 if (factor) {
1281 tmp = factor->cir_b |
1282 (factor->cir_u << QM_SHAPER_FACTOR_CIR_U_SHIFT) |
1283 (factor->cir_s << QM_SHAPER_FACTOR_CIR_S_SHIFT) |
1284 (QM_SHAPER_CBS_B << QM_SHAPER_FACTOR_CBS_B_SHIFT) |
1285 (factor->cbs_s << QM_SHAPER_FACTOR_CBS_S_SHIFT);
1286 }
1287 break;
1288 /*
1289 * Note: The current logic only needs to handle the above three types
1290 * If new types are added, they need to be supplemented here,
1291 * otherwise undefined behavior may occur.
1292 */
1293 default:
1294 break;
1295 }
1296 }
1297
1298 writel(lower_32_bits(tmp), addr: qm->io_base + QM_VFT_CFG_DATA_L);
1299 writel(upper_32_bits(tmp), addr: qm->io_base + QM_VFT_CFG_DATA_H);
1300}
1301
1302static int qm_set_vft_common(struct hisi_qm *qm, enum vft_type type,
1303 u32 fun_num, u32 base, u32 number)
1304{
1305 struct qm_shaper_factor *factor = NULL;
1306 unsigned int val;
1307 int ret;
1308
1309 if (type == SHAPER_VFT && test_bit(QM_SUPPORT_FUNC_QOS, &qm->caps))
1310 factor = &qm->factor[fun_num];
1311
1312 ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
1313 val & BIT(0), POLL_PERIOD,
1314 POLL_TIMEOUT);
1315 if (ret)
1316 return ret;
1317
1318 writel(val: 0x0, addr: qm->io_base + QM_VFT_CFG_OP_WR);
1319 writel(val: type, addr: qm->io_base + QM_VFT_CFG_TYPE);
1320 if (type == SHAPER_VFT)
1321 fun_num |= base << QM_SHAPER_VFT_OFFSET;
1322
1323 writel(val: fun_num, addr: qm->io_base + QM_VFT_CFG);
1324
1325 qm_vft_data_cfg(qm, type, base, number, factor);
1326
1327 writel(val: 0x0, addr: qm->io_base + QM_VFT_CFG_RDY);
1328 writel(val: 0x1, addr: qm->io_base + QM_VFT_CFG_OP_ENABLE);
1329
1330 return readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
1331 val & BIT(0), POLL_PERIOD,
1332 POLL_TIMEOUT);
1333}
1334
1335static int qm_shaper_init_vft(struct hisi_qm *qm, u32 fun_num)
1336{
1337 u32 qos = qm->factor[fun_num].func_qos;
1338 int ret, i;
1339
1340 ret = qm_get_shaper_para(ir: qos * QM_QOS_RATE, factor: &qm->factor[fun_num]);
1341 if (ret) {
1342 dev_err(&qm->pdev->dev, "failed to calculate shaper parameter!\n");
1343 return ret;
1344 }
1345 writel(val: qm->type_rate, addr: qm->io_base + QM_SHAPER_CFG);
1346 for (i = ALG_TYPE_0; i <= ALG_TYPE_1; i++) {
1347 /* The base number of queue reuse for different alg type */
1348 ret = qm_set_vft_common(qm, type: SHAPER_VFT, fun_num, base: i, number: 1);
1349 if (ret)
1350 return ret;
1351 }
1352
1353 return 0;
1354}
1355
1356/* The config should be conducted after qm_dev_mem_reset() */
1357static int qm_set_sqc_cqc_vft(struct hisi_qm *qm, u32 fun_num, u32 base,
1358 u32 number)
1359{
1360 int ret, i;
1361
1362 for (i = SQC_VFT; i <= CQC_VFT; i++) {
1363 ret = qm_set_vft_common(qm, type: i, fun_num, base, number);
1364 if (ret)
1365 return ret;
1366 }
1367
1368 /* init default shaper qos val */
1369 if (test_bit(QM_SUPPORT_FUNC_QOS, &qm->caps)) {
1370 ret = qm_shaper_init_vft(qm, fun_num);
1371 if (ret)
1372 goto back_sqc_cqc;
1373 }
1374
1375 return 0;
1376back_sqc_cqc:
1377 for (i = SQC_VFT; i <= CQC_VFT; i++)
1378 qm_set_vft_common(qm, type: i, fun_num, base: 0, number: 0);
1379
1380 return ret;
1381}
1382
1383static int qm_get_vft_v2(struct hisi_qm *qm, u32 *base, u32 *number)
1384{
1385 u64 sqc_vft;
1386 int ret;
1387
1388 ret = hisi_qm_mb(qm, QM_MB_CMD_SQC_VFT_V2, 0, 0, 1);
1389 if (ret)
1390 return ret;
1391
1392 sqc_vft = readl(addr: qm->io_base + QM_MB_CMD_DATA_ADDR_L) |
1393 ((u64)readl(addr: qm->io_base + QM_MB_CMD_DATA_ADDR_H) << 32);
1394 *base = QM_SQC_VFT_BASE_MASK_V2 & (sqc_vft >> QM_SQC_VFT_BASE_SHIFT_V2);
1395 *number = (QM_SQC_VFT_NUM_MASK_V2 &
1396 (sqc_vft >> QM_SQC_VFT_NUM_SHIFT_V2)) + 1;
1397
1398 return 0;
1399}
1400
1401static void qm_hw_error_init_v1(struct hisi_qm *qm)
1402{
1403 writel(QM_ABNORMAL_INT_MASK_VALUE, addr: qm->io_base + QM_ABNORMAL_INT_MASK);
1404}
1405
1406static void qm_hw_error_cfg(struct hisi_qm *qm)
1407{
1408 struct hisi_qm_err_mask *qm_err = &qm->err_info.qm_err;
1409
1410 qm->error_mask = qm_err->nfe | qm_err->ce | qm_err->fe;
1411 /* clear QM hw residual error source */
1412 writel(val: qm->error_mask, addr: qm->io_base + QM_ABNORMAL_INT_SOURCE);
1413
1414 /* configure error type */
1415 writel(val: qm_err->ce, addr: qm->io_base + QM_RAS_CE_ENABLE);
1416 writel(QM_RAS_CE_TIMES_PER_IRQ, addr: qm->io_base + QM_RAS_CE_THRESHOLD);
1417 writel(val: qm_err->nfe, addr: qm->io_base + QM_RAS_NFE_ENABLE);
1418 writel(val: qm_err->fe, addr: qm->io_base + QM_RAS_FE_ENABLE);
1419}
1420
1421static void qm_hw_error_init_v2(struct hisi_qm *qm)
1422{
1423 u32 irq_unmask;
1424
1425 qm_hw_error_cfg(qm);
1426
1427 irq_unmask = ~qm->error_mask;
1428 irq_unmask &= readl(addr: qm->io_base + QM_ABNORMAL_INT_MASK);
1429 writel(val: irq_unmask, addr: qm->io_base + QM_ABNORMAL_INT_MASK);
1430}
1431
1432static void qm_hw_error_uninit_v2(struct hisi_qm *qm)
1433{
1434 u32 irq_mask = qm->error_mask;
1435
1436 irq_mask |= readl(addr: qm->io_base + QM_ABNORMAL_INT_MASK);
1437 writel(val: irq_mask, addr: qm->io_base + QM_ABNORMAL_INT_MASK);
1438}
1439
1440static void qm_hw_error_init_v3(struct hisi_qm *qm)
1441{
1442 u32 irq_unmask;
1443
1444 qm_hw_error_cfg(qm);
1445
1446 /* enable close master ooo when hardware error happened */
1447 writel(val: qm->err_info.qm_err.shutdown_mask, addr: qm->io_base + QM_OOO_SHUTDOWN_SEL);
1448
1449 irq_unmask = ~qm->error_mask;
1450 irq_unmask &= readl(addr: qm->io_base + QM_ABNORMAL_INT_MASK);
1451 writel(val: irq_unmask, addr: qm->io_base + QM_ABNORMAL_INT_MASK);
1452}
1453
1454static void qm_hw_error_uninit_v3(struct hisi_qm *qm)
1455{
1456 u32 irq_mask = qm->error_mask;
1457
1458 irq_mask |= readl(addr: qm->io_base + QM_ABNORMAL_INT_MASK);
1459 writel(val: irq_mask, addr: qm->io_base + QM_ABNORMAL_INT_MASK);
1460
1461 /* disable close master ooo when hardware error happened */
1462 writel(val: 0x0, addr: qm->io_base + QM_OOO_SHUTDOWN_SEL);
1463}
1464
1465static void qm_log_hw_error(struct hisi_qm *qm, u32 error_status)
1466{
1467 const struct hisi_qm_hw_error *err;
1468 struct device *dev = &qm->pdev->dev;
1469 u32 reg_val, type, vf_num, qp_id;
1470 int i;
1471
1472 for (i = 0; i < ARRAY_SIZE(qm_hw_error); i++) {
1473 err = &qm_hw_error[i];
1474 if (!(err->int_msk & error_status))
1475 continue;
1476
1477 dev_err(dev, "%s [error status=0x%x] found\n",
1478 err->msg, err->int_msk);
1479
1480 if (err->int_msk & QM_DB_TIMEOUT) {
1481 reg_val = readl(addr: qm->io_base + QM_ABNORMAL_INF01);
1482 type = (reg_val & QM_DB_TIMEOUT_TYPE) >>
1483 QM_DB_TIMEOUT_TYPE_SHIFT;
1484 vf_num = reg_val & QM_DB_TIMEOUT_VF;
1485 qp_id = reg_val >> QM_DB_TIMEOUT_QP_SHIFT;
1486 dev_err(dev, "qm %s doorbell timeout in function %u qp %u\n",
1487 qm_db_timeout[type], vf_num, qp_id);
1488 } else if (err->int_msk & QM_OF_FIFO_OF) {
1489 reg_val = readl(addr: qm->io_base + QM_ABNORMAL_INF00);
1490 type = (reg_val & QM_FIFO_OVERFLOW_TYPE) >>
1491 QM_FIFO_OVERFLOW_TYPE_SHIFT;
1492 vf_num = reg_val & QM_FIFO_OVERFLOW_VF;
1493 qp_id = reg_val >> QM_FIFO_OVERFLOW_QP_SHIFT;
1494 if (type < ARRAY_SIZE(qm_fifo_overflow))
1495 dev_err(dev, "qm %s fifo overflow in function %u qp %u\n",
1496 qm_fifo_overflow[type], vf_num, qp_id);
1497 else
1498 dev_err(dev, "unknown error type\n");
1499 } else if (err->int_msk & QM_AXI_RRESP_ERR) {
1500 reg_val = readl(addr: qm->io_base + QM_ABNORMAL_INF02);
1501 if (reg_val & QM_AXI_POISON_ERR)
1502 dev_err(dev, "qm axi poison error happened\n");
1503 }
1504 }
1505}
1506
1507static enum acc_err_result qm_hw_error_handle_v2(struct hisi_qm *qm)
1508{
1509 struct hisi_qm_err_mask *qm_err = &qm->err_info.qm_err;
1510 u32 error_status;
1511
1512 error_status = qm_get_hw_error_status(qm);
1513 if (error_status & qm->error_mask) {
1514 if (error_status & QM_ECC_MBIT)
1515 qm->err_status.is_qm_ecc_mbit = true;
1516
1517 qm_log_hw_error(qm, error_status);
1518 if (error_status & qm_err->reset_mask) {
1519 /* Disable the same error reporting until device is recovered. */
1520 writel(val: qm_err->nfe & (~error_status), addr: qm->io_base + QM_RAS_NFE_ENABLE);
1521 return ACC_ERR_NEED_RESET;
1522 }
1523
1524 /* Clear error source if not need reset. */
1525 writel(val: error_status, addr: qm->io_base + QM_ABNORMAL_INT_SOURCE);
1526 writel(val: qm_err->nfe, addr: qm->io_base + QM_RAS_NFE_ENABLE);
1527 writel(val: qm_err->ce, addr: qm->io_base + QM_RAS_CE_ENABLE);
1528 }
1529
1530 return ACC_ERR_RECOVERED;
1531}
1532
1533static int qm_get_mb_cmd(struct hisi_qm *qm, u64 *msg, u16 fun_num)
1534{
1535 struct qm_mailbox mailbox;
1536 int ret;
1537
1538 qm_mb_pre_init(mailbox: &mailbox, QM_MB_CMD_DST, base: 0, queue: fun_num, op: 0);
1539 mutex_lock(&qm->mailbox_lock);
1540 ret = qm_mb_nolock(qm, mailbox: &mailbox);
1541 if (ret)
1542 goto err_unlock;
1543
1544 *msg = readl(addr: qm->io_base + QM_MB_CMD_DATA_ADDR_L) |
1545 ((u64)readl(addr: qm->io_base + QM_MB_CMD_DATA_ADDR_H) << 32);
1546
1547err_unlock:
1548 mutex_unlock(lock: &qm->mailbox_lock);
1549 return ret;
1550}
1551
1552static void qm_clear_cmd_interrupt(struct hisi_qm *qm, u64 vf_mask)
1553{
1554 u32 val;
1555
1556 if (qm->fun_type == QM_HW_PF)
1557 writeq(val: vf_mask, addr: qm->io_base + QM_IFC_INT_SOURCE_P);
1558
1559 val = readl(addr: qm->io_base + QM_IFC_INT_SOURCE_V);
1560 val |= QM_IFC_INT_SOURCE_MASK;
1561 writel(val, addr: qm->io_base + QM_IFC_INT_SOURCE_V);
1562}
1563
1564static void qm_handle_vf_msg(struct hisi_qm *qm, u32 vf_id)
1565{
1566 struct device *dev = &qm->pdev->dev;
1567 enum qm_ifc_cmd cmd;
1568 int ret;
1569
1570 ret = qm->ops->get_ifc(qm, &cmd, NULL, vf_id);
1571 if (ret) {
1572 dev_err(dev, "failed to get command from VF(%u)!\n", vf_id);
1573 return;
1574 }
1575
1576 switch (cmd) {
1577 case QM_VF_PREPARE_FAIL:
1578 dev_err(dev, "failed to stop VF(%u)!\n", vf_id);
1579 break;
1580 case QM_VF_START_FAIL:
1581 dev_err(dev, "failed to start VF(%u)!\n", vf_id);
1582 break;
1583 case QM_VF_PREPARE_DONE:
1584 case QM_VF_START_DONE:
1585 break;
1586 default:
1587 dev_err(dev, "unsupported command(0x%x) sent by VF(%u)!\n", cmd, vf_id);
1588 break;
1589 }
1590}
1591
1592static int qm_wait_vf_prepare_finish(struct hisi_qm *qm)
1593{
1594 struct device *dev = &qm->pdev->dev;
1595 u32 vfs_num = qm->vfs_num;
1596 int cnt = 0;
1597 int ret = 0;
1598 u64 val;
1599 u32 i;
1600
1601 if (!qm->vfs_num || !test_bit(QM_SUPPORT_MB_COMMAND, &qm->caps))
1602 return 0;
1603
1604 while (true) {
1605 val = readq(addr: qm->io_base + QM_IFC_INT_SOURCE_P);
1606 /* All VFs send command to PF, break */
1607 if ((val & GENMASK(vfs_num, 1)) == GENMASK(vfs_num, 1))
1608 break;
1609
1610 if (++cnt > QM_MAX_PF_WAIT_COUNT) {
1611 ret = -EBUSY;
1612 break;
1613 }
1614
1615 msleep(QM_WAIT_DST_ACK);
1616 }
1617
1618 /* PF check VFs msg */
1619 for (i = 1; i <= vfs_num; i++) {
1620 if (val & BIT(i))
1621 qm_handle_vf_msg(qm, vf_id: i);
1622 else
1623 dev_err(dev, "VF(%u) not ping PF!\n", i);
1624 }
1625
1626 /* PF clear interrupt to ack VFs */
1627 qm_clear_cmd_interrupt(qm, vf_mask: val);
1628
1629 return ret;
1630}
1631
1632static void qm_trigger_vf_interrupt(struct hisi_qm *qm, u32 fun_num)
1633{
1634 u32 val;
1635
1636 val = readl(addr: qm->io_base + QM_IFC_INT_CFG);
1637 val &= ~QM_IFC_SEND_ALL_VFS;
1638 val |= fun_num;
1639 writel(val, addr: qm->io_base + QM_IFC_INT_CFG);
1640
1641 val = readl(addr: qm->io_base + QM_IFC_INT_SET_P);
1642 val |= QM_IFC_INT_SET_MASK;
1643 writel(val, addr: qm->io_base + QM_IFC_INT_SET_P);
1644}
1645
1646static void qm_trigger_pf_interrupt(struct hisi_qm *qm)
1647{
1648 u32 val;
1649
1650 val = readl(addr: qm->io_base + QM_IFC_INT_SET_V);
1651 val |= QM_IFC_INT_SET_MASK;
1652 writel(val, addr: qm->io_base + QM_IFC_INT_SET_V);
1653}
1654
1655static int qm_ping_single_vf(struct hisi_qm *qm, enum qm_ifc_cmd cmd, u32 data, u32 fun_num)
1656{
1657 struct device *dev = &qm->pdev->dev;
1658 int cnt = 0;
1659 u64 val;
1660 int ret;
1661
1662 ret = qm->ops->set_ifc_begin(qm, cmd, data, fun_num);
1663 if (ret) {
1664 dev_err(dev, "failed to send command to vf(%u)!\n", fun_num);
1665 goto err_unlock;
1666 }
1667
1668 qm_trigger_vf_interrupt(qm, fun_num);
1669 while (true) {
1670 msleep(QM_WAIT_DST_ACK);
1671 val = readq(addr: qm->io_base + QM_IFC_READY_STATUS);
1672 /* if VF respond, PF notifies VF successfully. */
1673 if (!(val & BIT(fun_num)))
1674 goto err_unlock;
1675
1676 if (++cnt > QM_MAX_PF_WAIT_COUNT) {
1677 dev_err(dev, "failed to get response from VF(%u)!\n", fun_num);
1678 ret = -ETIMEDOUT;
1679 break;
1680 }
1681 }
1682
1683err_unlock:
1684 qm->ops->set_ifc_end(qm);
1685 return ret;
1686}
1687
1688static int qm_ping_all_vfs(struct hisi_qm *qm, enum qm_ifc_cmd cmd)
1689{
1690 struct device *dev = &qm->pdev->dev;
1691 u32 vfs_num = qm->vfs_num;
1692 u64 val = 0;
1693 int cnt = 0;
1694 int ret;
1695 u32 i;
1696
1697 ret = qm->ops->set_ifc_begin(qm, cmd, 0, QM_MB_PING_ALL_VFS);
1698 if (ret) {
1699 dev_err(dev, "failed to send command(0x%x) to all vfs!\n", cmd);
1700 qm->ops->set_ifc_end(qm);
1701 return ret;
1702 }
1703
1704 qm_trigger_vf_interrupt(qm, QM_IFC_SEND_ALL_VFS);
1705 while (true) {
1706 msleep(QM_WAIT_DST_ACK);
1707 val = readq(addr: qm->io_base + QM_IFC_READY_STATUS);
1708 /* If all VFs acked, PF notifies VFs successfully. */
1709 if (!(val & GENMASK(vfs_num, 1))) {
1710 qm->ops->set_ifc_end(qm);
1711 return 0;
1712 }
1713
1714 if (++cnt > QM_MAX_PF_WAIT_COUNT)
1715 break;
1716 }
1717
1718 qm->ops->set_ifc_end(qm);
1719
1720 /* Check which vf respond timeout. */
1721 for (i = 1; i <= vfs_num; i++) {
1722 if (val & BIT(i))
1723 dev_err(dev, "failed to get response from VF(%u)!\n", i);
1724 }
1725
1726 return -ETIMEDOUT;
1727}
1728
1729static int qm_ping_pf(struct hisi_qm *qm, enum qm_ifc_cmd cmd)
1730{
1731 int cnt = 0;
1732 u32 val;
1733 int ret;
1734
1735 ret = qm->ops->set_ifc_begin(qm, cmd, 0, 0);
1736 if (ret) {
1737 dev_err(&qm->pdev->dev, "failed to send command(0x%x) to PF!\n", cmd);
1738 goto unlock;
1739 }
1740
1741 qm_trigger_pf_interrupt(qm);
1742 /* Waiting for PF response */
1743 while (true) {
1744 msleep(QM_WAIT_DST_ACK);
1745 val = readl(addr: qm->io_base + QM_IFC_INT_SET_V);
1746 if (!(val & QM_IFC_INT_STATUS_MASK))
1747 break;
1748
1749 if (++cnt > QM_MAX_VF_WAIT_COUNT) {
1750 ret = -ETIMEDOUT;
1751 break;
1752 }
1753 }
1754
1755unlock:
1756 qm->ops->set_ifc_end(qm);
1757
1758 return ret;
1759}
1760
1761static int qm_drain_qm(struct hisi_qm *qm)
1762{
1763 return hisi_qm_mb(qm, QM_MB_CMD_FLUSH_QM, 0, 0, 0);
1764}
1765
1766static int qm_stop_qp(struct hisi_qp *qp)
1767{
1768 return hisi_qm_mb(qp->qm, QM_MB_CMD_STOP_QP, 0, qp->qp_id, 0);
1769}
1770
1771static int qm_set_msi(struct hisi_qm *qm, bool set)
1772{
1773 struct pci_dev *pdev = qm->pdev;
1774
1775 if (set) {
1776 pci_write_config_dword(dev: pdev, where: pdev->msi_cap + PCI_MSI_MASK_64,
1777 val: 0);
1778 } else {
1779 pci_write_config_dword(dev: pdev, where: pdev->msi_cap + PCI_MSI_MASK_64,
1780 ACC_PEH_MSI_DISABLE);
1781 if (qm->err_status.is_qm_ecc_mbit ||
1782 qm->err_status.is_dev_ecc_mbit)
1783 return 0;
1784
1785 mdelay(1);
1786 if (readl(addr: qm->io_base + QM_PEH_DFX_INFO0))
1787 return -EFAULT;
1788 }
1789
1790 return 0;
1791}
1792
1793static void qm_wait_msi_finish(struct hisi_qm *qm)
1794{
1795 struct pci_dev *pdev = qm->pdev;
1796 u32 cmd = ~0;
1797 int cnt = 0;
1798 u32 val;
1799 int ret;
1800
1801 while (true) {
1802 pci_read_config_dword(dev: pdev, where: pdev->msi_cap +
1803 PCI_MSI_PENDING_64, val: &cmd);
1804 if (!cmd)
1805 break;
1806
1807 if (++cnt > MAX_WAIT_COUNTS) {
1808 pci_warn(pdev, "failed to empty MSI PENDING!\n");
1809 break;
1810 }
1811
1812 udelay(usec: 1);
1813 }
1814
1815 ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_DFX_INFO0,
1816 val, !(val & QM_PEH_DFX_MASK),
1817 POLL_PERIOD, POLL_TIMEOUT);
1818 if (ret)
1819 pci_warn(pdev, "failed to empty PEH MSI!\n");
1820
1821 ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_DFX_INFO1,
1822 val, !(val & QM_PEH_MSI_FINISH_MASK),
1823 POLL_PERIOD, POLL_TIMEOUT);
1824 if (ret)
1825 pci_warn(pdev, "failed to finish MSI operation!\n");
1826}
1827
1828static int qm_set_msi_v3(struct hisi_qm *qm, bool set)
1829{
1830 struct pci_dev *pdev = qm->pdev;
1831 int ret = -ETIMEDOUT;
1832 u32 cmd, i;
1833
1834 pci_read_config_dword(dev: pdev, where: pdev->msi_cap, val: &cmd);
1835 if (set)
1836 cmd |= QM_MSI_CAP_ENABLE;
1837 else
1838 cmd &= ~QM_MSI_CAP_ENABLE;
1839
1840 pci_write_config_dword(dev: pdev, where: pdev->msi_cap, val: cmd);
1841 if (set) {
1842 for (i = 0; i < MAX_WAIT_COUNTS; i++) {
1843 pci_read_config_dword(dev: pdev, where: pdev->msi_cap, val: &cmd);
1844 if (cmd & QM_MSI_CAP_ENABLE)
1845 return 0;
1846
1847 udelay(usec: 1);
1848 }
1849 } else {
1850 udelay(WAIT_PERIOD_US_MIN);
1851 qm_wait_msi_finish(qm);
1852 ret = 0;
1853 }
1854
1855 return ret;
1856}
1857
1858static int qm_set_ifc_begin_v3(struct hisi_qm *qm, enum qm_ifc_cmd cmd, u32 data, u32 fun_num)
1859{
1860 struct qm_mailbox mailbox;
1861 u64 msg;
1862
1863 msg = cmd | (u64)data << QM_IFC_DATA_SHIFT;
1864
1865 qm_mb_pre_init(mailbox: &mailbox, QM_MB_CMD_SRC, base: msg, queue: fun_num, op: 0);
1866 mutex_lock(&qm->mailbox_lock);
1867 return qm_mb_nolock(qm, mailbox: &mailbox);
1868}
1869
1870static void qm_set_ifc_end_v3(struct hisi_qm *qm)
1871{
1872 mutex_unlock(lock: &qm->mailbox_lock);
1873}
1874
1875static int qm_get_ifc_v3(struct hisi_qm *qm, enum qm_ifc_cmd *cmd, u32 *data, u32 fun_num)
1876{
1877 u64 msg;
1878 int ret;
1879
1880 ret = qm_get_mb_cmd(qm, msg: &msg, fun_num);
1881 if (ret)
1882 return ret;
1883
1884 *cmd = msg & QM_IFC_CMD_MASK;
1885
1886 if (data)
1887 *data = msg >> QM_IFC_DATA_SHIFT;
1888
1889 return 0;
1890}
1891
1892static int qm_set_ifc_begin_v4(struct hisi_qm *qm, enum qm_ifc_cmd cmd, u32 data, u32 fun_num)
1893{
1894 uintptr_t offset;
1895 u64 msg;
1896
1897 if (qm->fun_type == QM_HW_PF)
1898 offset = QM_PF2VF_PF_W;
1899 else
1900 offset = QM_VF2PF_VF_W;
1901
1902 msg = cmd | (u64)data << QM_IFC_DATA_SHIFT;
1903
1904 mutex_lock(&qm->ifc_lock);
1905 writeq(val: msg, addr: qm->io_base + offset);
1906
1907 return 0;
1908}
1909
1910static void qm_set_ifc_end_v4(struct hisi_qm *qm)
1911{
1912 mutex_unlock(lock: &qm->ifc_lock);
1913}
1914
1915static u64 qm_get_ifc_pf(struct hisi_qm *qm, u32 fun_num)
1916{
1917 uintptr_t offset;
1918
1919 offset = QM_VF2PF_PF_R + QM_VF2PF_REG_SIZE * fun_num;
1920
1921 return (u64)readl(addr: qm->io_base + offset);
1922}
1923
1924static u64 qm_get_ifc_vf(struct hisi_qm *qm)
1925{
1926 return readq(addr: qm->io_base + QM_PF2VF_VF_R);
1927}
1928
1929static int qm_get_ifc_v4(struct hisi_qm *qm, enum qm_ifc_cmd *cmd, u32 *data, u32 fun_num)
1930{
1931 u64 msg;
1932
1933 if (qm->fun_type == QM_HW_PF)
1934 msg = qm_get_ifc_pf(qm, fun_num);
1935 else
1936 msg = qm_get_ifc_vf(qm);
1937
1938 *cmd = msg & QM_IFC_CMD_MASK;
1939
1940 if (data)
1941 *data = msg >> QM_IFC_DATA_SHIFT;
1942
1943 return 0;
1944}
1945
1946static const struct hisi_qm_hw_ops qm_hw_ops_v1 = {
1947 .qm_db = qm_db_v1,
1948 .hw_error_init = qm_hw_error_init_v1,
1949 .set_msi = qm_set_msi,
1950};
1951
1952static const struct hisi_qm_hw_ops qm_hw_ops_v2 = {
1953 .get_vft = qm_get_vft_v2,
1954 .qm_db = qm_db_v2,
1955 .hw_error_init = qm_hw_error_init_v2,
1956 .hw_error_uninit = qm_hw_error_uninit_v2,
1957 .hw_error_handle = qm_hw_error_handle_v2,
1958 .set_msi = qm_set_msi,
1959};
1960
1961static const struct hisi_qm_hw_ops qm_hw_ops_v3 = {
1962 .get_vft = qm_get_vft_v2,
1963 .qm_db = qm_db_v2,
1964 .hw_error_init = qm_hw_error_init_v3,
1965 .hw_error_uninit = qm_hw_error_uninit_v3,
1966 .hw_error_handle = qm_hw_error_handle_v2,
1967 .set_msi = qm_set_msi_v3,
1968 .set_ifc_begin = qm_set_ifc_begin_v3,
1969 .set_ifc_end = qm_set_ifc_end_v3,
1970 .get_ifc = qm_get_ifc_v3,
1971};
1972
1973static const struct hisi_qm_hw_ops qm_hw_ops_v4 = {
1974 .get_vft = qm_get_vft_v2,
1975 .qm_db = qm_db_v2,
1976 .hw_error_init = qm_hw_error_init_v3,
1977 .hw_error_uninit = qm_hw_error_uninit_v3,
1978 .hw_error_handle = qm_hw_error_handle_v2,
1979 .set_msi = qm_set_msi_v3,
1980 .set_ifc_begin = qm_set_ifc_begin_v4,
1981 .set_ifc_end = qm_set_ifc_end_v4,
1982 .get_ifc = qm_get_ifc_v4,
1983};
1984
1985static void *qm_get_avail_sqe(struct hisi_qp *qp)
1986{
1987 struct hisi_qp_status *qp_status = &qp->qp_status;
1988 u16 sq_tail = qp_status->sq_tail;
1989
1990 if (unlikely(atomic_read(&qp->qp_status.used) == qp->sq_depth - 1))
1991 return NULL;
1992
1993 return qp->sqe + sq_tail * qp->qm->sqe_size;
1994}
1995
1996static void hisi_qm_unset_hw_reset(struct hisi_qp *qp)
1997{
1998 u64 *addr;
1999
2000 /* Use last 64 bits of DUS to reset status. */
2001 addr = (u64 *)(qp->qdma.va + qp->qdma.size) - QM_RESET_STOP_TX_OFFSET;
2002 *addr = 0;
2003}
2004
2005static struct hisi_qp *qm_create_qp_nolock(struct hisi_qm *qm, u8 alg_type)
2006{
2007 struct device *dev = &qm->pdev->dev;
2008 struct hisi_qp *qp;
2009 int qp_id;
2010
2011 if (atomic_read(v: &qm->status.flags) == QM_STOP) {
2012 dev_info_ratelimited(dev, "failed to create qp as qm is stop!\n");
2013 return ERR_PTR(error: -EPERM);
2014 }
2015
2016 if (qm->qp_in_used == qm->qp_num) {
2017 dev_info_ratelimited(dev, "All %u queues of QM are busy!\n",
2018 qm->qp_num);
2019 atomic64_inc(v: &qm->debug.dfx.create_qp_err_cnt);
2020 return ERR_PTR(error: -EBUSY);
2021 }
2022
2023 qp_id = idr_alloc_cyclic(&qm->qp_idr, NULL, start: 0, end: qm->qp_num, GFP_ATOMIC);
2024 if (qp_id < 0) {
2025 dev_info_ratelimited(dev, "All %u queues of QM are busy!\n",
2026 qm->qp_num);
2027 atomic64_inc(v: &qm->debug.dfx.create_qp_err_cnt);
2028 return ERR_PTR(error: -EBUSY);
2029 }
2030
2031 qp = &qm->qp_array[qp_id];
2032 hisi_qm_unset_hw_reset(qp);
2033 memset(qp->cqe, 0, sizeof(struct qm_cqe) * qp->cq_depth);
2034
2035 qp->event_cb = NULL;
2036 qp->req_cb = NULL;
2037 qp->qp_id = qp_id;
2038 qp->alg_type = alg_type;
2039 qp->is_in_kernel = true;
2040 qm->qp_in_used++;
2041
2042 return qp;
2043}
2044
2045/**
2046 * hisi_qm_create_qp() - Create a queue pair from qm.
2047 * @qm: The qm we create a qp from.
2048 * @alg_type: Accelerator specific algorithm type in sqc.
2049 *
2050 * Return created qp, negative error code if failed.
2051 */
2052static struct hisi_qp *hisi_qm_create_qp(struct hisi_qm *qm, u8 alg_type)
2053{
2054 struct hisi_qp *qp;
2055 int ret;
2056
2057 ret = qm_pm_get_sync(qm);
2058 if (ret)
2059 return ERR_PTR(error: ret);
2060
2061 down_write(sem: &qm->qps_lock);
2062 qp = qm_create_qp_nolock(qm, alg_type);
2063 up_write(sem: &qm->qps_lock);
2064
2065 if (IS_ERR(ptr: qp))
2066 qm_pm_put_sync(qm);
2067
2068 return qp;
2069}
2070
2071/**
2072 * hisi_qm_release_qp() - Release a qp back to its qm.
2073 * @qp: The qp we want to release.
2074 *
2075 * This function releases the resource of a qp.
2076 */
2077static void hisi_qm_release_qp(struct hisi_qp *qp)
2078{
2079 struct hisi_qm *qm = qp->qm;
2080
2081 down_write(sem: &qm->qps_lock);
2082
2083 qm->qp_in_used--;
2084 idr_remove(&qm->qp_idr, id: qp->qp_id);
2085
2086 up_write(sem: &qm->qps_lock);
2087
2088 qm_pm_put_sync(qm);
2089}
2090
2091static int qm_sq_ctx_cfg(struct hisi_qp *qp, int qp_id, u32 pasid)
2092{
2093 struct hisi_qm *qm = qp->qm;
2094 enum qm_hw_ver ver = qm->ver;
2095 struct qm_sqc sqc = {0};
2096
2097 if (ver == QM_HW_V1) {
2098 sqc.dw3 = cpu_to_le32(QM_MK_SQC_DW3_V1(0, 0, 0, qm->sqe_size));
2099 sqc.w8 = cpu_to_le16(qp->sq_depth - 1);
2100 } else {
2101 sqc.dw3 = cpu_to_le32(QM_MK_SQC_DW3_V2(qm->sqe_size, qp->sq_depth));
2102 sqc.w8 = 0; /* rand_qc */
2103 }
2104 sqc.w13 = cpu_to_le16(QM_MK_SQC_W13(0, 1, qp->alg_type));
2105 sqc.base_l = cpu_to_le32(lower_32_bits(qp->sqe_dma));
2106 sqc.base_h = cpu_to_le32(upper_32_bits(qp->sqe_dma));
2107 sqc.cq_num = cpu_to_le16(qp_id);
2108 sqc.pasid = cpu_to_le16(pasid);
2109
2110 if (ver >= QM_HW_V3 && qm->use_sva && !qp->is_in_kernel)
2111 sqc.w11 = cpu_to_le16(QM_QC_PASID_ENABLE <<
2112 QM_QC_PASID_ENABLE_SHIFT);
2113
2114 return qm_set_and_get_xqc(qm, QM_MB_CMD_SQC, xqc: &sqc, qp_id, op: 0);
2115}
2116
2117static int qm_cq_ctx_cfg(struct hisi_qp *qp, int qp_id, u32 pasid)
2118{
2119 struct hisi_qm *qm = qp->qm;
2120 enum qm_hw_ver ver = qm->ver;
2121 struct qm_cqc cqc = {0};
2122
2123 if (ver == QM_HW_V1) {
2124 cqc.dw3 = cpu_to_le32(QM_MK_CQC_DW3_V1(0, 0, 0, QM_QC_CQE_SIZE));
2125 cqc.w8 = cpu_to_le16(qp->cq_depth - 1);
2126 } else {
2127 cqc.dw3 = cpu_to_le32(QM_MK_CQC_DW3_V2(QM_QC_CQE_SIZE, qp->cq_depth));
2128 cqc.w8 = 0; /* rand_qc */
2129 }
2130 /*
2131 * Enable request finishing interrupts defaultly.
2132 * So, there will be some interrupts until disabling
2133 * this.
2134 */
2135 cqc.dw6 = cpu_to_le32(1 << QM_CQ_PHASE_SHIFT | 1 << QM_CQ_FLAG_SHIFT);
2136 cqc.base_l = cpu_to_le32(lower_32_bits(qp->cqe_dma));
2137 cqc.base_h = cpu_to_le32(upper_32_bits(qp->cqe_dma));
2138 cqc.pasid = cpu_to_le16(pasid);
2139
2140 if (ver >= QM_HW_V3 && qm->use_sva && !qp->is_in_kernel)
2141 cqc.w11 = cpu_to_le16(QM_QC_PASID_ENABLE);
2142
2143 return qm_set_and_get_xqc(qm, QM_MB_CMD_CQC, xqc: &cqc, qp_id, op: 0);
2144}
2145
2146static int qm_qp_ctx_cfg(struct hisi_qp *qp, int qp_id, u32 pasid)
2147{
2148 int ret;
2149
2150 qm_init_qp_status(qp);
2151
2152 ret = qm_sq_ctx_cfg(qp, qp_id, pasid);
2153 if (ret)
2154 return ret;
2155
2156 return qm_cq_ctx_cfg(qp, qp_id, pasid);
2157}
2158
2159static int qm_start_qp_nolock(struct hisi_qp *qp, unsigned long arg)
2160{
2161 struct hisi_qm *qm = qp->qm;
2162 struct device *dev = &qm->pdev->dev;
2163 int qp_id = qp->qp_id;
2164 u32 pasid = arg;
2165 int ret;
2166
2167 if (atomic_read(v: &qm->status.flags) == QM_STOP) {
2168 dev_info_ratelimited(dev, "failed to start qp as qm is stop!\n");
2169 return -EPERM;
2170 }
2171
2172 ret = qm_qp_ctx_cfg(qp, qp_id, pasid);
2173 if (ret)
2174 return ret;
2175
2176 atomic_set(v: &qp->qp_status.flags, i: QP_START);
2177 dev_dbg(dev, "queue %d started\n", qp_id);
2178
2179 return 0;
2180}
2181
2182/**
2183 * hisi_qm_start_qp() - Start a qp into running.
2184 * @qp: The qp we want to start to run.
2185 * @arg: Accelerator specific argument.
2186 *
2187 * After this function, qp can receive request from user. Return 0 if
2188 * successful, negative error code if failed.
2189 */
2190int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg)
2191{
2192 struct hisi_qm *qm = qp->qm;
2193 int ret;
2194
2195 down_write(sem: &qm->qps_lock);
2196 ret = qm_start_qp_nolock(qp, arg);
2197 up_write(sem: &qm->qps_lock);
2198
2199 return ret;
2200}
2201EXPORT_SYMBOL_GPL(hisi_qm_start_qp);
2202
2203/**
2204 * qp_stop_fail_cb() - call request cb.
2205 * @qp: stopped failed qp.
2206 *
2207 * Callback function should be called whether task completed or not.
2208 */
2209static void qp_stop_fail_cb(struct hisi_qp *qp)
2210{
2211 int qp_used = atomic_read(v: &qp->qp_status.used);
2212 u16 cur_tail = qp->qp_status.sq_tail;
2213 u16 sq_depth = qp->sq_depth;
2214 u16 cur_head = (cur_tail + sq_depth - qp_used) % sq_depth;
2215 struct hisi_qm *qm = qp->qm;
2216 u16 pos;
2217 int i;
2218
2219 for (i = 0; i < qp_used; i++) {
2220 pos = (i + cur_head) % sq_depth;
2221 qp->req_cb(qp, qp->sqe + (u32)(qm->sqe_size * pos));
2222 atomic_dec(v: &qp->qp_status.used);
2223 }
2224}
2225
2226static int qm_wait_qp_empty(struct hisi_qm *qm, u32 *state, u32 qp_id)
2227{
2228 struct device *dev = &qm->pdev->dev;
2229 struct qm_sqc sqc;
2230 struct qm_cqc cqc;
2231 int ret, i = 0;
2232
2233 while (++i) {
2234 ret = qm_set_and_get_xqc(qm, QM_MB_CMD_SQC, xqc: &sqc, qp_id, op: 1);
2235 if (ret) {
2236 dev_err_ratelimited(dev, "Failed to dump sqc!\n");
2237 *state = QM_DUMP_SQC_FAIL;
2238 return ret;
2239 }
2240
2241 ret = qm_set_and_get_xqc(qm, QM_MB_CMD_CQC, xqc: &cqc, qp_id, op: 1);
2242 if (ret) {
2243 dev_err_ratelimited(dev, "Failed to dump cqc!\n");
2244 *state = QM_DUMP_CQC_FAIL;
2245 return ret;
2246 }
2247
2248 if ((sqc.tail == cqc.tail) &&
2249 (QM_SQ_TAIL_IDX(sqc) == QM_CQ_TAIL_IDX(cqc)))
2250 break;
2251
2252 if (i == MAX_WAIT_COUNTS) {
2253 dev_err(dev, "Fail to empty queue %u!\n", qp_id);
2254 *state = QM_STOP_QUEUE_FAIL;
2255 return -ETIMEDOUT;
2256 }
2257
2258 usleep_range(WAIT_PERIOD_US_MIN, WAIT_PERIOD_US_MAX);
2259 }
2260
2261 return 0;
2262}
2263
2264/**
2265 * qm_drain_qp() - Drain a qp.
2266 * @qp: The qp we want to drain.
2267 *
2268 * If the device does not support stopping queue by sending mailbox,
2269 * determine whether the queue is cleared by judging the tail pointers of
2270 * sq and cq.
2271 */
2272static int qm_drain_qp(struct hisi_qp *qp)
2273{
2274 struct hisi_qm *qm = qp->qm;
2275 u32 state = 0;
2276 int ret;
2277
2278 /* No need to judge if master OOO is blocked. */
2279 if (qm_check_dev_error(qm))
2280 return 0;
2281
2282 /* HW V3 supports drain qp by device */
2283 if (test_bit(QM_SUPPORT_STOP_QP, &qm->caps)) {
2284 ret = qm_stop_qp(qp);
2285 if (ret) {
2286 dev_err(&qm->pdev->dev, "Failed to stop qp!\n");
2287 state = QM_STOP_QUEUE_FAIL;
2288 goto set_dev_state;
2289 }
2290 return ret;
2291 }
2292
2293 ret = qm_wait_qp_empty(qm, state: &state, qp_id: qp->qp_id);
2294 if (ret)
2295 goto set_dev_state;
2296
2297 return 0;
2298
2299set_dev_state:
2300 if (qm->debug.dev_dfx.dev_timeout)
2301 qm->debug.dev_dfx.dev_state = state;
2302
2303 return ret;
2304}
2305
2306static void qm_stop_qp_nolock(struct hisi_qp *qp)
2307{
2308 struct hisi_qm *qm = qp->qm;
2309 struct device *dev = &qm->pdev->dev;
2310 int ret;
2311
2312 /*
2313 * It is allowed to stop and release qp when reset, If the qp is
2314 * stopped when reset but still want to be released then, the
2315 * is_resetting flag should be set negative so that this qp will not
2316 * be restarted after reset.
2317 */
2318 if (atomic_read(v: &qp->qp_status.flags) != QP_START) {
2319 qp->is_resetting = false;
2320 return;
2321 }
2322
2323 atomic_set(v: &qp->qp_status.flags, i: QP_STOP);
2324
2325 /* V3 supports direct stop function when FLR prepare */
2326 if (qm->ver < QM_HW_V3 || qm->status.stop_reason == QM_NORMAL) {
2327 ret = qm_drain_qp(qp);
2328 if (ret)
2329 dev_err(dev, "Failed to drain out data for stopping qp(%u)!\n", qp->qp_id);
2330 }
2331
2332 flush_workqueue(qm->wq);
2333 if (unlikely(qp->is_resetting && atomic_read(&qp->qp_status.used)))
2334 qp_stop_fail_cb(qp);
2335
2336 dev_dbg(dev, "stop queue %u!", qp->qp_id);
2337}
2338
2339/**
2340 * hisi_qm_stop_qp() - Stop a qp in qm.
2341 * @qp: The qp we want to stop.
2342 *
2343 * This function is reverse of hisi_qm_start_qp.
2344 */
2345void hisi_qm_stop_qp(struct hisi_qp *qp)
2346{
2347 down_write(sem: &qp->qm->qps_lock);
2348 qm_stop_qp_nolock(qp);
2349 up_write(sem: &qp->qm->qps_lock);
2350}
2351EXPORT_SYMBOL_GPL(hisi_qm_stop_qp);
2352
2353/**
2354 * hisi_qp_send() - Queue up a task in the hardware queue.
2355 * @qp: The qp in which to put the message.
2356 * @msg: The message.
2357 *
2358 * This function will return -EBUSY if qp is currently full, and -EAGAIN
2359 * if qp related qm is resetting.
2360 *
2361 * Note: This function may run with qm_irq_thread and ACC reset at same time.
2362 * It has no race with qm_irq_thread. However, during hisi_qp_send, ACC
2363 * reset may happen, we have no lock here considering performance. This
2364 * causes current qm_db sending fail or can not receive sended sqe. QM
2365 * sync/async receive function should handle the error sqe. ACC reset
2366 * done function should clear used sqe to 0.
2367 */
2368int hisi_qp_send(struct hisi_qp *qp, const void *msg)
2369{
2370 struct hisi_qp_status *qp_status = &qp->qp_status;
2371 u16 sq_tail = qp_status->sq_tail;
2372 u16 sq_tail_next = (sq_tail + 1) % qp->sq_depth;
2373 void *sqe = qm_get_avail_sqe(qp);
2374
2375 if (unlikely(atomic_read(&qp->qp_status.flags) == QP_STOP ||
2376 atomic_read(&qp->qm->status.flags) == QM_STOP ||
2377 qp->is_resetting)) {
2378 dev_info_ratelimited(&qp->qm->pdev->dev, "QP is stopped or resetting\n");
2379 return -EAGAIN;
2380 }
2381
2382 if (!sqe)
2383 return -EBUSY;
2384
2385 memcpy(sqe, msg, qp->qm->sqe_size);
2386
2387 qm_db(qm: qp->qm, qn: qp->qp_id, QM_DOORBELL_CMD_SQ, index: sq_tail_next, priority: 0);
2388 atomic_inc(v: &qp->qp_status.used);
2389 qp_status->sq_tail = sq_tail_next;
2390
2391 return 0;
2392}
2393EXPORT_SYMBOL_GPL(hisi_qp_send);
2394
2395static void hisi_qm_cache_wb(struct hisi_qm *qm)
2396{
2397 unsigned int val;
2398
2399 if (qm->ver == QM_HW_V1)
2400 return;
2401
2402 writel(val: 0x1, addr: qm->io_base + QM_CACHE_WB_START);
2403 if (readl_relaxed_poll_timeout(qm->io_base + QM_CACHE_WB_DONE,
2404 val, val & BIT(0), POLL_PERIOD,
2405 POLL_TIMEOUT))
2406 dev_err(&qm->pdev->dev, "QM writeback sqc cache fail!\n");
2407}
2408
2409static void qm_qp_event_notifier(struct hisi_qp *qp)
2410{
2411 wake_up_interruptible(&qp->uacce_q->wait);
2412}
2413
2414 /* This function returns free number of qp in qm. */
2415static int hisi_qm_get_available_instances(struct uacce_device *uacce)
2416{
2417 struct hisi_qm *qm = uacce->priv;
2418 int ret;
2419
2420 down_read(sem: &qm->qps_lock);
2421 ret = qm->qp_num - qm->qp_in_used;
2422 up_read(sem: &qm->qps_lock);
2423
2424 return ret;
2425}
2426
2427static void hisi_qm_set_hw_reset(struct hisi_qm *qm, int offset)
2428{
2429 int i;
2430
2431 for (i = 0; i < qm->qp_num; i++)
2432 qm_set_qp_disable(qp: &qm->qp_array[i], offset);
2433}
2434
2435static int hisi_qm_uacce_get_queue(struct uacce_device *uacce,
2436 unsigned long arg,
2437 struct uacce_queue *q)
2438{
2439 struct hisi_qm *qm = uacce->priv;
2440 struct hisi_qp *qp;
2441 u8 alg_type = 0;
2442
2443 qp = hisi_qm_create_qp(qm, alg_type);
2444 if (IS_ERR(ptr: qp))
2445 return PTR_ERR(ptr: qp);
2446
2447 q->priv = qp;
2448 q->uacce = uacce;
2449 qp->uacce_q = q;
2450 qp->event_cb = qm_qp_event_notifier;
2451 qp->pasid = arg;
2452 qp->is_in_kernel = false;
2453
2454 return 0;
2455}
2456
2457static void hisi_qm_uacce_put_queue(struct uacce_queue *q)
2458{
2459 struct hisi_qp *qp = q->priv;
2460
2461 hisi_qm_release_qp(qp);
2462}
2463
2464/* map sq/cq/doorbell to user space */
2465static int hisi_qm_uacce_mmap(struct uacce_queue *q,
2466 struct vm_area_struct *vma,
2467 struct uacce_qfile_region *qfr)
2468{
2469 struct hisi_qp *qp = q->priv;
2470 struct hisi_qm *qm = qp->qm;
2471 resource_size_t phys_base = qm->db_phys_base +
2472 qp->qp_id * qm->db_interval;
2473 size_t sz = vma->vm_end - vma->vm_start;
2474 struct pci_dev *pdev = qm->pdev;
2475 struct device *dev = &pdev->dev;
2476 unsigned long vm_pgoff;
2477 int ret;
2478
2479 switch (qfr->type) {
2480 case UACCE_QFRT_MMIO:
2481 if (qm->ver == QM_HW_V1) {
2482 if (sz > PAGE_SIZE * QM_DOORBELL_PAGE_NR)
2483 return -EINVAL;
2484 } else if (!test_bit(QM_SUPPORT_DB_ISOLATION, &qm->caps)) {
2485 if (sz > PAGE_SIZE * (QM_DOORBELL_PAGE_NR +
2486 QM_DOORBELL_SQ_CQ_BASE_V2 / PAGE_SIZE))
2487 return -EINVAL;
2488 } else {
2489 if (sz > qm->db_interval)
2490 return -EINVAL;
2491 }
2492
2493 vm_flags_set(vma, VM_IO);
2494
2495 return remap_pfn_range(vma, addr: vma->vm_start,
2496 pfn: phys_base >> PAGE_SHIFT,
2497 size: sz, pgprot_noncached(vma->vm_page_prot));
2498 case UACCE_QFRT_DUS:
2499 if (sz != qp->qdma.size)
2500 return -EINVAL;
2501
2502 /*
2503 * dma_mmap_coherent() requires vm_pgoff as 0
2504 * restore vm_pfoff to initial value for mmap()
2505 */
2506 vm_pgoff = vma->vm_pgoff;
2507 vma->vm_pgoff = 0;
2508 ret = dma_mmap_coherent(dev, vma, qp->qdma.va,
2509 qp->qdma.dma, sz);
2510 vma->vm_pgoff = vm_pgoff;
2511 return ret;
2512
2513 default:
2514 return -EINVAL;
2515 }
2516}
2517
2518static int hisi_qm_uacce_start_queue(struct uacce_queue *q)
2519{
2520 struct hisi_qp *qp = q->priv;
2521
2522 return hisi_qm_start_qp(qp, qp->pasid);
2523}
2524
2525static void hisi_qm_uacce_stop_queue(struct uacce_queue *q)
2526{
2527 struct hisi_qp *qp = q->priv;
2528 struct hisi_qm *qm = qp->qm;
2529 struct qm_dev_dfx *dev_dfx = &qm->debug.dev_dfx;
2530 u32 i = 0;
2531
2532 hisi_qm_stop_qp(qp);
2533
2534 if (!dev_dfx->dev_timeout || !dev_dfx->dev_state)
2535 return;
2536
2537 /*
2538 * After the queue fails to be stopped,
2539 * wait for a period of time before releasing the queue.
2540 */
2541 while (++i) {
2542 msleep(WAIT_PERIOD);
2543
2544 /* Since dev_timeout maybe modified, check i >= dev_timeout */
2545 if (i >= dev_dfx->dev_timeout) {
2546 dev_err(&qm->pdev->dev, "Stop q %u timeout, state %u\n",
2547 qp->qp_id, dev_dfx->dev_state);
2548 dev_dfx->dev_state = QM_FINISH_WAIT;
2549 break;
2550 }
2551 }
2552}
2553
2554static int hisi_qm_is_q_updated(struct uacce_queue *q)
2555{
2556 struct hisi_qp *qp = q->priv;
2557 struct qm_cqe *cqe = qp->cqe + qp->qp_status.cq_head;
2558 int updated = 0;
2559
2560 while (QM_CQE_PHASE(cqe) == qp->qp_status.cqc_phase) {
2561 /* make sure to read data from memory */
2562 dma_rmb();
2563 qm_cq_head_update(qp);
2564 cqe = qp->cqe + qp->qp_status.cq_head;
2565 updated = 1;
2566 }
2567
2568 return updated;
2569}
2570
2571static void qm_set_sqctype(struct uacce_queue *q, u16 type)
2572{
2573 struct hisi_qm *qm = q->uacce->priv;
2574 struct hisi_qp *qp = q->priv;
2575
2576 down_write(sem: &qm->qps_lock);
2577 qp->alg_type = type;
2578 up_write(sem: &qm->qps_lock);
2579}
2580
2581static long hisi_qm_uacce_ioctl(struct uacce_queue *q, unsigned int cmd,
2582 unsigned long arg)
2583{
2584 struct hisi_qp *qp = q->priv;
2585 struct hisi_qp_info qp_info;
2586 struct hisi_qp_ctx qp_ctx;
2587
2588 if (cmd == UACCE_CMD_QM_SET_QP_CTX) {
2589 if (copy_from_user(to: &qp_ctx, from: (void __user *)arg,
2590 n: sizeof(struct hisi_qp_ctx)))
2591 return -EFAULT;
2592
2593 if (qp_ctx.qc_type > QM_MAX_QC_TYPE)
2594 return -EINVAL;
2595
2596 qm_set_sqctype(q, type: qp_ctx.qc_type);
2597 qp_ctx.id = qp->qp_id;
2598
2599 if (copy_to_user(to: (void __user *)arg, from: &qp_ctx,
2600 n: sizeof(struct hisi_qp_ctx)))
2601 return -EFAULT;
2602
2603 return 0;
2604 } else if (cmd == UACCE_CMD_QM_SET_QP_INFO) {
2605 if (copy_from_user(to: &qp_info, from: (void __user *)arg,
2606 n: sizeof(struct hisi_qp_info)))
2607 return -EFAULT;
2608
2609 qp_info.sqe_size = qp->qm->sqe_size;
2610 qp_info.sq_depth = qp->sq_depth;
2611 qp_info.cq_depth = qp->cq_depth;
2612
2613 if (copy_to_user(to: (void __user *)arg, from: &qp_info,
2614 n: sizeof(struct hisi_qp_info)))
2615 return -EFAULT;
2616
2617 return 0;
2618 }
2619
2620 return -EINVAL;
2621}
2622
2623/**
2624 * qm_hw_err_isolate() - Try to set the isolation status of the uacce device
2625 * according to user's configuration of error threshold.
2626 * @qm: the uacce device
2627 */
2628static int qm_hw_err_isolate(struct hisi_qm *qm)
2629{
2630 struct qm_hw_err *err, *tmp, *hw_err;
2631 struct qm_err_isolate *isolate;
2632 u32 count = 0;
2633
2634 isolate = &qm->isolate_data;
2635
2636#define SECONDS_PER_HOUR 3600
2637
2638 /* All the hw errs are processed by PF driver */
2639 if (qm->uacce->is_vf || isolate->is_isolate || !isolate->err_threshold)
2640 return 0;
2641
2642 hw_err = kzalloc(sizeof(*hw_err), GFP_KERNEL);
2643 if (!hw_err)
2644 return -ENOMEM;
2645
2646 /*
2647 * Time-stamp every slot AER error. Then check the AER error log when the
2648 * next device AER error occurred. if the device slot AER error count exceeds
2649 * the setting error threshold in one hour, the isolated state will be set
2650 * to true. And the AER error logs that exceed one hour will be cleared.
2651 */
2652 mutex_lock(&isolate->isolate_lock);
2653 hw_err->timestamp = jiffies;
2654 list_for_each_entry_safe(err, tmp, &isolate->qm_hw_errs, list) {
2655 if ((hw_err->timestamp - err->timestamp) / HZ >
2656 SECONDS_PER_HOUR) {
2657 list_del(entry: &err->list);
2658 kfree(objp: err);
2659 } else {
2660 count++;
2661 }
2662 }
2663 list_add(new: &hw_err->list, head: &isolate->qm_hw_errs);
2664
2665 if (count >= isolate->err_threshold)
2666 isolate->is_isolate = true;
2667 mutex_unlock(lock: &isolate->isolate_lock);
2668
2669 return 0;
2670}
2671
2672static void qm_hw_err_destroy(struct hisi_qm *qm)
2673{
2674 struct qm_hw_err *err, *tmp;
2675
2676 list_for_each_entry_safe(err, tmp, &qm->isolate_data.qm_hw_errs, list) {
2677 list_del(entry: &err->list);
2678 kfree(objp: err);
2679 }
2680}
2681
2682static enum uacce_dev_state hisi_qm_get_isolate_state(struct uacce_device *uacce)
2683{
2684 struct hisi_qm *qm = uacce->priv;
2685 struct hisi_qm *pf_qm;
2686
2687 if (uacce->is_vf)
2688 pf_qm = pci_get_drvdata(pdev: pci_physfn(dev: qm->pdev));
2689 else
2690 pf_qm = qm;
2691
2692 return pf_qm->isolate_data.is_isolate ?
2693 UACCE_DEV_ISOLATE : UACCE_DEV_NORMAL;
2694}
2695
2696static int hisi_qm_isolate_threshold_write(struct uacce_device *uacce, u32 num)
2697{
2698 struct hisi_qm *qm = uacce->priv;
2699
2700 /* Must be set by PF */
2701 if (uacce->is_vf)
2702 return -EPERM;
2703
2704 if (qm->isolate_data.is_isolate)
2705 return -EPERM;
2706
2707 mutex_lock(&qm->isolate_data.isolate_lock);
2708 qm->isolate_data.err_threshold = num;
2709
2710 /* After the policy is updated, need to reset the hardware err list */
2711 qm_hw_err_destroy(qm);
2712 mutex_unlock(lock: &qm->isolate_data.isolate_lock);
2713
2714 return 0;
2715}
2716
2717static u32 hisi_qm_isolate_threshold_read(struct uacce_device *uacce)
2718{
2719 struct hisi_qm *qm = uacce->priv;
2720 struct hisi_qm *pf_qm;
2721
2722 if (uacce->is_vf) {
2723 pf_qm = pci_get_drvdata(pdev: pci_physfn(dev: qm->pdev));
2724 return pf_qm->isolate_data.err_threshold;
2725 }
2726
2727 return qm->isolate_data.err_threshold;
2728}
2729
2730static const struct uacce_ops uacce_qm_ops = {
2731 .get_available_instances = hisi_qm_get_available_instances,
2732 .get_queue = hisi_qm_uacce_get_queue,
2733 .put_queue = hisi_qm_uacce_put_queue,
2734 .start_queue = hisi_qm_uacce_start_queue,
2735 .stop_queue = hisi_qm_uacce_stop_queue,
2736 .mmap = hisi_qm_uacce_mmap,
2737 .ioctl = hisi_qm_uacce_ioctl,
2738 .is_q_updated = hisi_qm_is_q_updated,
2739 .get_isolate_state = hisi_qm_get_isolate_state,
2740 .isolate_err_threshold_write = hisi_qm_isolate_threshold_write,
2741 .isolate_err_threshold_read = hisi_qm_isolate_threshold_read,
2742};
2743
2744static void qm_remove_uacce(struct hisi_qm *qm)
2745{
2746 struct uacce_device *uacce = qm->uacce;
2747
2748 if (qm->use_sva) {
2749 mutex_lock(&qm->isolate_data.isolate_lock);
2750 qm_hw_err_destroy(qm);
2751 mutex_unlock(lock: &qm->isolate_data.isolate_lock);
2752
2753 uacce_remove(uacce);
2754 qm->uacce = NULL;
2755 }
2756}
2757
2758static void qm_uacce_api_ver_init(struct hisi_qm *qm)
2759{
2760 struct uacce_device *uacce = qm->uacce;
2761
2762 switch (qm->ver) {
2763 case QM_HW_V1:
2764 uacce->api_ver = HISI_QM_API_VER_BASE;
2765 break;
2766 case QM_HW_V2:
2767 uacce->api_ver = HISI_QM_API_VER2_BASE;
2768 break;
2769 case QM_HW_V3:
2770 case QM_HW_V4:
2771 uacce->api_ver = HISI_QM_API_VER3_BASE;
2772 break;
2773 default:
2774 uacce->api_ver = HISI_QM_API_VER5_BASE;
2775 break;
2776 }
2777}
2778
2779static int qm_alloc_uacce(struct hisi_qm *qm)
2780{
2781 struct pci_dev *pdev = qm->pdev;
2782 struct uacce_device *uacce;
2783 unsigned long mmio_page_nr;
2784 unsigned long dus_page_nr;
2785 u16 sq_depth, cq_depth;
2786 struct uacce_interface interface = {
2787 .flags = UACCE_DEV_SVA,
2788 .ops = &uacce_qm_ops,
2789 };
2790 int ret;
2791
2792 ret = strscpy(interface.name, dev_driver_string(&pdev->dev),
2793 sizeof(interface.name));
2794 if (ret < 0)
2795 return -ENAMETOOLONG;
2796
2797 uacce = uacce_alloc(parent: &pdev->dev, interface: &interface);
2798 if (IS_ERR(ptr: uacce))
2799 return PTR_ERR(ptr: uacce);
2800
2801 if (uacce->flags & UACCE_DEV_SVA) {
2802 qm->use_sva = true;
2803 } else {
2804 /* only consider sva case */
2805 qm_remove_uacce(qm);
2806 return -EINVAL;
2807 }
2808
2809 uacce->is_vf = pdev->is_virtfn;
2810 uacce->priv = qm;
2811
2812 if (qm->ver == QM_HW_V1)
2813 mmio_page_nr = QM_DOORBELL_PAGE_NR;
2814 else if (!test_bit(QM_SUPPORT_DB_ISOLATION, &qm->caps))
2815 mmio_page_nr = QM_DOORBELL_PAGE_NR +
2816 QM_DOORBELL_SQ_CQ_BASE_V2 / PAGE_SIZE;
2817 else
2818 mmio_page_nr = qm->db_interval / PAGE_SIZE;
2819
2820 qm_get_xqc_depth(qm, low_bits: &sq_depth, high_bits: &cq_depth, type: QM_QP_DEPTH_CAP);
2821
2822 /* Add one more page for device or qp status */
2823 dus_page_nr = (PAGE_SIZE - 1 + qm->sqe_size * sq_depth +
2824 sizeof(struct qm_cqe) * cq_depth + PAGE_SIZE) >>
2825 PAGE_SHIFT;
2826
2827 uacce->qf_pg_num[UACCE_QFRT_MMIO] = mmio_page_nr;
2828 uacce->qf_pg_num[UACCE_QFRT_DUS] = dus_page_nr;
2829
2830 qm->uacce = uacce;
2831 qm_uacce_api_ver_init(qm);
2832 INIT_LIST_HEAD(list: &qm->isolate_data.qm_hw_errs);
2833 mutex_init(&qm->isolate_data.isolate_lock);
2834
2835 return 0;
2836}
2837
2838/**
2839 * qm_frozen() - Try to froze QM to cut continuous queue request. If
2840 * there is user on the QM, return failure without doing anything.
2841 * @qm: The qm needed to be fronzen.
2842 *
2843 * This function frozes QM, then we can do SRIOV disabling.
2844 */
2845static int qm_frozen(struct hisi_qm *qm)
2846{
2847 if (test_bit(QM_DRIVER_REMOVING, &qm->misc_ctl))
2848 return 0;
2849
2850 down_write(sem: &qm->qps_lock);
2851
2852 if (!qm->qp_in_used) {
2853 qm->qp_in_used = qm->qp_num;
2854 up_write(sem: &qm->qps_lock);
2855 set_bit(nr: QM_DRIVER_REMOVING, addr: &qm->misc_ctl);
2856 return 0;
2857 }
2858
2859 up_write(sem: &qm->qps_lock);
2860
2861 return -EBUSY;
2862}
2863
2864static int qm_try_frozen_vfs(struct pci_dev *pdev,
2865 struct hisi_qm_list *qm_list)
2866{
2867 struct hisi_qm *qm, *vf_qm;
2868 struct pci_dev *dev;
2869 int ret = 0;
2870
2871 if (!qm_list || !pdev)
2872 return -EINVAL;
2873
2874 /* Try to frozen all the VFs as disable SRIOV */
2875 mutex_lock(&qm_list->lock);
2876 list_for_each_entry(qm, &qm_list->list, list) {
2877 dev = qm->pdev;
2878 if (dev == pdev)
2879 continue;
2880 if (pci_physfn(dev) == pdev) {
2881 vf_qm = pci_get_drvdata(pdev: dev);
2882 ret = qm_frozen(qm: vf_qm);
2883 if (ret)
2884 goto frozen_fail;
2885 }
2886 }
2887
2888frozen_fail:
2889 mutex_unlock(lock: &qm_list->lock);
2890
2891 return ret;
2892}
2893
2894/**
2895 * hisi_qm_wait_task_finish() - Wait until the task is finished
2896 * when removing the driver.
2897 * @qm: The qm needed to wait for the task to finish.
2898 * @qm_list: The list of all available devices.
2899 */
2900void hisi_qm_wait_task_finish(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
2901{
2902 while (qm_frozen(qm) ||
2903 ((qm->fun_type == QM_HW_PF) &&
2904 qm_try_frozen_vfs(pdev: qm->pdev, qm_list))) {
2905 msleep(WAIT_PERIOD);
2906 }
2907
2908 while (test_bit(QM_RST_SCHED, &qm->misc_ctl) ||
2909 test_bit(QM_RESETTING, &qm->misc_ctl))
2910 msleep(WAIT_PERIOD);
2911
2912 if (test_bit(QM_SUPPORT_MB_COMMAND, &qm->caps))
2913 flush_work(work: &qm->cmd_process);
2914
2915 udelay(REMOVE_WAIT_DELAY);
2916}
2917EXPORT_SYMBOL_GPL(hisi_qm_wait_task_finish);
2918
2919static void hisi_qp_memory_uninit(struct hisi_qm *qm, int num)
2920{
2921 struct device *dev = &qm->pdev->dev;
2922 struct qm_dma *qdma;
2923 int i;
2924
2925 for (i = num - 1; i >= 0; i--) {
2926 qdma = &qm->qp_array[i].qdma;
2927 dma_free_coherent(dev, size: qdma->size, cpu_addr: qdma->va, dma_handle: qdma->dma);
2928 kfree(objp: qm->poll_data[i].qp_finish_id);
2929 }
2930
2931 kfree(objp: qm->poll_data);
2932 kfree(objp: qm->qp_array);
2933}
2934
2935static int hisi_qp_memory_init(struct hisi_qm *qm, size_t dma_size, int id,
2936 u16 sq_depth, u16 cq_depth)
2937{
2938 struct device *dev = &qm->pdev->dev;
2939 size_t off = qm->sqe_size * sq_depth;
2940 struct hisi_qp *qp;
2941 int ret = -ENOMEM;
2942
2943 qm->poll_data[id].qp_finish_id = kcalloc(qm->qp_num, sizeof(u16),
2944 GFP_KERNEL);
2945 if (!qm->poll_data[id].qp_finish_id)
2946 return -ENOMEM;
2947
2948 qp = &qm->qp_array[id];
2949 qp->qdma.va = dma_alloc_coherent(dev, size: dma_size, dma_handle: &qp->qdma.dma,
2950 GFP_KERNEL);
2951 if (!qp->qdma.va)
2952 goto err_free_qp_finish_id;
2953
2954 qp->sqe = qp->qdma.va;
2955 qp->sqe_dma = qp->qdma.dma;
2956 qp->cqe = qp->qdma.va + off;
2957 qp->cqe_dma = qp->qdma.dma + off;
2958 qp->qdma.size = dma_size;
2959 qp->sq_depth = sq_depth;
2960 qp->cq_depth = cq_depth;
2961 qp->qm = qm;
2962 qp->qp_id = id;
2963
2964 return 0;
2965
2966err_free_qp_finish_id:
2967 kfree(objp: qm->poll_data[id].qp_finish_id);
2968 return ret;
2969}
2970
2971static void hisi_qm_pre_init(struct hisi_qm *qm)
2972{
2973 struct pci_dev *pdev = qm->pdev;
2974
2975 if (qm->ver == QM_HW_V1)
2976 qm->ops = &qm_hw_ops_v1;
2977 else if (qm->ver == QM_HW_V2)
2978 qm->ops = &qm_hw_ops_v2;
2979 else if (qm->ver == QM_HW_V3)
2980 qm->ops = &qm_hw_ops_v3;
2981 else
2982 qm->ops = &qm_hw_ops_v4;
2983
2984 pci_set_drvdata(pdev, data: qm);
2985 mutex_init(&qm->mailbox_lock);
2986 mutex_init(&qm->ifc_lock);
2987 init_rwsem(&qm->qps_lock);
2988 qm->qp_in_used = 0;
2989 if (test_bit(QM_SUPPORT_RPM, &qm->caps)) {
2990 if (!acpi_device_power_manageable(ACPI_COMPANION(&pdev->dev)))
2991 dev_info(&pdev->dev, "_PS0 and _PR0 are not defined");
2992 }
2993}
2994
2995static void qm_cmd_uninit(struct hisi_qm *qm)
2996{
2997 u32 val;
2998
2999 if (!test_bit(QM_SUPPORT_MB_COMMAND, &qm->caps))
3000 return;
3001
3002 val = readl(addr: qm->io_base + QM_IFC_INT_MASK);
3003 val |= QM_IFC_INT_DISABLE;
3004 writel(val, addr: qm->io_base + QM_IFC_INT_MASK);
3005}
3006
3007static void qm_cmd_init(struct hisi_qm *qm)
3008{
3009 u32 val;
3010
3011 if (!test_bit(QM_SUPPORT_MB_COMMAND, &qm->caps))
3012 return;
3013
3014 /* Clear communication interrupt source */
3015 qm_clear_cmd_interrupt(qm, QM_IFC_INT_SOURCE_CLR);
3016
3017 /* Enable pf to vf communication reg. */
3018 val = readl(addr: qm->io_base + QM_IFC_INT_MASK);
3019 val &= ~QM_IFC_INT_DISABLE;
3020 writel(val, addr: qm->io_base + QM_IFC_INT_MASK);
3021}
3022
3023static void qm_put_pci_res(struct hisi_qm *qm)
3024{
3025 struct pci_dev *pdev = qm->pdev;
3026
3027 if (test_bit(QM_SUPPORT_DB_ISOLATION, &qm->caps))
3028 iounmap(addr: qm->db_io_base);
3029
3030 iounmap(addr: qm->io_base);
3031 pci_release_mem_regions(pdev);
3032}
3033
3034static void hisi_mig_region_clear(struct hisi_qm *qm)
3035{
3036 u32 val;
3037
3038 /* Clear migration region set of PF */
3039 if (qm->fun_type == QM_HW_PF && qm->ver > QM_HW_V3) {
3040 val = readl(addr: qm->io_base + QM_MIG_REGION_SEL);
3041 val &= ~QM_MIG_REGION_EN;
3042 writel(val, addr: qm->io_base + QM_MIG_REGION_SEL);
3043 }
3044}
3045
3046static void hisi_mig_region_enable(struct hisi_qm *qm)
3047{
3048 u32 val;
3049
3050 /* Select migration region of PF */
3051 if (qm->fun_type == QM_HW_PF && qm->ver > QM_HW_V3) {
3052 val = readl(addr: qm->io_base + QM_MIG_REGION_SEL);
3053 val |= QM_MIG_REGION_EN;
3054 writel(val, addr: qm->io_base + QM_MIG_REGION_SEL);
3055 }
3056}
3057
3058static void hisi_qm_pci_uninit(struct hisi_qm *qm)
3059{
3060 struct pci_dev *pdev = qm->pdev;
3061
3062 pci_free_irq_vectors(dev: pdev);
3063 hisi_mig_region_clear(qm);
3064 qm_put_pci_res(qm);
3065 pci_disable_device(dev: pdev);
3066}
3067
3068static void hisi_qm_set_state(struct hisi_qm *qm, u8 state)
3069{
3070 if (qm->ver > QM_HW_V2 && qm->fun_type == QM_HW_VF)
3071 writel(val: state, addr: qm->io_base + QM_VF_STATE);
3072}
3073
3074static void hisi_qm_unint_work(struct hisi_qm *qm)
3075{
3076 destroy_workqueue(wq: qm->wq);
3077}
3078
3079static void hisi_qm_free_rsv_buf(struct hisi_qm *qm)
3080{
3081 struct qm_dma *xqc_dma = &qm->xqc_buf.qcdma;
3082 struct device *dev = &qm->pdev->dev;
3083
3084 dma_free_coherent(dev, size: xqc_dma->size, cpu_addr: xqc_dma->va, dma_handle: xqc_dma->dma);
3085}
3086
3087static void hisi_qm_memory_uninit(struct hisi_qm *qm)
3088{
3089 struct device *dev = &qm->pdev->dev;
3090
3091 hisi_qp_memory_uninit(qm, num: qm->qp_num);
3092 hisi_qm_free_rsv_buf(qm);
3093 if (qm->qdma.va) {
3094 hisi_qm_cache_wb(qm);
3095 dma_free_coherent(dev, size: qm->qdma.size,
3096 cpu_addr: qm->qdma.va, dma_handle: qm->qdma.dma);
3097 }
3098
3099 idr_destroy(&qm->qp_idr);
3100
3101 if (test_bit(QM_SUPPORT_FUNC_QOS, &qm->caps))
3102 kfree(objp: qm->factor);
3103}
3104
3105/**
3106 * hisi_qm_uninit() - Uninitialize qm.
3107 * @qm: The qm needed uninit.
3108 *
3109 * This function uninits qm related device resources.
3110 */
3111void hisi_qm_uninit(struct hisi_qm *qm)
3112{
3113 qm_cmd_uninit(qm);
3114 hisi_qm_unint_work(qm);
3115
3116 down_write(sem: &qm->qps_lock);
3117 hisi_qm_memory_uninit(qm);
3118 hisi_qm_set_state(qm, state: QM_NOT_READY);
3119 up_write(sem: &qm->qps_lock);
3120
3121 qm_remove_uacce(qm);
3122 qm_irqs_unregister(qm);
3123 hisi_qm_pci_uninit(qm);
3124}
3125EXPORT_SYMBOL_GPL(hisi_qm_uninit);
3126
3127/**
3128 * hisi_qm_get_vft() - Get vft from a qm.
3129 * @qm: The qm we want to get its vft.
3130 * @base: The base number of queue in vft.
3131 * @number: The number of queues in vft.
3132 *
3133 * We can allocate multiple queues to a qm by configuring virtual function
3134 * table. We get related configures by this function. Normally, we call this
3135 * function in VF driver to get the queue information.
3136 *
3137 * qm hw v1 does not support this interface.
3138 */
3139static int hisi_qm_get_vft(struct hisi_qm *qm, u32 *base, u32 *number)
3140{
3141 if (!base || !number)
3142 return -EINVAL;
3143
3144 if (!qm->ops->get_vft) {
3145 dev_err(&qm->pdev->dev, "Don't support vft read!\n");
3146 return -EINVAL;
3147 }
3148
3149 return qm->ops->get_vft(qm, base, number);
3150}
3151
3152/**
3153 * hisi_qm_set_vft() - Set vft to a qm.
3154 * @qm: The qm we want to set its vft.
3155 * @fun_num: The function number.
3156 * @base: The base number of queue in vft.
3157 * @number: The number of queues in vft.
3158 *
3159 * This function is alway called in PF driver, it is used to assign queues
3160 * among PF and VFs.
3161 *
3162 * Assign queues A~B to PF: hisi_qm_set_vft(qm, 0, A, B - A + 1)
3163 * Assign queues A~B to VF: hisi_qm_set_vft(qm, 2, A, B - A + 1)
3164 * (VF function number 0x2)
3165 */
3166static int hisi_qm_set_vft(struct hisi_qm *qm, u32 fun_num, u32 base,
3167 u32 number)
3168{
3169 u32 max_q_num = qm->ctrl_qp_num;
3170
3171 if (base >= max_q_num || number > max_q_num ||
3172 (base + number) > max_q_num)
3173 return -EINVAL;
3174
3175 return qm_set_sqc_cqc_vft(qm, fun_num, base, number);
3176}
3177
3178static void qm_init_eq_aeq_status(struct hisi_qm *qm)
3179{
3180 struct hisi_qm_status *status = &qm->status;
3181
3182 status->eq_head = 0;
3183 status->aeq_head = 0;
3184 status->eqc_phase = true;
3185 status->aeqc_phase = true;
3186}
3187
3188static void qm_enable_eq_aeq_interrupts(struct hisi_qm *qm)
3189{
3190 /* Clear eq/aeq interrupt source */
3191 qm_db(qm, qn: 0, QM_DOORBELL_CMD_AEQ, index: qm->status.aeq_head, priority: 0);
3192 qm_db(qm, qn: 0, QM_DOORBELL_CMD_EQ, index: qm->status.eq_head, priority: 0);
3193
3194 writel(val: 0x0, addr: qm->io_base + QM_VF_EQ_INT_MASK);
3195 writel(val: 0x0, addr: qm->io_base + QM_VF_AEQ_INT_MASK);
3196}
3197
3198static void qm_disable_eq_aeq_interrupts(struct hisi_qm *qm)
3199{
3200 writel(val: 0x1, addr: qm->io_base + QM_VF_EQ_INT_MASK);
3201 writel(val: 0x1, addr: qm->io_base + QM_VF_AEQ_INT_MASK);
3202}
3203
3204static int qm_eq_ctx_cfg(struct hisi_qm *qm)
3205{
3206 struct qm_eqc eqc = {0};
3207
3208 eqc.base_l = cpu_to_le32(lower_32_bits(qm->eqe_dma));
3209 eqc.base_h = cpu_to_le32(upper_32_bits(qm->eqe_dma));
3210 if (qm->ver == QM_HW_V1)
3211 eqc.dw3 = cpu_to_le32(QM_EQE_AEQE_SIZE);
3212 eqc.dw6 = cpu_to_le32(((u32)qm->eq_depth - 1) | (1 << QM_EQC_PHASE_SHIFT));
3213
3214 return qm_set_and_get_xqc(qm, QM_MB_CMD_EQC, xqc: &eqc, qp_id: 0, op: 0);
3215}
3216
3217static int qm_aeq_ctx_cfg(struct hisi_qm *qm)
3218{
3219 struct qm_aeqc aeqc = {0};
3220
3221 aeqc.base_l = cpu_to_le32(lower_32_bits(qm->aeqe_dma));
3222 aeqc.base_h = cpu_to_le32(upper_32_bits(qm->aeqe_dma));
3223 aeqc.dw6 = cpu_to_le32(((u32)qm->aeq_depth - 1) | (1 << QM_EQC_PHASE_SHIFT));
3224
3225 return qm_set_and_get_xqc(qm, QM_MB_CMD_AEQC, xqc: &aeqc, qp_id: 0, op: 0);
3226}
3227
3228static int qm_eq_aeq_ctx_cfg(struct hisi_qm *qm)
3229{
3230 struct device *dev = &qm->pdev->dev;
3231 int ret;
3232
3233 qm_init_eq_aeq_status(qm);
3234
3235 /* Before starting the dev, clear the memory and then configure to device using. */
3236 memset(qm->qdma.va, 0, qm->qdma.size);
3237
3238 ret = qm_eq_ctx_cfg(qm);
3239 if (ret) {
3240 dev_err(dev, "Set eqc failed!\n");
3241 return ret;
3242 }
3243
3244 return qm_aeq_ctx_cfg(qm);
3245}
3246
3247static int __hisi_qm_start(struct hisi_qm *qm)
3248{
3249 struct device *dev = &qm->pdev->dev;
3250 int ret;
3251
3252 if (!qm->qdma.va) {
3253 dev_err(dev, "qm qdma is NULL!\n");
3254 return -EINVAL;
3255 }
3256
3257 if (qm->fun_type == QM_HW_PF) {
3258 ret = hisi_qm_set_vft(qm, fun_num: 0, base: qm->qp_base, number: qm->qp_num);
3259 if (ret)
3260 return ret;
3261 }
3262
3263 ret = qm_eq_aeq_ctx_cfg(qm);
3264 if (ret)
3265 return ret;
3266
3267 ret = hisi_qm_mb(qm, QM_MB_CMD_SQC_BT, qm->sqc_dma, 0, 0);
3268 if (ret)
3269 return ret;
3270
3271 ret = hisi_qm_mb(qm, QM_MB_CMD_CQC_BT, qm->cqc_dma, 0, 0);
3272 if (ret)
3273 return ret;
3274
3275 qm_init_prefetch(qm);
3276 qm_enable_eq_aeq_interrupts(qm);
3277
3278 return 0;
3279}
3280
3281/**
3282 * hisi_qm_start() - start qm
3283 * @qm: The qm to be started.
3284 *
3285 * This function starts a qm, then we can allocate qp from this qm.
3286 */
3287int hisi_qm_start(struct hisi_qm *qm)
3288{
3289 struct device *dev = &qm->pdev->dev;
3290 int ret = 0;
3291
3292 down_write(sem: &qm->qps_lock);
3293
3294 dev_dbg(dev, "qm start with %u queue pairs\n", qm->qp_num);
3295
3296 if (!qm->qp_num) {
3297 dev_err(dev, "qp_num should not be 0\n");
3298 ret = -EINVAL;
3299 goto err_unlock;
3300 }
3301
3302 ret = __hisi_qm_start(qm);
3303 if (ret)
3304 goto err_unlock;
3305
3306 atomic_set(v: &qm->status.flags, i: QM_WORK);
3307 hisi_qm_set_state(qm, state: QM_READY);
3308
3309err_unlock:
3310 up_write(sem: &qm->qps_lock);
3311 return ret;
3312}
3313EXPORT_SYMBOL_GPL(hisi_qm_start);
3314
3315static int qm_restart(struct hisi_qm *qm)
3316{
3317 struct device *dev = &qm->pdev->dev;
3318 struct hisi_qp *qp;
3319 int ret, i;
3320
3321 ret = hisi_qm_start(qm);
3322 if (ret < 0)
3323 return ret;
3324
3325 down_write(sem: &qm->qps_lock);
3326 for (i = 0; i < qm->qp_num; i++) {
3327 qp = &qm->qp_array[i];
3328 if (atomic_read(v: &qp->qp_status.flags) == QP_STOP &&
3329 qp->is_resetting == true && qp->is_in_kernel == true) {
3330 ret = qm_start_qp_nolock(qp, arg: 0);
3331 if (ret < 0) {
3332 dev_err(dev, "Failed to start qp%d!\n", i);
3333
3334 up_write(sem: &qm->qps_lock);
3335 return ret;
3336 }
3337 qp->is_resetting = false;
3338 }
3339 }
3340 up_write(sem: &qm->qps_lock);
3341
3342 return 0;
3343}
3344
3345/* Stop started qps in reset flow */
3346static void qm_stop_started_qp(struct hisi_qm *qm)
3347{
3348 struct hisi_qp *qp;
3349 int i;
3350
3351 for (i = 0; i < qm->qp_num; i++) {
3352 qp = &qm->qp_array[i];
3353 if (atomic_read(v: &qp->qp_status.flags) == QP_START) {
3354 qp->is_resetting = true;
3355 qm_stop_qp_nolock(qp);
3356 }
3357 }
3358}
3359
3360/**
3361 * qm_invalid_queues() - invalid all queues in use.
3362 * @qm: The qm in which the queues will be invalidated.
3363 *
3364 * This function invalid all queues in use. If the doorbell command is sent
3365 * to device in user space after the device is reset, the device discards
3366 * the doorbell command.
3367 */
3368static void qm_invalid_queues(struct hisi_qm *qm)
3369{
3370 struct hisi_qp *qp;
3371 struct qm_sqc *sqc;
3372 struct qm_cqc *cqc;
3373 int i;
3374
3375 /*
3376 * Normal stop queues is no longer used and does not need to be
3377 * invalid queues.
3378 */
3379 if (qm->status.stop_reason == QM_NORMAL)
3380 return;
3381
3382 if (qm->status.stop_reason == QM_DOWN)
3383 hisi_qm_cache_wb(qm);
3384
3385 for (i = 0; i < qm->qp_num; i++) {
3386 qp = &qm->qp_array[i];
3387 if (!qp->is_resetting)
3388 continue;
3389
3390 /* Modify random data and set sqc close bit to invalid queue. */
3391 sqc = qm->sqc + i;
3392 cqc = qm->cqc + i;
3393 sqc->w8 = cpu_to_le16(QM_XQC_RANDOM_DATA);
3394 sqc->w13 = cpu_to_le16(QM_SQC_DISABLE_QP);
3395 cqc->w8 = cpu_to_le16(QM_XQC_RANDOM_DATA);
3396 if (qp->is_in_kernel)
3397 memset(qp->qdma.va, 0, qp->qdma.size);
3398 }
3399}
3400
3401/**
3402 * hisi_qm_stop() - Stop a qm.
3403 * @qm: The qm which will be stopped.
3404 * @r: The reason to stop qm.
3405 *
3406 * This function stops qm and its qps, then qm can not accept request.
3407 * Related resources are not released at this state, we can use hisi_qm_start
3408 * to let qm start again.
3409 */
3410int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r)
3411{
3412 struct device *dev = &qm->pdev->dev;
3413 int ret = 0;
3414
3415 down_write(sem: &qm->qps_lock);
3416
3417 if (atomic_read(v: &qm->status.flags) == QM_STOP)
3418 goto err_unlock;
3419
3420 /* Stop all the request sending at first. */
3421 atomic_set(v: &qm->status.flags, i: QM_STOP);
3422 qm->status.stop_reason = r;
3423
3424 if (qm->status.stop_reason != QM_NORMAL) {
3425 hisi_qm_set_hw_reset(qm, QM_RESET_STOP_TX_OFFSET);
3426 /*
3427 * When performing soft reset, the hardware will no longer
3428 * do tasks, and the tasks in the device will be flushed
3429 * out directly since the master ooo is closed.
3430 */
3431 if (test_bit(QM_SUPPORT_STOP_FUNC, &qm->caps) &&
3432 r != QM_SOFT_RESET) {
3433 ret = qm_drain_qm(qm);
3434 if (ret) {
3435 dev_err(dev, "failed to drain qm!\n");
3436 goto err_unlock;
3437 }
3438 }
3439
3440 qm_stop_started_qp(qm);
3441
3442 hisi_qm_set_hw_reset(qm, QM_RESET_STOP_RX_OFFSET);
3443 }
3444
3445 qm_disable_eq_aeq_interrupts(qm);
3446 if (qm->fun_type == QM_HW_PF) {
3447 ret = hisi_qm_set_vft(qm, fun_num: 0, base: 0, number: 0);
3448 if (ret < 0) {
3449 dev_err(dev, "Failed to set vft!\n");
3450 ret = -EBUSY;
3451 goto err_unlock;
3452 }
3453 }
3454
3455 qm_invalid_queues(qm);
3456 qm->status.stop_reason = QM_NORMAL;
3457
3458err_unlock:
3459 up_write(sem: &qm->qps_lock);
3460 return ret;
3461}
3462EXPORT_SYMBOL_GPL(hisi_qm_stop);
3463
3464static void qm_hw_error_init(struct hisi_qm *qm)
3465{
3466 if (!qm->ops->hw_error_init) {
3467 dev_err(&qm->pdev->dev, "QM doesn't support hw error handling!\n");
3468 return;
3469 }
3470
3471 qm->ops->hw_error_init(qm);
3472}
3473
3474static void qm_hw_error_uninit(struct hisi_qm *qm)
3475{
3476 if (!qm->ops->hw_error_uninit) {
3477 dev_err(&qm->pdev->dev, "Unexpected QM hw error uninit!\n");
3478 return;
3479 }
3480
3481 qm->ops->hw_error_uninit(qm);
3482}
3483
3484static enum acc_err_result qm_hw_error_handle(struct hisi_qm *qm)
3485{
3486 if (!qm->ops->hw_error_handle) {
3487 dev_err(&qm->pdev->dev, "QM doesn't support hw error report!\n");
3488 return ACC_ERR_NONE;
3489 }
3490
3491 return qm->ops->hw_error_handle(qm);
3492}
3493
3494/**
3495 * hisi_qm_dev_err_init() - Initialize device error configuration.
3496 * @qm: The qm for which we want to do error initialization.
3497 *
3498 * Initialize QM and device error related configuration.
3499 */
3500void hisi_qm_dev_err_init(struct hisi_qm *qm)
3501{
3502 if (qm->fun_type == QM_HW_VF)
3503 return;
3504
3505 qm_hw_error_init(qm);
3506
3507 if (!qm->err_ini->hw_err_enable) {
3508 dev_err(&qm->pdev->dev, "Device doesn't support hw error init!\n");
3509 return;
3510 }
3511 qm->err_ini->hw_err_enable(qm);
3512}
3513EXPORT_SYMBOL_GPL(hisi_qm_dev_err_init);
3514
3515/**
3516 * hisi_qm_dev_err_uninit() - Uninitialize device error configuration.
3517 * @qm: The qm for which we want to do error uninitialization.
3518 *
3519 * Uninitialize QM and device error related configuration.
3520 */
3521void hisi_qm_dev_err_uninit(struct hisi_qm *qm)
3522{
3523 if (qm->fun_type == QM_HW_VF)
3524 return;
3525
3526 qm_hw_error_uninit(qm);
3527
3528 if (!qm->err_ini->hw_err_disable) {
3529 dev_err(&qm->pdev->dev, "Unexpected device hw error uninit!\n");
3530 return;
3531 }
3532 qm->err_ini->hw_err_disable(qm);
3533}
3534EXPORT_SYMBOL_GPL(hisi_qm_dev_err_uninit);
3535
3536/**
3537 * hisi_qm_free_qps() - free multiple queue pairs.
3538 * @qps: The queue pairs need to be freed.
3539 * @qp_num: The num of queue pairs.
3540 */
3541void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num)
3542{
3543 int i;
3544
3545 if (!qps || qp_num <= 0)
3546 return;
3547
3548 for (i = qp_num - 1; i >= 0; i--)
3549 hisi_qm_release_qp(qp: qps[i]);
3550}
3551EXPORT_SYMBOL_GPL(hisi_qm_free_qps);
3552
3553static void free_list(struct list_head *head)
3554{
3555 struct hisi_qm_resource *res, *tmp;
3556
3557 list_for_each_entry_safe(res, tmp, head, list) {
3558 list_del(entry: &res->list);
3559 kfree(objp: res);
3560 }
3561}
3562
3563static int hisi_qm_sort_devices(int node, struct list_head *head,
3564 struct hisi_qm_list *qm_list)
3565{
3566 struct hisi_qm_resource *res, *tmp;
3567 struct hisi_qm *qm;
3568 struct list_head *n;
3569 struct device *dev;
3570 int dev_node;
3571
3572 list_for_each_entry(qm, &qm_list->list, list) {
3573 dev = &qm->pdev->dev;
3574
3575 dev_node = dev_to_node(dev);
3576 if (dev_node < 0)
3577 dev_node = 0;
3578
3579 res = kzalloc(sizeof(*res), GFP_KERNEL);
3580 if (!res)
3581 return -ENOMEM;
3582
3583 res->qm = qm;
3584 res->distance = node_distance(dev_node, node);
3585 n = head;
3586 list_for_each_entry(tmp, head, list) {
3587 if (res->distance < tmp->distance) {
3588 n = &tmp->list;
3589 break;
3590 }
3591 }
3592 list_add_tail(new: &res->list, head: n);
3593 }
3594
3595 return 0;
3596}
3597
3598/**
3599 * hisi_qm_alloc_qps_node() - Create multiple queue pairs.
3600 * @qm_list: The list of all available devices.
3601 * @qp_num: The number of queue pairs need created.
3602 * @alg_type: The algorithm type.
3603 * @node: The numa node.
3604 * @qps: The queue pairs need created.
3605 *
3606 * This function will sort all available device according to numa distance.
3607 * Then try to create all queue pairs from one device, if all devices do
3608 * not meet the requirements will return error.
3609 */
3610int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num,
3611 u8 alg_type, int node, struct hisi_qp **qps)
3612{
3613 struct hisi_qm_resource *tmp;
3614 int ret = -ENODEV;
3615 LIST_HEAD(head);
3616 int i;
3617
3618 if (!qps || !qm_list || qp_num <= 0)
3619 return -EINVAL;
3620
3621 mutex_lock(&qm_list->lock);
3622 if (hisi_qm_sort_devices(node, head: &head, qm_list)) {
3623 mutex_unlock(lock: &qm_list->lock);
3624 goto err;
3625 }
3626
3627 list_for_each_entry(tmp, &head, list) {
3628 for (i = 0; i < qp_num; i++) {
3629 qps[i] = hisi_qm_create_qp(qm: tmp->qm, alg_type);
3630 if (IS_ERR(ptr: qps[i])) {
3631 hisi_qm_free_qps(qps, i);
3632 break;
3633 }
3634 }
3635
3636 if (i == qp_num) {
3637 ret = 0;
3638 break;
3639 }
3640 }
3641
3642 mutex_unlock(lock: &qm_list->lock);
3643 if (ret)
3644 pr_info("Failed to create qps, node[%d], alg[%u], qp[%d]!\n",
3645 node, alg_type, qp_num);
3646
3647err:
3648 free_list(head: &head);
3649 return ret;
3650}
3651EXPORT_SYMBOL_GPL(hisi_qm_alloc_qps_node);
3652
3653static int qm_vf_q_assign(struct hisi_qm *qm, u32 num_vfs)
3654{
3655 u32 remain_q_num, vfs_q_num, act_q_num, q_num, i, j;
3656 u32 max_qp_num = qm->max_qp_num;
3657 u32 q_base = qm->qp_num;
3658 int ret;
3659
3660 if (!num_vfs)
3661 return -EINVAL;
3662
3663 vfs_q_num = qm->ctrl_qp_num - qm->qp_num;
3664
3665 /* If vfs_q_num is less than num_vfs, return error. */
3666 if (vfs_q_num < num_vfs)
3667 return -EINVAL;
3668
3669 q_num = vfs_q_num / num_vfs;
3670 remain_q_num = vfs_q_num % num_vfs;
3671
3672 for (i = num_vfs; i > 0; i--) {
3673 /*
3674 * if q_num + remain_q_num > max_qp_num in last vf, divide the
3675 * remaining queues equally.
3676 */
3677 if (i == num_vfs && q_num + remain_q_num <= max_qp_num) {
3678 act_q_num = q_num + remain_q_num;
3679 remain_q_num = 0;
3680 } else if (remain_q_num > 0) {
3681 act_q_num = q_num + 1;
3682 remain_q_num--;
3683 } else {
3684 act_q_num = q_num;
3685 }
3686
3687 act_q_num = min(act_q_num, max_qp_num);
3688 ret = hisi_qm_set_vft(qm, fun_num: i, base: q_base, number: act_q_num);
3689 if (ret) {
3690 for (j = num_vfs; j > i; j--)
3691 hisi_qm_set_vft(qm, fun_num: j, base: 0, number: 0);
3692 return ret;
3693 }
3694 q_base += act_q_num;
3695 }
3696
3697 return 0;
3698}
3699
3700static void qm_clear_vft_config(struct hisi_qm *qm)
3701{
3702 u32 i;
3703
3704 /*
3705 * When disabling SR-IOV, clear the configuration of each VF in the hardware
3706 * sequentially. Failure to clear a single VF should not affect the clearing
3707 * operation of other VFs.
3708 */
3709 for (i = 1; i <= qm->vfs_num; i++)
3710 (void)hisi_qm_set_vft(qm, fun_num: i, base: 0, number: 0);
3711
3712 qm->vfs_num = 0;
3713}
3714
3715static int qm_func_shaper_enable(struct hisi_qm *qm, u32 fun_index, u32 qos)
3716{
3717 struct device *dev = &qm->pdev->dev;
3718 struct qm_shaper_factor t_factor;
3719 u32 ir = qos * QM_QOS_RATE;
3720 int ret, total_vfs, i;
3721
3722 total_vfs = pci_sriov_get_totalvfs(dev: qm->pdev);
3723 if (fun_index > total_vfs)
3724 return -EINVAL;
3725
3726 memcpy(&t_factor, &qm->factor[fun_index], sizeof(t_factor));
3727 qm->factor[fun_index].func_qos = qos;
3728
3729 ret = qm_get_shaper_para(ir, factor: &qm->factor[fun_index]);
3730 if (ret) {
3731 dev_err(dev, "failed to calculate shaper parameter!\n");
3732 return -EINVAL;
3733 }
3734
3735 for (i = ALG_TYPE_0; i <= ALG_TYPE_1; i++) {
3736 /* The base number of queue reuse for different alg type */
3737 ret = qm_set_vft_common(qm, type: SHAPER_VFT, fun_num: fun_index, base: i, number: 1);
3738 if (ret) {
3739 dev_err(dev, "type: %d, failed to set shaper vft!\n", i);
3740 goto back_func_qos;
3741 }
3742 }
3743
3744 return 0;
3745
3746back_func_qos:
3747 memcpy(&qm->factor[fun_index], &t_factor, sizeof(t_factor));
3748 for (i--; i >= ALG_TYPE_0; i--) {
3749 ret = qm_set_vft_common(qm, type: SHAPER_VFT, fun_num: fun_index, base: i, number: 1);
3750 if (ret)
3751 dev_err(dev, "failed to restore shaper vft during rollback!\n");
3752 }
3753
3754 return -EINVAL;
3755}
3756
3757static u32 qm_get_shaper_vft_qos(struct hisi_qm *qm, u32 fun_index)
3758{
3759 u64 cir_u = 0, cir_b = 0, cir_s = 0;
3760 u64 shaper_vft, ir_calc, ir;
3761 unsigned int val;
3762 u32 error_rate;
3763 int ret;
3764
3765 ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
3766 val & BIT(0), POLL_PERIOD,
3767 POLL_TIMEOUT);
3768 if (ret)
3769 return 0;
3770
3771 writel(val: 0x1, addr: qm->io_base + QM_VFT_CFG_OP_WR);
3772 writel(val: SHAPER_VFT, addr: qm->io_base + QM_VFT_CFG_TYPE);
3773 writel(val: fun_index, addr: qm->io_base + QM_VFT_CFG);
3774
3775 writel(val: 0x0, addr: qm->io_base + QM_VFT_CFG_RDY);
3776 writel(val: 0x1, addr: qm->io_base + QM_VFT_CFG_OP_ENABLE);
3777
3778 ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
3779 val & BIT(0), POLL_PERIOD,
3780 POLL_TIMEOUT);
3781 if (ret)
3782 return 0;
3783
3784 shaper_vft = readl(addr: qm->io_base + QM_VFT_CFG_DATA_L) |
3785 ((u64)readl(addr: qm->io_base + QM_VFT_CFG_DATA_H) << 32);
3786
3787 cir_b = shaper_vft & QM_SHAPER_CIR_B_MASK;
3788 cir_u = shaper_vft & QM_SHAPER_CIR_U_MASK;
3789 cir_u = cir_u >> QM_SHAPER_FACTOR_CIR_U_SHIFT;
3790
3791 cir_s = shaper_vft & QM_SHAPER_CIR_S_MASK;
3792 cir_s = cir_s >> QM_SHAPER_FACTOR_CIR_S_SHIFT;
3793
3794 ir_calc = acc_shaper_para_calc(cir_b, cir_u, cir_s);
3795
3796 ir = qm->factor[fun_index].func_qos * QM_QOS_RATE;
3797
3798 error_rate = QM_QOS_EXPAND_RATE * (u32)abs(ir_calc - ir) / ir;
3799 if (error_rate > QM_QOS_MIN_ERROR_RATE) {
3800 pci_err(qm->pdev, "error_rate: %u, get function qos is error!\n", error_rate);
3801 return 0;
3802 }
3803
3804 return ir;
3805}
3806
3807static void qm_vf_get_qos(struct hisi_qm *qm, u32 fun_num)
3808{
3809 struct device *dev = &qm->pdev->dev;
3810 u32 qos;
3811 int ret;
3812
3813 qos = qm_get_shaper_vft_qos(qm, fun_index: fun_num);
3814 if (!qos) {
3815 dev_err(dev, "function(%u) failed to get qos by PF!\n", fun_num);
3816 return;
3817 }
3818
3819 ret = qm_ping_single_vf(qm, cmd: QM_PF_SET_QOS, data: qos, fun_num);
3820 if (ret)
3821 dev_err(dev, "failed to send command(0x%x) to VF(%u)!\n", QM_PF_SET_QOS, fun_num);
3822}
3823
3824static int qm_vf_read_qos(struct hisi_qm *qm)
3825{
3826 int cnt = 0;
3827 int ret = -EINVAL;
3828
3829 /* reset mailbox qos val */
3830 qm->mb_qos = 0;
3831
3832 /* vf ping pf to get function qos */
3833 ret = qm_ping_pf(qm, cmd: QM_VF_GET_QOS);
3834 if (ret) {
3835 pci_err(qm->pdev, "failed to send cmd to PF to get qos!\n");
3836 return ret;
3837 }
3838
3839 while (true) {
3840 msleep(QM_WAIT_DST_ACK);
3841 if (qm->mb_qos)
3842 break;
3843
3844 if (++cnt > QM_MAX_VF_WAIT_COUNT) {
3845 pci_err(qm->pdev, "PF ping VF timeout!\n");
3846 return -ETIMEDOUT;
3847 }
3848 }
3849
3850 return ret;
3851}
3852
3853static ssize_t qm_algqos_read(struct file *filp, char __user *buf,
3854 size_t count, loff_t *pos)
3855{
3856 struct hisi_qm *qm = filp->private_data;
3857 char tbuf[QM_DBG_READ_LEN];
3858 u32 qos_val, ir;
3859 int ret;
3860
3861 ret = hisi_qm_get_dfx_access(qm);
3862 if (ret)
3863 return ret;
3864
3865 /* Mailbox and reset cannot be operated at the same time */
3866 if (test_and_set_bit(nr: QM_RESETTING, addr: &qm->misc_ctl)) {
3867 pci_err(qm->pdev, "dev resetting, read alg qos failed!\n");
3868 ret = -EAGAIN;
3869 goto err_put_dfx_access;
3870 }
3871
3872 if (qm->fun_type == QM_HW_PF) {
3873 ir = qm_get_shaper_vft_qos(qm, fun_index: 0);
3874 } else {
3875 ret = qm_vf_read_qos(qm);
3876 if (ret)
3877 goto err_get_status;
3878 ir = qm->mb_qos;
3879 }
3880
3881 qos_val = ir / QM_QOS_RATE;
3882 ret = scnprintf(buf: tbuf, QM_DBG_READ_LEN, fmt: "%u\n", qos_val);
3883
3884 ret = simple_read_from_buffer(to: buf, count, ppos: pos, from: tbuf, available: ret);
3885
3886err_get_status:
3887 clear_bit(nr: QM_RESETTING, addr: &qm->misc_ctl);
3888err_put_dfx_access:
3889 hisi_qm_put_dfx_access(qm);
3890 return ret;
3891}
3892
3893static ssize_t qm_get_qos_value(struct hisi_qm *qm, const char *buf,
3894 unsigned long *val,
3895 unsigned int *fun_index)
3896{
3897 const struct bus_type *bus_type = qm->pdev->dev.bus;
3898 char tbuf_bdf[QM_DBG_READ_LEN] = {0};
3899 char val_buf[QM_DBG_READ_LEN] = {0};
3900 struct pci_dev *pdev;
3901 struct device *dev;
3902 int ret;
3903
3904 ret = sscanf(buf, "%s %s", tbuf_bdf, val_buf);
3905 if (ret != QM_QOS_PARAM_NUM)
3906 return -EINVAL;
3907
3908 ret = kstrtoul(s: val_buf, base: 10, res: val);
3909 if (ret || *val == 0 || *val > QM_QOS_MAX_VAL) {
3910 pci_err(qm->pdev, "input qos value is error, please set 1~1000!\n");
3911 return -EINVAL;
3912 }
3913
3914 dev = bus_find_device_by_name(bus: bus_type, NULL, name: tbuf_bdf);
3915 if (!dev) {
3916 pci_err(qm->pdev, "input pci bdf number is error!\n");
3917 return -ENODEV;
3918 }
3919
3920 pdev = container_of(dev, struct pci_dev, dev);
3921 if (pci_physfn(dev: pdev) != qm->pdev) {
3922 pci_err(qm->pdev, "the pdev input does not match the pf!\n");
3923 put_device(dev);
3924 return -EINVAL;
3925 }
3926
3927 *fun_index = pdev->devfn;
3928 put_device(dev);
3929
3930 return 0;
3931}
3932
3933static ssize_t qm_algqos_write(struct file *filp, const char __user *buf,
3934 size_t count, loff_t *pos)
3935{
3936 struct hisi_qm *qm = filp->private_data;
3937 char tbuf[QM_DBG_READ_LEN];
3938 unsigned int fun_index;
3939 unsigned long val;
3940 int len, ret;
3941
3942 if (*pos != 0)
3943 return 0;
3944
3945 if (count >= QM_DBG_READ_LEN)
3946 return -ENOSPC;
3947
3948 len = simple_write_to_buffer(to: tbuf, QM_DBG_READ_LEN - 1, ppos: pos, from: buf, count);
3949 if (len < 0)
3950 return len;
3951
3952 tbuf[len] = '\0';
3953 ret = qm_get_qos_value(qm, buf: tbuf, val: &val, fun_index: &fun_index);
3954 if (ret)
3955 return ret;
3956
3957 /* Mailbox and reset cannot be operated at the same time */
3958 if (test_and_set_bit(nr: QM_RESETTING, addr: &qm->misc_ctl)) {
3959 pci_err(qm->pdev, "dev resetting, write alg qos failed!\n");
3960 return -EAGAIN;
3961 }
3962
3963 ret = qm_pm_get_sync(qm);
3964 if (ret) {
3965 ret = -EINVAL;
3966 goto err_get_status;
3967 }
3968
3969 ret = qm_func_shaper_enable(qm, fun_index, qos: val);
3970 if (ret) {
3971 pci_err(qm->pdev, "failed to enable function shaper!\n");
3972 ret = -EINVAL;
3973 goto err_put_sync;
3974 }
3975
3976 pci_info(qm->pdev, "the qos value of function%u is set to %lu.\n",
3977 fun_index, val);
3978 ret = count;
3979
3980err_put_sync:
3981 qm_pm_put_sync(qm);
3982err_get_status:
3983 clear_bit(nr: QM_RESETTING, addr: &qm->misc_ctl);
3984 return ret;
3985}
3986
3987static const struct file_operations qm_algqos_fops = {
3988 .owner = THIS_MODULE,
3989 .open = simple_open,
3990 .read = qm_algqos_read,
3991 .write = qm_algqos_write,
3992};
3993
3994/**
3995 * hisi_qm_set_algqos_init() - Initialize function qos debugfs files.
3996 * @qm: The qm for which we want to add debugfs files.
3997 *
3998 * Create function qos debugfs files, VF ping PF to get function qos.
3999 */
4000void hisi_qm_set_algqos_init(struct hisi_qm *qm)
4001{
4002 if (qm->fun_type == QM_HW_PF)
4003 debugfs_create_file("alg_qos", 0644, qm->debug.debug_root,
4004 qm, &qm_algqos_fops);
4005 else if (test_bit(QM_SUPPORT_MB_COMMAND, &qm->caps))
4006 debugfs_create_file("alg_qos", 0444, qm->debug.debug_root,
4007 qm, &qm_algqos_fops);
4008}
4009
4010static void hisi_qm_init_vf_qos(struct hisi_qm *qm, int total_func)
4011{
4012 int i;
4013
4014 for (i = 1; i <= total_func; i++)
4015 qm->factor[i].func_qos = QM_QOS_MAX_VAL;
4016}
4017
4018/**
4019 * hisi_qm_sriov_enable() - enable virtual functions
4020 * @pdev: the PCIe device
4021 * @max_vfs: the number of virtual functions to enable
4022 *
4023 * Returns the number of enabled VFs. If there are VFs enabled already or
4024 * max_vfs is more than the total number of device can be enabled, returns
4025 * failure.
4026 */
4027int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs)
4028{
4029 struct hisi_qm *qm = pci_get_drvdata(pdev);
4030 int pre_existing_vfs, num_vfs, total_vfs, ret;
4031
4032 ret = qm_pm_get_sync(qm);
4033 if (ret)
4034 return ret;
4035
4036 total_vfs = pci_sriov_get_totalvfs(dev: pdev);
4037 pre_existing_vfs = pci_num_vf(dev: pdev);
4038 if (pre_existing_vfs) {
4039 pci_err(pdev, "%d VFs already enabled. Please disable pre-enabled VFs!\n",
4040 pre_existing_vfs);
4041 goto err_put_sync;
4042 }
4043
4044 if (max_vfs > total_vfs) {
4045 pci_err(pdev, "%d VFs is more than total VFs %d!\n", max_vfs, total_vfs);
4046 ret = -ERANGE;
4047 goto err_put_sync;
4048 }
4049
4050 num_vfs = max_vfs;
4051
4052 if (test_bit(QM_SUPPORT_FUNC_QOS, &qm->caps))
4053 hisi_qm_init_vf_qos(qm, total_func: num_vfs);
4054
4055 ret = qm_vf_q_assign(qm, num_vfs);
4056 if (ret) {
4057 pci_err(pdev, "Can't assign queues for VF!\n");
4058 goto err_put_sync;
4059 }
4060
4061 qm->vfs_num = num_vfs;
4062 ret = pci_enable_sriov(dev: pdev, nr_virtfn: num_vfs);
4063 if (ret) {
4064 pci_err(pdev, "Can't enable VF!\n");
4065 qm_clear_vft_config(qm);
4066 goto err_put_sync;
4067 }
4068
4069 pci_info(pdev, "VF enabled, vfs_num(=%d)!\n", num_vfs);
4070
4071 return num_vfs;
4072
4073err_put_sync:
4074 qm_pm_put_sync(qm);
4075 return ret;
4076}
4077EXPORT_SYMBOL_GPL(hisi_qm_sriov_enable);
4078
4079/**
4080 * hisi_qm_sriov_disable - disable virtual functions
4081 * @pdev: the PCI device.
4082 * @is_frozen: true when all the VFs are frozen.
4083 *
4084 * Return failure if there are VFs assigned already or VF is in used.
4085 */
4086int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen)
4087{
4088 struct hisi_qm *qm = pci_get_drvdata(pdev);
4089
4090 if (pci_vfs_assigned(dev: pdev)) {
4091 pci_err(pdev, "Failed to disable VFs as VFs are assigned!\n");
4092 return -EPERM;
4093 }
4094
4095 /* While VF is in used, SRIOV cannot be disabled. */
4096 if (!is_frozen && qm_try_frozen_vfs(pdev, qm_list: qm->qm_list)) {
4097 pci_err(pdev, "Task is using its VF!\n");
4098 return -EBUSY;
4099 }
4100
4101 pci_disable_sriov(dev: pdev);
4102 qm_clear_vft_config(qm);
4103 qm_pm_put_sync(qm);
4104
4105 return 0;
4106}
4107EXPORT_SYMBOL_GPL(hisi_qm_sriov_disable);
4108
4109/**
4110 * hisi_qm_sriov_configure - configure the number of VFs
4111 * @pdev: The PCI device
4112 * @num_vfs: The number of VFs need enabled
4113 *
4114 * Enable SR-IOV according to num_vfs, 0 means disable.
4115 */
4116int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs)
4117{
4118 if (num_vfs == 0)
4119 return hisi_qm_sriov_disable(pdev, false);
4120 else
4121 return hisi_qm_sriov_enable(pdev, num_vfs);
4122}
4123EXPORT_SYMBOL_GPL(hisi_qm_sriov_configure);
4124
4125static enum acc_err_result qm_dev_err_handle(struct hisi_qm *qm)
4126{
4127 if (!qm->err_ini->get_err_result) {
4128 dev_err(&qm->pdev->dev, "Device doesn't support reset!\n");
4129 return ACC_ERR_NONE;
4130 }
4131
4132 return qm->err_ini->get_err_result(qm);
4133}
4134
4135static enum acc_err_result qm_process_dev_error(struct hisi_qm *qm)
4136{
4137 enum acc_err_result qm_ret, dev_ret;
4138
4139 /* log qm error */
4140 qm_ret = qm_hw_error_handle(qm);
4141
4142 /* log device error */
4143 dev_ret = qm_dev_err_handle(qm);
4144
4145 return (qm_ret == ACC_ERR_NEED_RESET ||
4146 dev_ret == ACC_ERR_NEED_RESET) ?
4147 ACC_ERR_NEED_RESET : ACC_ERR_RECOVERED;
4148}
4149
4150/**
4151 * hisi_qm_dev_err_detected() - Get device and qm error status then log it.
4152 * @pdev: The PCI device which need report error.
4153 * @state: The connectivity between CPU and device.
4154 *
4155 * We register this function into PCIe AER handlers, It will report device or
4156 * qm hardware error status when error occur.
4157 */
4158pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
4159 pci_channel_state_t state)
4160{
4161 struct hisi_qm *qm = pci_get_drvdata(pdev);
4162 enum acc_err_result ret;
4163
4164 if (pdev->is_virtfn)
4165 return PCI_ERS_RESULT_NONE;
4166
4167 pci_info(pdev, "PCI error detected, state(=%u)!!\n", state);
4168 if (state == pci_channel_io_perm_failure)
4169 return PCI_ERS_RESULT_DISCONNECT;
4170
4171 ret = qm_process_dev_error(qm);
4172 if (ret == ACC_ERR_NEED_RESET)
4173 return PCI_ERS_RESULT_NEED_RESET;
4174
4175 return PCI_ERS_RESULT_RECOVERED;
4176}
4177EXPORT_SYMBOL_GPL(hisi_qm_dev_err_detected);
4178
4179static int qm_check_req_recv(struct hisi_qm *qm)
4180{
4181 struct pci_dev *pdev = qm->pdev;
4182 int ret;
4183 u32 val;
4184
4185 if (qm->ver >= QM_HW_V3)
4186 return 0;
4187
4188 writel(ACC_VENDOR_ID_VALUE, addr: qm->io_base + QM_PEH_VENDOR_ID);
4189 ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_VENDOR_ID, val,
4190 (val == ACC_VENDOR_ID_VALUE),
4191 POLL_PERIOD, POLL_TIMEOUT);
4192 if (ret) {
4193 dev_err(&pdev->dev, "Fails to read QM reg!\n");
4194 return ret;
4195 }
4196
4197 writel(PCI_VENDOR_ID_HUAWEI, addr: qm->io_base + QM_PEH_VENDOR_ID);
4198 ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_VENDOR_ID, val,
4199 (val == PCI_VENDOR_ID_HUAWEI),
4200 POLL_PERIOD, POLL_TIMEOUT);
4201 if (ret)
4202 dev_err(&pdev->dev, "Fails to read QM reg in the second time!\n");
4203
4204 return ret;
4205}
4206
4207static int qm_set_pf_mse(struct hisi_qm *qm, bool set)
4208{
4209 struct pci_dev *pdev = qm->pdev;
4210 u16 cmd;
4211 int i;
4212
4213 pci_read_config_word(dev: pdev, PCI_COMMAND, val: &cmd);
4214 if (set)
4215 cmd |= PCI_COMMAND_MEMORY;
4216 else
4217 cmd &= ~PCI_COMMAND_MEMORY;
4218
4219 pci_write_config_word(dev: pdev, PCI_COMMAND, val: cmd);
4220 for (i = 0; i < MAX_WAIT_COUNTS; i++) {
4221 pci_read_config_word(dev: pdev, PCI_COMMAND, val: &cmd);
4222 if (set == ((cmd & PCI_COMMAND_MEMORY) >> 1))
4223 return 0;
4224
4225 udelay(usec: 1);
4226 }
4227
4228 return -ETIMEDOUT;
4229}
4230
4231static int qm_set_vf_mse(struct hisi_qm *qm, bool set)
4232{
4233 struct pci_dev *pdev = qm->pdev;
4234 u16 sriov_ctrl;
4235 int pos;
4236 int i;
4237
4238 /*
4239 * Since function qm_set_vf_mse is called only after SRIOV is enabled,
4240 * pci_find_ext_capability cannot return 0, pos does not need to be
4241 * checked.
4242 */
4243 pos = pci_find_ext_capability(dev: pdev, PCI_EXT_CAP_ID_SRIOV);
4244 pci_read_config_word(dev: pdev, where: pos + PCI_SRIOV_CTRL, val: &sriov_ctrl);
4245 if (set)
4246 sriov_ctrl |= PCI_SRIOV_CTRL_MSE;
4247 else
4248 sriov_ctrl &= ~PCI_SRIOV_CTRL_MSE;
4249 pci_write_config_word(dev: pdev, where: pos + PCI_SRIOV_CTRL, val: sriov_ctrl);
4250
4251 for (i = 0; i < MAX_WAIT_COUNTS; i++) {
4252 pci_read_config_word(dev: pdev, where: pos + PCI_SRIOV_CTRL, val: &sriov_ctrl);
4253 if (set == (sriov_ctrl & PCI_SRIOV_CTRL_MSE) >>
4254 ACC_PEH_SRIOV_CTRL_VF_MSE_SHIFT)
4255 return 0;
4256
4257 udelay(usec: 1);
4258 }
4259
4260 return -ETIMEDOUT;
4261}
4262
4263static void qm_dev_ecc_mbit_handle(struct hisi_qm *qm)
4264{
4265 u32 nfe_enb = 0;
4266
4267 /* Kunpeng930 hardware automatically close master ooo when NFE occurs */
4268 if (qm->ver >= QM_HW_V3)
4269 return;
4270
4271 if (!qm->err_status.is_dev_ecc_mbit &&
4272 qm->err_status.is_qm_ecc_mbit &&
4273 qm->err_ini->close_axi_master_ooo) {
4274 qm->err_ini->close_axi_master_ooo(qm);
4275 } else if (qm->err_status.is_dev_ecc_mbit &&
4276 !qm->err_status.is_qm_ecc_mbit &&
4277 !qm->err_ini->close_axi_master_ooo) {
4278 nfe_enb = readl(addr: qm->io_base + QM_RAS_NFE_ENABLE);
4279 writel(val: nfe_enb & ~qm->err_info.qm_err.ecc_2bits_mask,
4280 addr: qm->io_base + QM_RAS_NFE_ENABLE);
4281 writel(val: qm->err_info.qm_err.ecc_2bits_mask, addr: qm->io_base + QM_ABNORMAL_INT_SET);
4282 }
4283}
4284
4285static int qm_vf_reset_prepare(struct hisi_qm *qm,
4286 enum qm_stop_reason stop_reason)
4287{
4288 struct hisi_qm_list *qm_list = qm->qm_list;
4289 struct pci_dev *pdev = qm->pdev;
4290 struct pci_dev *virtfn;
4291 struct hisi_qm *vf_qm;
4292 int ret = 0;
4293
4294 mutex_lock(&qm_list->lock);
4295 list_for_each_entry(vf_qm, &qm_list->list, list) {
4296 virtfn = vf_qm->pdev;
4297 if (virtfn == pdev)
4298 continue;
4299
4300 if (pci_physfn(dev: virtfn) == pdev) {
4301 /* save VFs PCIE BAR configuration */
4302 pci_save_state(dev: virtfn);
4303
4304 ret = hisi_qm_stop(vf_qm, stop_reason);
4305 if (ret)
4306 goto stop_fail;
4307 }
4308 }
4309
4310stop_fail:
4311 mutex_unlock(lock: &qm_list->lock);
4312 return ret;
4313}
4314
4315static int qm_try_stop_vfs(struct hisi_qm *qm, enum qm_ifc_cmd cmd,
4316 enum qm_stop_reason stop_reason)
4317{
4318 struct pci_dev *pdev = qm->pdev;
4319 int ret;
4320
4321 if (!qm->vfs_num)
4322 return 0;
4323
4324 /* Kunpeng930 supports to notify VFs to stop before PF reset */
4325 if (test_bit(QM_SUPPORT_MB_COMMAND, &qm->caps)) {
4326 ret = qm_ping_all_vfs(qm, cmd);
4327 if (ret)
4328 pci_err(pdev, "failed to send command to all VFs before PF reset!\n");
4329 } else {
4330 ret = qm_vf_reset_prepare(qm, stop_reason);
4331 if (ret)
4332 pci_err(pdev, "failed to prepare reset, ret = %d.\n", ret);
4333 }
4334
4335 return ret;
4336}
4337
4338static int qm_controller_reset_prepare(struct hisi_qm *qm)
4339{
4340 struct pci_dev *pdev = qm->pdev;
4341 int ret;
4342
4343 if (qm->err_ini->set_priv_status) {
4344 ret = qm->err_ini->set_priv_status(qm);
4345 if (ret)
4346 return ret;
4347 }
4348
4349 ret = qm_reset_prepare_ready(qm);
4350 if (ret) {
4351 pci_err(pdev, "Controller reset not ready!\n");
4352 return ret;
4353 }
4354
4355 qm_dev_ecc_mbit_handle(qm);
4356
4357 /* PF obtains the information of VF by querying the register. */
4358 qm_cmd_uninit(qm);
4359
4360 /* Whether VFs stop successfully, soft reset will continue. */
4361 ret = qm_try_stop_vfs(qm, cmd: QM_PF_SRST_PREPARE, stop_reason: QM_SOFT_RESET);
4362 if (ret)
4363 pci_err(pdev, "failed to stop vfs by pf in soft reset.\n");
4364
4365 ret = hisi_qm_stop(qm, QM_SOFT_RESET);
4366 if (ret) {
4367 pci_err(pdev, "Fails to stop QM!\n");
4368 qm_reset_bit_clear(qm);
4369 return ret;
4370 }
4371
4372 if (qm->use_sva) {
4373 ret = qm_hw_err_isolate(qm);
4374 if (ret)
4375 pci_err(pdev, "failed to isolate hw err!\n");
4376 }
4377
4378 ret = qm_wait_vf_prepare_finish(qm);
4379 if (ret)
4380 pci_err(pdev, "failed to stop by vfs in soft reset!\n");
4381
4382 clear_bit(nr: QM_RST_SCHED, addr: &qm->misc_ctl);
4383
4384 return 0;
4385}
4386
4387static int qm_master_ooo_check(struct hisi_qm *qm)
4388{
4389 u32 val;
4390 int ret;
4391
4392 /* Check the ooo register of the device before resetting the device. */
4393 writel(ACC_MASTER_GLOBAL_CTRL_SHUTDOWN, addr: qm->io_base + ACC_MASTER_GLOBAL_CTRL);
4394 ret = readl_relaxed_poll_timeout(qm->io_base + ACC_MASTER_TRANS_RETURN,
4395 val, (val == ACC_MASTER_TRANS_RETURN_RW),
4396 POLL_PERIOD, POLL_TIMEOUT);
4397 if (ret)
4398 pci_warn(qm->pdev, "Bus lock! Please reset system.\n");
4399
4400 return ret;
4401}
4402
4403static int qm_soft_reset_prepare(struct hisi_qm *qm)
4404{
4405 struct pci_dev *pdev = qm->pdev;
4406 int ret;
4407
4408 /* Ensure all doorbells and mailboxes received by QM */
4409 ret = qm_check_req_recv(qm);
4410 if (ret)
4411 return ret;
4412
4413 if (qm->vfs_num) {
4414 ret = qm_set_vf_mse(qm, set: false);
4415 if (ret) {
4416 pci_err(pdev, "Fails to disable vf MSE bit.\n");
4417 return ret;
4418 }
4419 }
4420
4421 ret = qm->ops->set_msi(qm, false);
4422 if (ret) {
4423 pci_err(pdev, "Fails to disable PEH MSI bit.\n");
4424 return ret;
4425 }
4426
4427 ret = qm_master_ooo_check(qm);
4428 if (ret)
4429 return ret;
4430
4431 if (qm->err_ini->close_sva_prefetch)
4432 qm->err_ini->close_sva_prefetch(qm);
4433
4434 ret = qm_set_pf_mse(qm, set: false);
4435 if (ret)
4436 pci_err(pdev, "Fails to disable pf MSE bit.\n");
4437
4438 return ret;
4439}
4440
4441static int qm_reset_device(struct hisi_qm *qm)
4442{
4443 struct pci_dev *pdev = qm->pdev;
4444
4445 /* The reset related sub-control registers are not in PCI BAR */
4446 if (ACPI_HANDLE(&pdev->dev)) {
4447 unsigned long long value = 0;
4448 acpi_status s;
4449
4450 s = acpi_evaluate_integer(ACPI_HANDLE(&pdev->dev),
4451 pathname: qm->err_info.acpi_rst,
4452 NULL, data: &value);
4453 if (ACPI_FAILURE(s)) {
4454 pci_err(pdev, "NO controller reset method!\n");
4455 return -EIO;
4456 }
4457
4458 if (value) {
4459 pci_err(pdev, "Reset step %llu failed!\n", value);
4460 return -EIO;
4461 }
4462
4463 return 0;
4464 }
4465
4466 pci_err(pdev, "No reset method!\n");
4467 return -EINVAL;
4468}
4469
4470static int qm_soft_reset(struct hisi_qm *qm)
4471{
4472 int ret;
4473
4474 ret = qm_soft_reset_prepare(qm);
4475 if (ret)
4476 return ret;
4477
4478 return qm_reset_device(qm);
4479}
4480
4481static int qm_vf_reset_done(struct hisi_qm *qm)
4482{
4483 struct hisi_qm_list *qm_list = qm->qm_list;
4484 struct pci_dev *pdev = qm->pdev;
4485 struct pci_dev *virtfn;
4486 struct hisi_qm *vf_qm;
4487 int ret = 0;
4488
4489 mutex_lock(&qm_list->lock);
4490 list_for_each_entry(vf_qm, &qm_list->list, list) {
4491 virtfn = vf_qm->pdev;
4492 if (virtfn == pdev)
4493 continue;
4494
4495 if (pci_physfn(dev: virtfn) == pdev) {
4496 /* enable VFs PCIE BAR configuration */
4497 pci_restore_state(dev: virtfn);
4498
4499 ret = qm_restart(qm: vf_qm);
4500 if (ret)
4501 goto restart_fail;
4502 }
4503 }
4504
4505restart_fail:
4506 mutex_unlock(lock: &qm_list->lock);
4507 return ret;
4508}
4509
4510static int qm_try_start_vfs(struct hisi_qm *qm, enum qm_ifc_cmd cmd)
4511{
4512 struct pci_dev *pdev = qm->pdev;
4513 int ret;
4514
4515 if (!qm->vfs_num)
4516 return 0;
4517
4518 ret = qm_vf_q_assign(qm, num_vfs: qm->vfs_num);
4519 if (ret) {
4520 pci_err(pdev, "failed to assign VFs, ret = %d.\n", ret);
4521 return ret;
4522 }
4523
4524 /* Kunpeng930 supports to notify VFs to start after PF reset. */
4525 if (test_bit(QM_SUPPORT_MB_COMMAND, &qm->caps)) {
4526 ret = qm_ping_all_vfs(qm, cmd);
4527 if (ret)
4528 pci_warn(pdev, "failed to send cmd to all VFs after PF reset!\n");
4529 } else {
4530 ret = qm_vf_reset_done(qm);
4531 if (ret)
4532 pci_warn(pdev, "failed to start vfs, ret = %d.\n", ret);
4533 }
4534
4535 return ret;
4536}
4537
4538static int qm_dev_hw_init(struct hisi_qm *qm)
4539{
4540 return qm->err_ini->hw_init(qm);
4541}
4542
4543static void qm_restart_prepare(struct hisi_qm *qm)
4544{
4545 u32 value;
4546
4547 if (qm->ver >= QM_HW_V3)
4548 return;
4549
4550 if (!qm->err_status.is_qm_ecc_mbit &&
4551 !qm->err_status.is_dev_ecc_mbit)
4552 return;
4553
4554 /* temporarily close the OOO port used for PEH to write out MSI */
4555 value = readl(addr: qm->io_base + ACC_AM_CFG_PORT_WR_EN);
4556 writel(val: value & ~qm->err_info.msi_wr_port,
4557 addr: qm->io_base + ACC_AM_CFG_PORT_WR_EN);
4558
4559 /* clear dev ecc 2bit error source if having */
4560 value = qm_get_dev_err_status(qm) & qm->err_info.dev_err.ecc_2bits_mask;
4561 if (value && qm->err_ini->clear_dev_hw_err_status)
4562 qm->err_ini->clear_dev_hw_err_status(qm, value);
4563
4564 /* clear QM ecc mbit error source */
4565 writel(val: qm->err_info.qm_err.ecc_2bits_mask, addr: qm->io_base + QM_ABNORMAL_INT_SOURCE);
4566
4567 /* clear AM Reorder Buffer ecc mbit source */
4568 writel(ACC_ROB_ECC_ERR_MULTPL, addr: qm->io_base + ACC_AM_ROB_ECC_INT_STS);
4569}
4570
4571static void qm_restart_done(struct hisi_qm *qm)
4572{
4573 u32 value;
4574
4575 if (qm->ver >= QM_HW_V3)
4576 goto clear_flags;
4577
4578 if (!qm->err_status.is_qm_ecc_mbit &&
4579 !qm->err_status.is_dev_ecc_mbit)
4580 return;
4581
4582 /* open the OOO port for PEH to write out MSI */
4583 value = readl(addr: qm->io_base + ACC_AM_CFG_PORT_WR_EN);
4584 value |= qm->err_info.msi_wr_port;
4585 writel(val: value, addr: qm->io_base + ACC_AM_CFG_PORT_WR_EN);
4586
4587clear_flags:
4588 qm->err_status.is_qm_ecc_mbit = false;
4589 qm->err_status.is_dev_ecc_mbit = false;
4590}
4591
4592static void qm_disable_axi_error(struct hisi_qm *qm)
4593{
4594 struct hisi_qm_err_mask *qm_err = &qm->err_info.qm_err;
4595 u32 val;
4596
4597 val = ~(qm->error_mask & (~QM_RAS_AXI_ERROR));
4598 writel(val, addr: qm->io_base + QM_ABNORMAL_INT_MASK);
4599 if (qm->ver > QM_HW_V2)
4600 writel(val: qm_err->shutdown_mask & (~QM_RAS_AXI_ERROR),
4601 addr: qm->io_base + QM_OOO_SHUTDOWN_SEL);
4602
4603 if (qm->err_ini->disable_axi_error)
4604 qm->err_ini->disable_axi_error(qm);
4605}
4606
4607static void qm_enable_axi_error(struct hisi_qm *qm)
4608{
4609 /* clear axi error source */
4610 writel(QM_RAS_AXI_ERROR, addr: qm->io_base + QM_ABNORMAL_INT_SOURCE);
4611
4612 writel(val: ~qm->error_mask, addr: qm->io_base + QM_ABNORMAL_INT_MASK);
4613 if (qm->ver > QM_HW_V2)
4614 writel(val: qm->err_info.qm_err.shutdown_mask, addr: qm->io_base + QM_OOO_SHUTDOWN_SEL);
4615
4616 if (qm->err_ini->enable_axi_error)
4617 qm->err_ini->enable_axi_error(qm);
4618}
4619
4620static int qm_controller_reset_done(struct hisi_qm *qm)
4621{
4622 struct pci_dev *pdev = qm->pdev;
4623 int ret;
4624
4625 ret = qm->ops->set_msi(qm, true);
4626 if (ret) {
4627 pci_err(pdev, "Fails to enable PEH MSI bit!\n");
4628 return ret;
4629 }
4630
4631 ret = qm_set_pf_mse(qm, set: true);
4632 if (ret) {
4633 pci_err(pdev, "Fails to enable pf MSE bit!\n");
4634 return ret;
4635 }
4636
4637 if (qm->vfs_num) {
4638 ret = qm_set_vf_mse(qm, set: true);
4639 if (ret) {
4640 pci_err(pdev, "Fails to enable vf MSE bit!\n");
4641 return ret;
4642 }
4643 }
4644
4645 ret = qm_dev_hw_init(qm);
4646 if (ret) {
4647 pci_err(pdev, "Failed to init device\n");
4648 return ret;
4649 }
4650
4651 qm_restart_prepare(qm);
4652 hisi_qm_dev_err_init(qm);
4653 qm_disable_axi_error(qm);
4654 if (qm->err_ini->open_axi_master_ooo)
4655 qm->err_ini->open_axi_master_ooo(qm);
4656
4657 ret = qm_dev_mem_reset(qm);
4658 if (ret) {
4659 pci_err(pdev, "failed to reset device memory\n");
4660 return ret;
4661 }
4662
4663 ret = qm_restart(qm);
4664 if (ret) {
4665 pci_err(pdev, "Failed to start QM!\n");
4666 return ret;
4667 }
4668
4669 ret = qm_try_start_vfs(qm, cmd: QM_PF_RESET_DONE);
4670 if (ret)
4671 pci_err(pdev, "failed to start vfs by pf in soft reset.\n");
4672
4673 ret = qm_wait_vf_prepare_finish(qm);
4674 if (ret)
4675 pci_err(pdev, "failed to start by vfs in soft reset!\n");
4676 qm_enable_axi_error(qm);
4677 qm_cmd_init(qm);
4678 qm_restart_done(qm);
4679
4680 qm_reset_bit_clear(qm);
4681
4682 return 0;
4683}
4684
4685static int qm_controller_reset(struct hisi_qm *qm)
4686{
4687 struct pci_dev *pdev = qm->pdev;
4688 int ret;
4689
4690 pci_info(pdev, "Controller resetting...\n");
4691
4692 ret = qm_controller_reset_prepare(qm);
4693 if (ret) {
4694 hisi_qm_set_hw_reset(qm, QM_RESET_STOP_TX_OFFSET);
4695 hisi_qm_set_hw_reset(qm, QM_RESET_STOP_RX_OFFSET);
4696 clear_bit(nr: QM_RST_SCHED, addr: &qm->misc_ctl);
4697 return ret;
4698 }
4699
4700 hisi_qm_show_last_dfx_regs(qm);
4701 if (qm->err_ini->show_last_dfx_regs)
4702 qm->err_ini->show_last_dfx_regs(qm);
4703
4704 ret = qm_soft_reset(qm);
4705 if (ret)
4706 goto err_reset;
4707
4708 ret = qm_controller_reset_done(qm);
4709 if (ret)
4710 goto err_reset;
4711
4712 pci_info(pdev, "Controller reset complete\n");
4713
4714 return 0;
4715
4716err_reset:
4717 pci_err(pdev, "Controller reset failed (%d)\n", ret);
4718 qm_reset_bit_clear(qm);
4719
4720 /* if resetting fails, isolate the device */
4721 if (qm->use_sva)
4722 qm->isolate_data.is_isolate = true;
4723 return ret;
4724}
4725
4726/**
4727 * hisi_qm_dev_slot_reset() - slot reset
4728 * @pdev: the PCIe device
4729 *
4730 * This function offers QM relate PCIe device reset interface. Drivers which
4731 * use QM can use this function as slot_reset in its struct pci_error_handlers.
4732 */
4733pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev)
4734{
4735 struct hisi_qm *qm = pci_get_drvdata(pdev);
4736 int ret;
4737
4738 if (pdev->is_virtfn)
4739 return PCI_ERS_RESULT_RECOVERED;
4740
4741 /* reset pcie device controller */
4742 ret = qm_controller_reset(qm);
4743 if (ret) {
4744 pci_err(pdev, "Controller reset failed (%d)\n", ret);
4745 return PCI_ERS_RESULT_DISCONNECT;
4746 }
4747
4748 return PCI_ERS_RESULT_RECOVERED;
4749}
4750EXPORT_SYMBOL_GPL(hisi_qm_dev_slot_reset);
4751
4752void hisi_qm_reset_prepare(struct pci_dev *pdev)
4753{
4754 struct hisi_qm *pf_qm = pci_get_drvdata(pdev: pci_physfn(dev: pdev));
4755 struct hisi_qm *qm = pci_get_drvdata(pdev);
4756 u32 delay = 0;
4757 int ret;
4758
4759 hisi_qm_dev_err_uninit(pf_qm);
4760
4761 /*
4762 * Check whether there is an ECC mbit error, If it occurs, need to
4763 * wait for soft reset to fix it.
4764 */
4765 while (qm_check_dev_error(qm)) {
4766 msleep(msecs: ++delay);
4767 if (delay > QM_RESET_WAIT_TIMEOUT)
4768 return;
4769 }
4770
4771 ret = qm_reset_prepare_ready(qm);
4772 if (ret) {
4773 pci_err(pdev, "FLR not ready!\n");
4774 return;
4775 }
4776
4777 /* PF obtains the information of VF by querying the register. */
4778 if (qm->fun_type == QM_HW_PF)
4779 qm_cmd_uninit(qm);
4780
4781 ret = qm_try_stop_vfs(qm, cmd: QM_PF_FLR_PREPARE, stop_reason: QM_DOWN);
4782 if (ret)
4783 pci_err(pdev, "failed to stop vfs by pf in FLR.\n");
4784
4785 ret = hisi_qm_stop(qm, QM_DOWN);
4786 if (ret) {
4787 pci_err(pdev, "Failed to stop QM, ret = %d.\n", ret);
4788 hisi_qm_set_hw_reset(qm, QM_RESET_STOP_TX_OFFSET);
4789 hisi_qm_set_hw_reset(qm, QM_RESET_STOP_RX_OFFSET);
4790 return;
4791 }
4792
4793 ret = qm_wait_vf_prepare_finish(qm);
4794 if (ret)
4795 pci_err(pdev, "failed to stop by vfs in FLR!\n");
4796
4797 pci_info(pdev, "FLR resetting...\n");
4798}
4799EXPORT_SYMBOL_GPL(hisi_qm_reset_prepare);
4800
4801static bool qm_flr_reset_complete(struct pci_dev *pdev)
4802{
4803 struct pci_dev *pf_pdev = pci_physfn(dev: pdev);
4804 struct hisi_qm *qm = pci_get_drvdata(pdev: pf_pdev);
4805 u32 id;
4806
4807 pci_read_config_dword(dev: qm->pdev, PCI_COMMAND, val: &id);
4808 if (id == QM_PCI_COMMAND_INVALID) {
4809 pci_err(pdev, "Device can not be used!\n");
4810 return false;
4811 }
4812
4813 return true;
4814}
4815
4816void hisi_qm_reset_done(struct pci_dev *pdev)
4817{
4818 struct hisi_qm *pf_qm = pci_get_drvdata(pdev: pci_physfn(dev: pdev));
4819 struct hisi_qm *qm = pci_get_drvdata(pdev);
4820 int ret;
4821
4822 if (qm->fun_type == QM_HW_PF) {
4823 ret = qm_dev_hw_init(qm);
4824 if (ret) {
4825 pci_err(pdev, "Failed to init PF, ret = %d.\n", ret);
4826 goto flr_done;
4827 }
4828 }
4829
4830 hisi_qm_dev_err_init(pf_qm);
4831
4832 ret = qm_restart(qm);
4833 if (ret) {
4834 pci_err(pdev, "Failed to start QM, ret = %d.\n", ret);
4835 goto flr_done;
4836 }
4837
4838 ret = qm_try_start_vfs(qm, cmd: QM_PF_RESET_DONE);
4839 if (ret)
4840 pci_err(pdev, "failed to start vfs by pf in FLR.\n");
4841
4842 ret = qm_wait_vf_prepare_finish(qm);
4843 if (ret)
4844 pci_err(pdev, "failed to start by vfs in FLR!\n");
4845
4846flr_done:
4847 if (qm->fun_type == QM_HW_PF)
4848 qm_cmd_init(qm);
4849
4850 if (qm_flr_reset_complete(pdev))
4851 pci_info(pdev, "FLR reset complete\n");
4852
4853 qm_reset_bit_clear(qm);
4854}
4855EXPORT_SYMBOL_GPL(hisi_qm_reset_done);
4856
4857static irqreturn_t qm_rsvd_irq(int irq, void *data)
4858{
4859 struct hisi_qm *qm = data;
4860
4861 dev_info(&qm->pdev->dev, "Reserved interrupt, ignore!\n");
4862
4863 return IRQ_HANDLED;
4864}
4865
4866static irqreturn_t qm_abnormal_irq(int irq, void *data)
4867{
4868 struct hisi_qm *qm = data;
4869 enum acc_err_result ret;
4870
4871 atomic64_inc(v: &qm->debug.dfx.abnormal_irq_cnt);
4872 ret = qm_process_dev_error(qm);
4873 if (ret == ACC_ERR_NEED_RESET &&
4874 !test_bit(QM_DRIVER_REMOVING, &qm->misc_ctl) &&
4875 !test_and_set_bit(nr: QM_RST_SCHED, addr: &qm->misc_ctl))
4876 schedule_work(work: &qm->rst_work);
4877
4878 return IRQ_HANDLED;
4879}
4880
4881/**
4882 * hisi_qm_dev_shutdown() - Shutdown device.
4883 * @pdev: The device will be shutdown.
4884 *
4885 * This function will stop qm when OS shutdown or rebooting.
4886 */
4887void hisi_qm_dev_shutdown(struct pci_dev *pdev)
4888{
4889 struct hisi_qm *qm = pci_get_drvdata(pdev);
4890 int ret;
4891
4892 ret = hisi_qm_stop(qm, QM_DOWN);
4893 if (ret)
4894 dev_err(&pdev->dev, "Fail to stop qm in shutdown!\n");
4895}
4896EXPORT_SYMBOL_GPL(hisi_qm_dev_shutdown);
4897
4898static void hisi_qm_controller_reset(struct work_struct *rst_work)
4899{
4900 struct hisi_qm *qm = container_of(rst_work, struct hisi_qm, rst_work);
4901 int ret;
4902
4903 ret = qm_pm_get_sync(qm);
4904 if (ret) {
4905 clear_bit(nr: QM_RST_SCHED, addr: &qm->misc_ctl);
4906 return;
4907 }
4908
4909 /* reset pcie device controller */
4910 ret = qm_controller_reset(qm);
4911 if (ret)
4912 dev_err(&qm->pdev->dev, "controller reset failed (%d)\n", ret);
4913
4914 qm_pm_put_sync(qm);
4915}
4916
4917static void qm_pf_reset_vf_prepare(struct hisi_qm *qm,
4918 enum qm_stop_reason stop_reason)
4919{
4920 enum qm_ifc_cmd cmd = QM_VF_PREPARE_DONE;
4921 struct pci_dev *pdev = qm->pdev;
4922 int ret;
4923
4924 ret = qm_reset_prepare_ready(qm);
4925 if (ret) {
4926 dev_err(&pdev->dev, "reset prepare not ready!\n");
4927 atomic_set(v: &qm->status.flags, i: QM_STOP);
4928 cmd = QM_VF_PREPARE_FAIL;
4929 goto err_prepare;
4930 }
4931
4932 ret = hisi_qm_stop(qm, stop_reason);
4933 if (ret) {
4934 dev_err(&pdev->dev, "failed to stop QM, ret = %d.\n", ret);
4935 atomic_set(v: &qm->status.flags, i: QM_STOP);
4936 cmd = QM_VF_PREPARE_FAIL;
4937 goto err_prepare;
4938 } else {
4939 goto out;
4940 }
4941
4942err_prepare:
4943 hisi_qm_set_hw_reset(qm, QM_RESET_STOP_TX_OFFSET);
4944 hisi_qm_set_hw_reset(qm, QM_RESET_STOP_RX_OFFSET);
4945out:
4946 pci_save_state(dev: pdev);
4947 ret = qm_ping_pf(qm, cmd);
4948 if (ret)
4949 dev_warn(&pdev->dev, "PF responds timeout in reset prepare!\n");
4950}
4951
4952static void qm_pf_reset_vf_done(struct hisi_qm *qm)
4953{
4954 enum qm_ifc_cmd cmd = QM_VF_START_DONE;
4955 struct pci_dev *pdev = qm->pdev;
4956 int ret;
4957
4958 pci_restore_state(dev: pdev);
4959 ret = hisi_qm_start(qm);
4960 if (ret) {
4961 dev_err(&pdev->dev, "failed to start QM, ret = %d.\n", ret);
4962 cmd = QM_VF_START_FAIL;
4963 }
4964
4965 qm_cmd_init(qm);
4966 ret = qm_ping_pf(qm, cmd);
4967 if (ret)
4968 dev_warn(&pdev->dev, "PF responds timeout in reset done!\n");
4969
4970 qm_reset_bit_clear(qm);
4971}
4972
4973static int qm_wait_pf_reset_finish(struct hisi_qm *qm)
4974{
4975 struct device *dev = &qm->pdev->dev;
4976 u32 val, cmd;
4977 int ret;
4978
4979 /* Wait for reset to finish */
4980 ret = readl_relaxed_poll_timeout(qm->io_base + QM_IFC_INT_SOURCE_V, val,
4981 val == BIT(0), QM_VF_RESET_WAIT_US,
4982 QM_VF_RESET_WAIT_TIMEOUT_US);
4983 /* hardware completion status should be available by this time */
4984 if (ret) {
4985 dev_err(dev, "couldn't get reset done status from PF, timeout!\n");
4986 return -ETIMEDOUT;
4987 }
4988
4989 /*
4990 * Whether message is got successfully,
4991 * VF needs to ack PF by clearing the interrupt.
4992 */
4993 ret = qm->ops->get_ifc(qm, &cmd, NULL, 0);
4994 qm_clear_cmd_interrupt(qm, vf_mask: 0);
4995 if (ret) {
4996 dev_err(dev, "failed to get command from PF in reset done!\n");
4997 return ret;
4998 }
4999
5000 if (cmd != QM_PF_RESET_DONE) {
5001 dev_err(dev, "the command(0x%x) is not reset done!\n", cmd);
5002 ret = -EINVAL;
5003 }
5004
5005 return ret;
5006}
5007
5008static void qm_pf_reset_vf_process(struct hisi_qm *qm,
5009 enum qm_stop_reason stop_reason)
5010{
5011 struct device *dev = &qm->pdev->dev;
5012 int ret;
5013
5014 dev_info(dev, "device reset start...\n");
5015
5016 /* The message is obtained by querying the register during resetting */
5017 qm_cmd_uninit(qm);
5018 qm_pf_reset_vf_prepare(qm, stop_reason);
5019
5020 ret = qm_wait_pf_reset_finish(qm);
5021 if (ret)
5022 goto err_get_status;
5023
5024 qm_pf_reset_vf_done(qm);
5025
5026 dev_info(dev, "device reset done.\n");
5027
5028 return;
5029
5030err_get_status:
5031 qm_cmd_init(qm);
5032 qm_reset_bit_clear(qm);
5033}
5034
5035static void qm_handle_cmd_msg(struct hisi_qm *qm, u32 fun_num)
5036{
5037 struct device *dev = &qm->pdev->dev;
5038 enum qm_ifc_cmd cmd;
5039 u32 data;
5040 int ret;
5041
5042 /*
5043 * Get the msg from source by sending mailbox. Whether message is got
5044 * successfully, destination needs to ack source by clearing the interrupt.
5045 */
5046 ret = qm->ops->get_ifc(qm, &cmd, &data, fun_num);
5047 qm_clear_cmd_interrupt(qm, BIT(fun_num));
5048 if (ret) {
5049 dev_err(dev, "failed to get command from source!\n");
5050 return;
5051 }
5052
5053 switch (cmd) {
5054 case QM_PF_FLR_PREPARE:
5055 qm_pf_reset_vf_process(qm, stop_reason: QM_DOWN);
5056 break;
5057 case QM_PF_SRST_PREPARE:
5058 qm_pf_reset_vf_process(qm, stop_reason: QM_SOFT_RESET);
5059 break;
5060 case QM_VF_GET_QOS:
5061 qm_vf_get_qos(qm, fun_num);
5062 break;
5063 case QM_PF_SET_QOS:
5064 qm->mb_qos = data;
5065 break;
5066 default:
5067 dev_err(dev, "unsupported command(0x%x) sent by function(%u)!\n", cmd, fun_num);
5068 break;
5069 }
5070}
5071
5072static void qm_cmd_process(struct work_struct *cmd_process)
5073{
5074 struct hisi_qm *qm = container_of(cmd_process,
5075 struct hisi_qm, cmd_process);
5076 u32 vfs_num = qm->vfs_num;
5077 u64 val;
5078 u32 i;
5079
5080 if (qm->fun_type == QM_HW_PF) {
5081 val = readq(addr: qm->io_base + QM_IFC_INT_SOURCE_P);
5082 if (!val)
5083 return;
5084
5085 for (i = 1; i <= vfs_num; i++) {
5086 if (val & BIT(i))
5087 qm_handle_cmd_msg(qm, fun_num: i);
5088 }
5089
5090 return;
5091 }
5092
5093 qm_handle_cmd_msg(qm, fun_num: 0);
5094}
5095
5096/**
5097 * hisi_qm_alg_register() - Register alg to crypto.
5098 * @qm: The qm needs add.
5099 * @qm_list: The qm list.
5100 * @guard: Guard of qp_num.
5101 *
5102 * Register algorithm to crypto when the function is satisfy guard.
5103 */
5104int hisi_qm_alg_register(struct hisi_qm *qm, struct hisi_qm_list *qm_list, int guard)
5105{
5106 struct device *dev = &qm->pdev->dev;
5107
5108 if (qm->ver <= QM_HW_V2 && qm->use_sva) {
5109 dev_info(dev, "HW V2 not both use uacce sva mode and hardware crypto algs.\n");
5110 return 0;
5111 }
5112
5113 if (qm->qp_num < guard) {
5114 dev_info(dev, "qp_num is less than task need.\n");
5115 return 0;
5116 }
5117
5118 return qm_list->register_to_crypto(qm);
5119}
5120EXPORT_SYMBOL_GPL(hisi_qm_alg_register);
5121
5122/**
5123 * hisi_qm_alg_unregister() - Unregister alg from crypto.
5124 * @qm: The qm needs delete.
5125 * @qm_list: The qm list.
5126 * @guard: Guard of qp_num.
5127 *
5128 * Unregister algorithm from crypto when the last function is satisfy guard.
5129 */
5130void hisi_qm_alg_unregister(struct hisi_qm *qm, struct hisi_qm_list *qm_list, int guard)
5131{
5132 if (qm->ver <= QM_HW_V2 && qm->use_sva)
5133 return;
5134
5135 if (qm->qp_num < guard)
5136 return;
5137
5138 qm_list->unregister_from_crypto(qm);
5139}
5140EXPORT_SYMBOL_GPL(hisi_qm_alg_unregister);
5141
5142static void qm_unregister_abnormal_irq(struct hisi_qm *qm)
5143{
5144 struct pci_dev *pdev = qm->pdev;
5145 u32 irq_vector, val;
5146
5147 if (qm->fun_type == QM_HW_VF && qm->ver < QM_HW_V3)
5148 return;
5149
5150 val = qm->cap_tables.qm_cap_table[QM_ABNORMAL_IRQ].cap_val;
5151 if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_ABN_IRQ_TYPE_MASK))
5152 return;
5153
5154 irq_vector = val & QM_IRQ_VECTOR_MASK;
5155 free_irq(pci_irq_vector(dev: pdev, nr: irq_vector), qm);
5156}
5157
5158static int qm_register_abnormal_irq(struct hisi_qm *qm)
5159{
5160 struct pci_dev *pdev = qm->pdev;
5161 u32 irq_vector, val;
5162 int ret;
5163
5164 val = qm->cap_tables.qm_cap_table[QM_ABNORMAL_IRQ].cap_val;
5165 if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_ABN_IRQ_TYPE_MASK))
5166 return 0;
5167 irq_vector = val & QM_IRQ_VECTOR_MASK;
5168
5169 /* For VF, this is a reserved interrupt in V3 version. */
5170 if (qm->fun_type == QM_HW_VF) {
5171 if (qm->ver < QM_HW_V3)
5172 return 0;
5173
5174 ret = request_irq(irq: pci_irq_vector(dev: pdev, nr: irq_vector), handler: qm_rsvd_irq,
5175 IRQF_NO_AUTOEN, name: qm->dev_name, dev: qm);
5176 if (ret) {
5177 dev_err(&pdev->dev, "failed to request reserved irq, ret = %d!\n", ret);
5178 return ret;
5179 }
5180 return 0;
5181 }
5182
5183 ret = request_irq(irq: pci_irq_vector(dev: pdev, nr: irq_vector), handler: qm_abnormal_irq, flags: 0, name: qm->dev_name, dev: qm);
5184 if (ret)
5185 dev_err(&qm->pdev->dev, "failed to request abnormal irq, ret = %d!\n", ret);
5186
5187 return ret;
5188}
5189
5190static void qm_unregister_mb_cmd_irq(struct hisi_qm *qm)
5191{
5192 struct pci_dev *pdev = qm->pdev;
5193 u32 irq_vector, val;
5194
5195 val = qm->cap_tables.qm_cap_table[QM_MB_IRQ].cap_val;
5196 if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK))
5197 return;
5198
5199 irq_vector = val & QM_IRQ_VECTOR_MASK;
5200 free_irq(pci_irq_vector(dev: pdev, nr: irq_vector), qm);
5201}
5202
5203static int qm_register_mb_cmd_irq(struct hisi_qm *qm)
5204{
5205 struct pci_dev *pdev = qm->pdev;
5206 u32 irq_vector, val;
5207 int ret;
5208
5209 val = qm->cap_tables.qm_cap_table[QM_MB_IRQ].cap_val;
5210 if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK))
5211 return 0;
5212
5213 irq_vector = val & QM_IRQ_VECTOR_MASK;
5214 ret = request_irq(irq: pci_irq_vector(dev: pdev, nr: irq_vector), handler: qm_mb_cmd_irq, flags: 0, name: qm->dev_name, dev: qm);
5215 if (ret)
5216 dev_err(&pdev->dev, "failed to request function communication irq, ret = %d", ret);
5217
5218 return ret;
5219}
5220
5221static void qm_unregister_aeq_irq(struct hisi_qm *qm)
5222{
5223 struct pci_dev *pdev = qm->pdev;
5224 u32 irq_vector, val;
5225
5226 val = qm->cap_tables.qm_cap_table[QM_AEQ_IRQ].cap_val;
5227 if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK))
5228 return;
5229
5230 irq_vector = val & QM_IRQ_VECTOR_MASK;
5231 free_irq(pci_irq_vector(dev: pdev, nr: irq_vector), qm);
5232}
5233
5234static int qm_register_aeq_irq(struct hisi_qm *qm)
5235{
5236 struct pci_dev *pdev = qm->pdev;
5237 u32 irq_vector, val;
5238 int ret;
5239
5240 val = qm->cap_tables.qm_cap_table[QM_AEQ_IRQ].cap_val;
5241 if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK))
5242 return 0;
5243
5244 irq_vector = val & QM_IRQ_VECTOR_MASK;
5245 ret = request_threaded_irq(irq: pci_irq_vector(dev: pdev, nr: irq_vector), NULL,
5246 thread_fn: qm_aeq_thread, IRQF_ONESHOT, name: qm->dev_name, dev: qm);
5247 if (ret)
5248 dev_err(&pdev->dev, "failed to request eq irq, ret = %d", ret);
5249
5250 return ret;
5251}
5252
5253static void qm_unregister_eq_irq(struct hisi_qm *qm)
5254{
5255 struct pci_dev *pdev = qm->pdev;
5256 u32 irq_vector, val;
5257
5258 val = qm->cap_tables.qm_cap_table[QM_EQ_IRQ].cap_val;
5259 if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK))
5260 return;
5261
5262 irq_vector = val & QM_IRQ_VECTOR_MASK;
5263 free_irq(pci_irq_vector(dev: pdev, nr: irq_vector), qm);
5264}
5265
5266static int qm_register_eq_irq(struct hisi_qm *qm)
5267{
5268 struct pci_dev *pdev = qm->pdev;
5269 u32 irq_vector, val;
5270 int ret;
5271
5272 val = qm->cap_tables.qm_cap_table[QM_EQ_IRQ].cap_val;
5273 if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK))
5274 return 0;
5275
5276 irq_vector = val & QM_IRQ_VECTOR_MASK;
5277 ret = request_irq(irq: pci_irq_vector(dev: pdev, nr: irq_vector), handler: qm_eq_irq, flags: 0, name: qm->dev_name, dev: qm);
5278 if (ret)
5279 dev_err(&pdev->dev, "failed to request eq irq, ret = %d", ret);
5280
5281 return ret;
5282}
5283
5284static void qm_irqs_unregister(struct hisi_qm *qm)
5285{
5286 qm_unregister_mb_cmd_irq(qm);
5287 qm_unregister_abnormal_irq(qm);
5288 qm_unregister_aeq_irq(qm);
5289 qm_unregister_eq_irq(qm);
5290}
5291
5292static int qm_irqs_register(struct hisi_qm *qm)
5293{
5294 int ret;
5295
5296 ret = qm_register_eq_irq(qm);
5297 if (ret)
5298 return ret;
5299
5300 ret = qm_register_aeq_irq(qm);
5301 if (ret)
5302 goto free_eq_irq;
5303
5304 ret = qm_register_abnormal_irq(qm);
5305 if (ret)
5306 goto free_aeq_irq;
5307
5308 ret = qm_register_mb_cmd_irq(qm);
5309 if (ret)
5310 goto free_abnormal_irq;
5311
5312 return 0;
5313
5314free_abnormal_irq:
5315 qm_unregister_abnormal_irq(qm);
5316free_aeq_irq:
5317 qm_unregister_aeq_irq(qm);
5318free_eq_irq:
5319 qm_unregister_eq_irq(qm);
5320 return ret;
5321}
5322
5323static int qm_get_qp_num(struct hisi_qm *qm)
5324{
5325 struct device *dev = &qm->pdev->dev;
5326 bool is_db_isolation;
5327
5328 /* VF's qp_num assigned by PF in v2, and VF can get qp_num by vft. */
5329 if (qm->fun_type == QM_HW_VF) {
5330 if (qm->ver != QM_HW_V1)
5331 /* v2 starts to support get vft by mailbox */
5332 return hisi_qm_get_vft(qm, base: &qm->qp_base, number: &qm->qp_num);
5333
5334 return 0;
5335 }
5336
5337 is_db_isolation = test_bit(QM_SUPPORT_DB_ISOLATION, &qm->caps);
5338 qm->ctrl_qp_num = hisi_qm_get_hw_info(qm, qm_basic_info, QM_TOTAL_QP_NUM_CAP, true);
5339 qm->max_qp_num = hisi_qm_get_hw_info(qm, qm_basic_info,
5340 QM_FUNC_MAX_QP_CAP, is_db_isolation);
5341
5342 if (qm->qp_num <= qm->max_qp_num)
5343 return 0;
5344
5345 if (test_bit(QM_MODULE_PARAM, &qm->misc_ctl)) {
5346 /* Check whether the set qp number is valid */
5347 dev_err(dev, "qp num(%u) is more than max qp num(%u)!\n",
5348 qm->qp_num, qm->max_qp_num);
5349 return -EINVAL;
5350 }
5351
5352 dev_info(dev, "Default qp num(%u) is too big, reset it to Function's max qp num(%u)!\n",
5353 qm->qp_num, qm->max_qp_num);
5354 qm->qp_num = qm->max_qp_num;
5355 qm->debug.curr_qm_qp_num = qm->qp_num;
5356
5357 return 0;
5358}
5359
5360static int qm_pre_store_caps(struct hisi_qm *qm)
5361{
5362 struct hisi_qm_cap_record *qm_cap;
5363 struct pci_dev *pdev = qm->pdev;
5364 size_t i, size;
5365
5366 size = ARRAY_SIZE(qm_cap_query_info);
5367 qm_cap = devm_kcalloc(dev: &pdev->dev, n: sizeof(*qm_cap), size, GFP_KERNEL);
5368 if (!qm_cap)
5369 return -ENOMEM;
5370
5371 for (i = 0; i < size; i++) {
5372 qm_cap[i].type = qm_cap_query_info[i].type;
5373 qm_cap[i].name = qm_cap_query_info[i].name;
5374 qm_cap[i].cap_val = hisi_qm_get_cap_value(qm, qm_cap_query_info,
5375 i, qm->cap_ver);
5376 }
5377
5378 qm->cap_tables.qm_cap_table = qm_cap;
5379 qm->cap_tables.qm_cap_size = size;
5380
5381 return 0;
5382}
5383
5384static int qm_get_hw_caps(struct hisi_qm *qm)
5385{
5386 const struct hisi_qm_cap_info *cap_info = qm->fun_type == QM_HW_PF ?
5387 qm_cap_info_pf : qm_cap_info_vf;
5388 u32 size = qm->fun_type == QM_HW_PF ? ARRAY_SIZE(qm_cap_info_pf) :
5389 ARRAY_SIZE(qm_cap_info_vf);
5390 u32 val, i;
5391
5392 /* Doorbell isolate register is a independent register. */
5393 val = hisi_qm_get_hw_info(qm, qm_cap_info_comm, QM_SUPPORT_DB_ISOLATION, true);
5394 if (val)
5395 set_bit(nr: QM_SUPPORT_DB_ISOLATION, addr: &qm->caps);
5396
5397 if (qm->ver >= QM_HW_V3) {
5398 val = readl(addr: qm->io_base + QM_FUNC_CAPS_REG);
5399 qm->cap_ver = val & QM_CAPBILITY_VERSION;
5400 }
5401
5402 /* Get PF/VF common capbility */
5403 for (i = 1; i < ARRAY_SIZE(qm_cap_info_comm); i++) {
5404 val = hisi_qm_get_hw_info(qm, qm_cap_info_comm, i, qm->cap_ver);
5405 if (val)
5406 set_bit(nr: qm_cap_info_comm[i].type, addr: &qm->caps);
5407 }
5408
5409 /* Get PF/VF different capbility */
5410 for (i = 0; i < size; i++) {
5411 val = hisi_qm_get_hw_info(qm, cap_info, i, qm->cap_ver);
5412 if (val)
5413 set_bit(nr: cap_info[i].type, addr: &qm->caps);
5414 }
5415
5416 /* Fetch and save the value of qm capability registers */
5417 return qm_pre_store_caps(qm);
5418}
5419
5420static void qm_get_version(struct hisi_qm *qm)
5421{
5422 struct pci_dev *pdev = qm->pdev;
5423 u32 sub_version_id;
5424
5425 qm->ver = pdev->revision;
5426
5427 if (pdev->revision == QM_HW_V3) {
5428 sub_version_id = readl(addr: qm->io_base + QM_SUB_VERSION_ID);
5429 if (sub_version_id)
5430 qm->ver = sub_version_id;
5431 }
5432}
5433
5434static int qm_get_pci_res(struct hisi_qm *qm)
5435{
5436 struct pci_dev *pdev = qm->pdev;
5437 struct device *dev = &pdev->dev;
5438 int ret;
5439
5440 ret = pci_request_mem_regions(pdev, name: qm->dev_name);
5441 if (ret < 0) {
5442 dev_err(dev, "Failed to request mem regions!\n");
5443 return ret;
5444 }
5445
5446 qm->phys_base = pci_resource_start(pdev, PCI_BAR_2);
5447 qm->io_base = ioremap(offset: qm->phys_base, pci_resource_len(pdev, PCI_BAR_2));
5448 if (!qm->io_base) {
5449 ret = -EIO;
5450 goto err_request_mem_regions;
5451 }
5452
5453 qm_get_version(qm);
5454
5455 ret = qm_get_hw_caps(qm);
5456 if (ret)
5457 goto err_ioremap;
5458
5459 if (test_bit(QM_SUPPORT_DB_ISOLATION, &qm->caps)) {
5460 qm->db_interval = QM_QP_DB_INTERVAL;
5461 qm->db_phys_base = pci_resource_start(pdev, PCI_BAR_4);
5462 qm->db_io_base = ioremap(offset: qm->db_phys_base,
5463 pci_resource_len(pdev, PCI_BAR_4));
5464 if (!qm->db_io_base) {
5465 ret = -EIO;
5466 goto err_ioremap;
5467 }
5468 } else {
5469 qm->db_phys_base = qm->phys_base;
5470 qm->db_io_base = qm->io_base;
5471 qm->db_interval = 0;
5472 }
5473
5474 hisi_qm_pre_init(qm);
5475 ret = qm_get_qp_num(qm);
5476 if (ret)
5477 goto err_db_ioremap;
5478
5479 return 0;
5480
5481err_db_ioremap:
5482 if (test_bit(QM_SUPPORT_DB_ISOLATION, &qm->caps))
5483 iounmap(addr: qm->db_io_base);
5484err_ioremap:
5485 iounmap(addr: qm->io_base);
5486err_request_mem_regions:
5487 pci_release_mem_regions(pdev);
5488 return ret;
5489}
5490
5491static int qm_clear_device(struct hisi_qm *qm)
5492{
5493 acpi_handle handle = ACPI_HANDLE(&qm->pdev->dev);
5494 int ret;
5495
5496 if (qm->fun_type == QM_HW_VF)
5497 return 0;
5498
5499 /* Device does not support reset, return */
5500 if (!qm->err_ini->err_info_init)
5501 return 0;
5502 qm->err_ini->err_info_init(qm);
5503
5504 if (!handle)
5505 return 0;
5506
5507 /* No reset method, return */
5508 if (!acpi_has_method(handle, name: qm->err_info.acpi_rst))
5509 return 0;
5510
5511 ret = qm_master_ooo_check(qm);
5512 if (ret) {
5513 writel(val: 0x0, addr: qm->io_base + ACC_MASTER_GLOBAL_CTRL);
5514 return ret;
5515 }
5516
5517 if (qm->err_ini->set_priv_status) {
5518 ret = qm->err_ini->set_priv_status(qm);
5519 if (ret) {
5520 writel(val: 0x0, addr: qm->io_base + ACC_MASTER_GLOBAL_CTRL);
5521 return ret;
5522 }
5523 }
5524
5525 return qm_reset_device(qm);
5526}
5527
5528static int hisi_qm_pci_init(struct hisi_qm *qm)
5529{
5530 struct pci_dev *pdev = qm->pdev;
5531 struct device *dev = &pdev->dev;
5532 unsigned int num_vec;
5533 int ret;
5534
5535 ret = pci_enable_device_mem(dev: pdev);
5536 if (ret < 0) {
5537 dev_err(dev, "Failed to enable device mem!\n");
5538 return ret;
5539 }
5540
5541 ret = qm_get_pci_res(qm);
5542 if (ret)
5543 goto err_disable_pcidev;
5544
5545 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
5546 if (ret < 0)
5547 goto err_get_pci_res;
5548 pci_set_master(dev: pdev);
5549
5550 num_vec = qm_get_irq_num(qm);
5551 if (!num_vec) {
5552 dev_err(dev, "Device irq num is zero!\n");
5553 ret = -EINVAL;
5554 goto err_get_pci_res;
5555 }
5556 num_vec = roundup_pow_of_two(num_vec);
5557 ret = pci_alloc_irq_vectors(dev: pdev, min_vecs: num_vec, max_vecs: num_vec, PCI_IRQ_MSI);
5558 if (ret < 0) {
5559 dev_err(dev, "Failed to enable MSI vectors!\n");
5560 goto err_get_pci_res;
5561 }
5562
5563 ret = qm_clear_device(qm);
5564 if (ret)
5565 goto err_free_vectors;
5566
5567 return 0;
5568
5569err_free_vectors:
5570 pci_free_irq_vectors(dev: pdev);
5571err_get_pci_res:
5572 qm_put_pci_res(qm);
5573err_disable_pcidev:
5574 pci_disable_device(dev: pdev);
5575 return ret;
5576}
5577
5578static int hisi_qm_init_work(struct hisi_qm *qm)
5579{
5580 int i;
5581
5582 for (i = 0; i < qm->qp_num; i++)
5583 INIT_WORK(&qm->poll_data[i].work, qm_work_process);
5584
5585 if (qm->fun_type == QM_HW_PF)
5586 INIT_WORK(&qm->rst_work, hisi_qm_controller_reset);
5587
5588 if (qm->ver > QM_HW_V2)
5589 INIT_WORK(&qm->cmd_process, qm_cmd_process);
5590
5591 qm->wq = alloc_workqueue("%s", WQ_HIGHPRI | WQ_MEM_RECLAIM |
5592 WQ_UNBOUND, num_online_cpus(),
5593 pci_name(qm->pdev));
5594 if (!qm->wq) {
5595 pci_err(qm->pdev, "failed to alloc workqueue!\n");
5596 return -ENOMEM;
5597 }
5598
5599 return 0;
5600}
5601
5602static int hisi_qp_alloc_memory(struct hisi_qm *qm)
5603{
5604 struct device *dev = &qm->pdev->dev;
5605 u16 sq_depth, cq_depth;
5606 size_t qp_dma_size;
5607 int i, ret;
5608
5609 qm->qp_array = kcalloc(qm->qp_num, sizeof(struct hisi_qp), GFP_KERNEL);
5610 if (!qm->qp_array)
5611 return -ENOMEM;
5612
5613 qm->poll_data = kcalloc(qm->qp_num, sizeof(struct hisi_qm_poll_data), GFP_KERNEL);
5614 if (!qm->poll_data) {
5615 kfree(objp: qm->qp_array);
5616 return -ENOMEM;
5617 }
5618
5619 qm_get_xqc_depth(qm, low_bits: &sq_depth, high_bits: &cq_depth, type: QM_QP_DEPTH_CAP);
5620
5621 /* one more page for device or qp statuses */
5622 qp_dma_size = qm->sqe_size * sq_depth + sizeof(struct qm_cqe) * cq_depth;
5623 qp_dma_size = PAGE_ALIGN(qp_dma_size) + PAGE_SIZE;
5624 for (i = 0; i < qm->qp_num; i++) {
5625 qm->poll_data[i].qm = qm;
5626 ret = hisi_qp_memory_init(qm, dma_size: qp_dma_size, id: i, sq_depth, cq_depth);
5627 if (ret)
5628 goto err_init_qp_mem;
5629
5630 dev_dbg(dev, "allocate qp dma buf size=%zx)\n", qp_dma_size);
5631 }
5632
5633 return 0;
5634err_init_qp_mem:
5635 hisi_qp_memory_uninit(qm, num: i);
5636
5637 return ret;
5638}
5639
5640static int hisi_qm_alloc_rsv_buf(struct hisi_qm *qm)
5641{
5642 struct qm_rsv_buf *xqc_buf = &qm->xqc_buf;
5643 struct qm_dma *xqc_dma = &xqc_buf->qcdma;
5644 struct device *dev = &qm->pdev->dev;
5645 size_t off = 0;
5646
5647#define QM_XQC_BUF_INIT(xqc_buf, type) do { \
5648 (xqc_buf)->type = ((xqc_buf)->qcdma.va + (off)); \
5649 (xqc_buf)->type##_dma = (xqc_buf)->qcdma.dma + (off); \
5650 off += QMC_ALIGN(sizeof(struct qm_##type)); \
5651} while (0)
5652
5653 xqc_dma->size = QMC_ALIGN(sizeof(struct qm_eqc)) +
5654 QMC_ALIGN(sizeof(struct qm_aeqc)) +
5655 QMC_ALIGN(sizeof(struct qm_sqc)) +
5656 QMC_ALIGN(sizeof(struct qm_cqc));
5657 xqc_dma->va = dma_alloc_coherent(dev, size: xqc_dma->size,
5658 dma_handle: &xqc_dma->dma, GFP_KERNEL);
5659 if (!xqc_dma->va)
5660 return -ENOMEM;
5661
5662 QM_XQC_BUF_INIT(xqc_buf, eqc);
5663 QM_XQC_BUF_INIT(xqc_buf, aeqc);
5664 QM_XQC_BUF_INIT(xqc_buf, sqc);
5665 QM_XQC_BUF_INIT(xqc_buf, cqc);
5666
5667 return 0;
5668}
5669
5670static int hisi_qm_memory_init(struct hisi_qm *qm)
5671{
5672 struct device *dev = &qm->pdev->dev;
5673 int ret, total_func;
5674 size_t off = 0;
5675
5676 if (test_bit(QM_SUPPORT_FUNC_QOS, &qm->caps)) {
5677 total_func = pci_sriov_get_totalvfs(dev: qm->pdev) + 1;
5678 qm->factor = kcalloc(total_func, sizeof(struct qm_shaper_factor), GFP_KERNEL);
5679 if (!qm->factor)
5680 return -ENOMEM;
5681
5682 /* Only the PF value needs to be initialized */
5683 qm->factor[0].func_qos = QM_QOS_MAX_VAL;
5684 }
5685
5686#define QM_INIT_BUF(qm, type, num) do { \
5687 (qm)->type = ((qm)->qdma.va + (off)); \
5688 (qm)->type##_dma = (qm)->qdma.dma + (off); \
5689 off += QMC_ALIGN(sizeof(struct qm_##type) * (num)); \
5690} while (0)
5691
5692 idr_init(idr: &qm->qp_idr);
5693 qm_get_xqc_depth(qm, low_bits: &qm->eq_depth, high_bits: &qm->aeq_depth, type: QM_XEQ_DEPTH_CAP);
5694 qm->qdma.size = QMC_ALIGN(sizeof(struct qm_eqe) * qm->eq_depth) +
5695 QMC_ALIGN(sizeof(struct qm_aeqe) * qm->aeq_depth) +
5696 QMC_ALIGN(sizeof(struct qm_sqc) * qm->qp_num) +
5697 QMC_ALIGN(sizeof(struct qm_cqc) * qm->qp_num);
5698 qm->qdma.va = dma_alloc_coherent(dev, size: qm->qdma.size, dma_handle: &qm->qdma.dma,
5699 GFP_ATOMIC);
5700 dev_dbg(dev, "allocate qm dma buf size=%zx)\n", qm->qdma.size);
5701 if (!qm->qdma.va) {
5702 ret = -ENOMEM;
5703 goto err_destroy_idr;
5704 }
5705
5706 QM_INIT_BUF(qm, eqe, qm->eq_depth);
5707 QM_INIT_BUF(qm, aeqe, qm->aeq_depth);
5708 QM_INIT_BUF(qm, sqc, qm->qp_num);
5709 QM_INIT_BUF(qm, cqc, qm->qp_num);
5710
5711 ret = hisi_qm_alloc_rsv_buf(qm);
5712 if (ret)
5713 goto err_free_qdma;
5714
5715 ret = hisi_qp_alloc_memory(qm);
5716 if (ret)
5717 goto err_free_reserve_buf;
5718
5719 return 0;
5720
5721err_free_reserve_buf:
5722 hisi_qm_free_rsv_buf(qm);
5723err_free_qdma:
5724 dma_free_coherent(dev, size: qm->qdma.size, cpu_addr: qm->qdma.va, dma_handle: qm->qdma.dma);
5725err_destroy_idr:
5726 idr_destroy(&qm->qp_idr);
5727 if (test_bit(QM_SUPPORT_FUNC_QOS, &qm->caps))
5728 kfree(objp: qm->factor);
5729
5730 return ret;
5731}
5732
5733/**
5734 * hisi_qm_init() - Initialize configures about qm.
5735 * @qm: The qm needing init.
5736 *
5737 * This function init qm, then we can call hisi_qm_start to put qm into work.
5738 */
5739int hisi_qm_init(struct hisi_qm *qm)
5740{
5741 struct pci_dev *pdev = qm->pdev;
5742 struct device *dev = &pdev->dev;
5743 int ret;
5744
5745 ret = hisi_qm_pci_init(qm);
5746 if (ret)
5747 return ret;
5748
5749 ret = qm_irqs_register(qm);
5750 if (ret)
5751 goto err_pci_init;
5752
5753 if (qm->fun_type == QM_HW_PF) {
5754 /* Set the doorbell timeout to QM_DB_TIMEOUT_CFG ns. */
5755 writel(QM_DB_TIMEOUT_SET, addr: qm->io_base + QM_DB_TIMEOUT_CFG);
5756 qm_disable_clock_gate(qm);
5757 ret = qm_dev_mem_reset(qm);
5758 if (ret) {
5759 dev_err(dev, "failed to reset device memory\n");
5760 goto err_irq_register;
5761 }
5762 }
5763
5764 if (qm->mode == UACCE_MODE_SVA) {
5765 ret = qm_alloc_uacce(qm);
5766 if (ret < 0)
5767 dev_warn(dev, "fail to alloc uacce (%d)\n", ret);
5768 }
5769
5770 ret = hisi_qm_memory_init(qm);
5771 if (ret)
5772 goto err_alloc_uacce;
5773
5774 ret = hisi_qm_init_work(qm);
5775 if (ret)
5776 goto err_free_qm_memory;
5777
5778 qm_cmd_init(qm);
5779 hisi_mig_region_enable(qm);
5780
5781 return 0;
5782
5783err_free_qm_memory:
5784 hisi_qm_memory_uninit(qm);
5785err_alloc_uacce:
5786 qm_remove_uacce(qm);
5787err_irq_register:
5788 qm_irqs_unregister(qm);
5789err_pci_init:
5790 hisi_qm_pci_uninit(qm);
5791 return ret;
5792}
5793EXPORT_SYMBOL_GPL(hisi_qm_init);
5794
5795/**
5796 * hisi_qm_get_dfx_access() - Try to get dfx access.
5797 * @qm: pointer to accelerator device.
5798 *
5799 * Try to get dfx access, then user can get message.
5800 *
5801 * If device is in suspended, return failure, otherwise
5802 * bump up the runtime PM usage counter.
5803 */
5804int hisi_qm_get_dfx_access(struct hisi_qm *qm)
5805{
5806 struct device *dev = &qm->pdev->dev;
5807
5808 if (pm_runtime_suspended(dev)) {
5809 dev_info(dev, "can not read/write - device in suspended.\n");
5810 return -EAGAIN;
5811 }
5812
5813 return qm_pm_get_sync(qm);
5814}
5815EXPORT_SYMBOL_GPL(hisi_qm_get_dfx_access);
5816
5817/**
5818 * hisi_qm_put_dfx_access() - Put dfx access.
5819 * @qm: pointer to accelerator device.
5820 *
5821 * Put dfx access, drop runtime PM usage counter.
5822 */
5823void hisi_qm_put_dfx_access(struct hisi_qm *qm)
5824{
5825 qm_pm_put_sync(qm);
5826}
5827EXPORT_SYMBOL_GPL(hisi_qm_put_dfx_access);
5828
5829/**
5830 * hisi_qm_pm_init() - Initialize qm runtime PM.
5831 * @qm: pointer to accelerator device.
5832 *
5833 * Function that initialize qm runtime PM.
5834 */
5835void hisi_qm_pm_init(struct hisi_qm *qm)
5836{
5837 struct device *dev = &qm->pdev->dev;
5838
5839 if (!test_bit(QM_SUPPORT_RPM, &qm->caps))
5840 return;
5841
5842 pm_runtime_set_autosuspend_delay(dev, QM_AUTOSUSPEND_DELAY);
5843 pm_runtime_use_autosuspend(dev);
5844 pm_runtime_put_noidle(dev);
5845}
5846EXPORT_SYMBOL_GPL(hisi_qm_pm_init);
5847
5848/**
5849 * hisi_qm_pm_uninit() - Uninitialize qm runtime PM.
5850 * @qm: pointer to accelerator device.
5851 *
5852 * Function that uninitialize qm runtime PM.
5853 */
5854void hisi_qm_pm_uninit(struct hisi_qm *qm)
5855{
5856 struct device *dev = &qm->pdev->dev;
5857
5858 if (!test_bit(QM_SUPPORT_RPM, &qm->caps))
5859 return;
5860
5861 pm_runtime_get_noresume(dev);
5862 pm_runtime_dont_use_autosuspend(dev);
5863}
5864EXPORT_SYMBOL_GPL(hisi_qm_pm_uninit);
5865
5866static int qm_prepare_for_suspend(struct hisi_qm *qm)
5867{
5868 struct pci_dev *pdev = qm->pdev;
5869 int ret;
5870
5871 ret = qm->ops->set_msi(qm, false);
5872 if (ret) {
5873 pci_err(pdev, "failed to disable MSI before suspending!\n");
5874 return ret;
5875 }
5876
5877 ret = qm_master_ooo_check(qm);
5878 if (ret)
5879 return ret;
5880
5881 if (qm->err_ini->set_priv_status) {
5882 ret = qm->err_ini->set_priv_status(qm);
5883 if (ret)
5884 return ret;
5885 }
5886
5887 ret = qm_set_pf_mse(qm, set: false);
5888 if (ret)
5889 pci_err(pdev, "failed to disable MSE before suspending!\n");
5890
5891 return ret;
5892}
5893
5894static int qm_rebuild_for_resume(struct hisi_qm *qm)
5895{
5896 struct pci_dev *pdev = qm->pdev;
5897 int ret;
5898
5899 ret = qm_set_pf_mse(qm, set: true);
5900 if (ret) {
5901 pci_err(pdev, "failed to enable MSE after resuming!\n");
5902 return ret;
5903 }
5904
5905 ret = qm->ops->set_msi(qm, true);
5906 if (ret) {
5907 pci_err(pdev, "failed to enable MSI after resuming!\n");
5908 return ret;
5909 }
5910
5911 ret = qm_dev_hw_init(qm);
5912 if (ret) {
5913 pci_err(pdev, "failed to init device after resuming\n");
5914 return ret;
5915 }
5916
5917 qm_cmd_init(qm);
5918 hisi_mig_region_enable(qm);
5919 hisi_qm_dev_err_init(qm);
5920 /* Set the doorbell timeout to QM_DB_TIMEOUT_CFG ns. */
5921 writel(QM_DB_TIMEOUT_SET, addr: qm->io_base + QM_DB_TIMEOUT_CFG);
5922 qm_disable_clock_gate(qm);
5923 ret = qm_dev_mem_reset(qm);
5924 if (ret)
5925 pci_err(pdev, "failed to reset device memory\n");
5926
5927 return ret;
5928}
5929
5930/**
5931 * hisi_qm_suspend() - Runtime suspend of given device.
5932 * @dev: device to suspend.
5933 *
5934 * Function that suspend the device.
5935 */
5936int hisi_qm_suspend(struct device *dev)
5937{
5938 struct pci_dev *pdev = to_pci_dev(dev);
5939 struct hisi_qm *qm = pci_get_drvdata(pdev);
5940 int ret;
5941
5942 pci_info(pdev, "entering suspended state\n");
5943
5944 ret = hisi_qm_stop(qm, QM_NORMAL);
5945 if (ret) {
5946 pci_err(pdev, "failed to stop qm(%d)\n", ret);
5947 return ret;
5948 }
5949
5950 ret = qm_prepare_for_suspend(qm);
5951 if (ret)
5952 pci_err(pdev, "failed to prepare suspended(%d)\n", ret);
5953
5954 return ret;
5955}
5956EXPORT_SYMBOL_GPL(hisi_qm_suspend);
5957
5958/**
5959 * hisi_qm_resume() - Runtime resume of given device.
5960 * @dev: device to resume.
5961 *
5962 * Function that resume the device.
5963 */
5964int hisi_qm_resume(struct device *dev)
5965{
5966 struct pci_dev *pdev = to_pci_dev(dev);
5967 struct hisi_qm *qm = pci_get_drvdata(pdev);
5968 int ret;
5969
5970 pci_info(pdev, "resuming from suspend state\n");
5971
5972 ret = qm_rebuild_for_resume(qm);
5973 if (ret) {
5974 pci_err(pdev, "failed to rebuild resume(%d)\n", ret);
5975 return ret;
5976 }
5977
5978 ret = hisi_qm_start(qm);
5979 if (ret) {
5980 if (qm_check_dev_error(qm)) {
5981 pci_info(pdev, "failed to start qm due to device error, device will be reset!\n");
5982 return 0;
5983 }
5984
5985 pci_err(pdev, "failed to start qm(%d)!\n", ret);
5986 }
5987
5988 return ret;
5989}
5990EXPORT_SYMBOL_GPL(hisi_qm_resume);
5991
5992MODULE_LICENSE("GPL v2");
5993MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>");
5994MODULE_DESCRIPTION("HiSilicon Accelerator queue manager driver");
5995

source code of linux/drivers/crypto/hisilicon/qm.c