1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2019 HiSilicon Limited. */
3#ifndef __HISI_HPRE_H
4#define __HISI_HPRE_H
5
6#include <linux/list.h>
7#include <linux/hisi_acc_qm.h>
8
9#define HPRE_SQE_SIZE sizeof(struct hpre_sqe)
10#define HPRE_PF_DEF_Q_NUM 64
11#define HPRE_PF_DEF_Q_BASE 0
12
13/*
14 * type used in qm sqc DW6.
15 * 0 - Algorithm which has been supported in V2, like RSA, DH and so on;
16 * 1 - ECC algorithm in V3.
17 */
18#define HPRE_V2_ALG_TYPE 0
19#define HPRE_V3_ECC_ALG_TYPE 1
20
21enum {
22 HPRE_CLUSTER0,
23 HPRE_CLUSTER1,
24 HPRE_CLUSTER2,
25 HPRE_CLUSTER3,
26 HPRE_CLUSTERS_NUM_MAX
27};
28
29enum hpre_ctrl_dbgfs_file {
30 HPRE_CLEAR_ENABLE,
31 HPRE_CLUSTER_CTRL,
32 HPRE_DEBUG_FILE_NUM,
33};
34
35enum hpre_dfx_dbgfs_file {
36 HPRE_SEND_CNT,
37 HPRE_RECV_CNT,
38 HPRE_SEND_FAIL_CNT,
39 HPRE_SEND_BUSY_CNT,
40 HPRE_OVER_THRHLD_CNT,
41 HPRE_OVERTIME_THRHLD,
42 HPRE_INVALID_REQ_CNT,
43 HPRE_DFX_FILE_NUM
44};
45
46#define HPRE_DEBUGFS_FILE_NUM (HPRE_DEBUG_FILE_NUM + HPRE_CLUSTERS_NUM_MAX - 1)
47
48struct hpre_debugfs_file {
49 int index;
50 enum hpre_ctrl_dbgfs_file type;
51 spinlock_t lock;
52 struct hpre_debug *debug;
53};
54
55struct hpre_dfx {
56 atomic64_t value;
57 enum hpre_dfx_dbgfs_file type;
58};
59
60/*
61 * One HPRE controller has one PF and multiple VFs, some global configurations
62 * which PF has need this structure.
63 * Just relevant for PF.
64 */
65struct hpre_debug {
66 struct hpre_dfx dfx[HPRE_DFX_FILE_NUM];
67 struct hpre_debugfs_file files[HPRE_DEBUGFS_FILE_NUM];
68};
69
70struct hpre {
71 struct hisi_qm qm;
72 struct hpre_debug debug;
73 unsigned long status;
74};
75
76enum hpre_alg_type {
77 HPRE_ALG_NC_NCRT = 0x0,
78 HPRE_ALG_NC_CRT = 0x1,
79 HPRE_ALG_KG_STD = 0x2,
80 HPRE_ALG_KG_CRT = 0x3,
81 HPRE_ALG_DH_G2 = 0x4,
82 HPRE_ALG_DH = 0x5,
83 HPRE_ALG_ECC_MUL = 0xD,
84 /* shared by x25519 and x448, but x448 is not supported now */
85 HPRE_ALG_CURVE25519_MUL = 0x10,
86};
87
88struct hpre_sqe {
89 __le32 dw0;
90 __u8 task_len1;
91 __u8 task_len2;
92 __u8 mrttest_num;
93 __u8 resv1;
94 __le64 key;
95 __le64 in;
96 __le64 out;
97 __le16 tag;
98 __le16 resv2;
99#define _HPRE_SQE_ALIGN_EXT 7
100 __le32 rsvd1[_HPRE_SQE_ALIGN_EXT];
101};
102
103enum hpre_cap_table_type {
104 QM_RAS_NFE_TYPE = 0x0,
105 QM_RAS_NFE_RESET,
106 QM_RAS_CE_TYPE,
107 HPRE_RAS_NFE_TYPE,
108 HPRE_RAS_NFE_RESET,
109 HPRE_RAS_CE_TYPE,
110 HPRE_CORE_INFO,
111 HPRE_CORE_EN,
112 HPRE_DRV_ALG_BITMAP,
113 HPRE_ALG_BITMAP,
114 HPRE_CORE1_BITMAP_CAP,
115 HPRE_CORE2_BITMAP_CAP,
116 HPRE_CORE3_BITMAP_CAP,
117 HPRE_CORE4_BITMAP_CAP,
118 HPRE_CORE5_BITMAP_CAP,
119 HPRE_CORE6_BITMAP_CAP,
120 HPRE_CORE7_BITMAP_CAP,
121 HPRE_CORE8_BITMAP_CAP,
122 HPRE_CORE9_BITMAP_CAP,
123 HPRE_CORE10_BITMAP_CAP,
124};
125
126struct hisi_qp *hpre_create_qp(u8 type);
127int hpre_algs_register(struct hisi_qm *qm);
128void hpre_algs_unregister(struct hisi_qm *qm);
129bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg);
130#endif
131

source code of linux/drivers/crypto/hisilicon/hpre/hpre.h