| 1 | /* SPDX-License-Identifier: MIT */ |
| 2 | /* |
| 3 | * Copyright (C) 2019,2021 Advanced Micro Devices, Inc. |
| 4 | * |
| 5 | * Author: Rijo Thomas <Rijo-john.Thomas@amd.com> |
| 6 | * Author: Devaraj Rangasamy <Devaraj.Rangasamy@amd.com> |
| 7 | * |
| 8 | */ |
| 9 | |
| 10 | /* This file describes the TEE communication interface between host and AMD |
| 11 | * Secure Processor |
| 12 | */ |
| 13 | |
| 14 | #ifndef __TEE_DEV_H__ |
| 15 | #define __TEE_DEV_H__ |
| 16 | |
| 17 | #include <linux/device.h> |
| 18 | #include <linux/mutex.h> |
| 19 | |
| 20 | #define TEE_DEFAULT_CMD_TIMEOUT (10 * MSEC_PER_SEC) |
| 21 | #define TEE_DEFAULT_RING_TIMEOUT 10 |
| 22 | #define MAX_BUFFER_SIZE 988 |
| 23 | |
| 24 | /** |
| 25 | * struct tee_init_ring_cmd - Command to init TEE ring buffer |
| 26 | * @low_addr: bits [31:0] of the physical address of ring buffer |
| 27 | * @hi_addr: bits [63:32] of the physical address of ring buffer |
| 28 | * @size: size of ring buffer in bytes |
| 29 | */ |
| 30 | struct tee_init_ring_cmd { |
| 31 | u32 low_addr; |
| 32 | u32 hi_addr; |
| 33 | u32 size; |
| 34 | }; |
| 35 | |
| 36 | #define MAX_RING_BUFFER_ENTRIES 32 |
| 37 | |
| 38 | /** |
| 39 | * struct ring_buf_manager - Helper structure to manage ring buffer. |
| 40 | * @ring_start: starting address of ring buffer |
| 41 | * @ring_size: size of ring buffer in bytes |
| 42 | * @ring_pa: physical address of ring buffer |
| 43 | * @wptr: index to the last written entry in ring buffer |
| 44 | */ |
| 45 | struct ring_buf_manager { |
| 46 | struct mutex mutex; /* synchronizes access to ring buffer */ |
| 47 | void *ring_start; |
| 48 | u32 ring_size; |
| 49 | phys_addr_t ring_pa; |
| 50 | u32 wptr; |
| 51 | }; |
| 52 | |
| 53 | struct psp_tee_device { |
| 54 | struct device *dev; |
| 55 | struct psp_device *psp; |
| 56 | void __iomem *io_regs; |
| 57 | struct tee_vdata *vdata; |
| 58 | struct ring_buf_manager rb_mgr; |
| 59 | }; |
| 60 | |
| 61 | /** |
| 62 | * enum tee_cmd_state - TEE command states for the ring buffer interface |
| 63 | * @TEE_CMD_STATE_INIT: initial state of command when sent from host |
| 64 | * @TEE_CMD_STATE_PROCESS: command being processed by TEE environment |
| 65 | * @TEE_CMD_STATE_COMPLETED: command processing completed |
| 66 | */ |
| 67 | enum tee_cmd_state { |
| 68 | TEE_CMD_STATE_INIT, |
| 69 | TEE_CMD_STATE_PROCESS, |
| 70 | TEE_CMD_STATE_COMPLETED, |
| 71 | }; |
| 72 | |
| 73 | /** |
| 74 | * enum cmd_resp_state - TEE command's response status maintained by driver |
| 75 | * @CMD_RESPONSE_INVALID: initial state when no command is written to ring |
| 76 | * @CMD_WAITING_FOR_RESPONSE: driver waiting for response from TEE |
| 77 | * @CMD_RESPONSE_TIMEDOUT: failed to get response from TEE |
| 78 | * @CMD_RESPONSE_COPIED: driver has copied response from TEE |
| 79 | */ |
| 80 | enum cmd_resp_state { |
| 81 | CMD_RESPONSE_INVALID, |
| 82 | CMD_WAITING_FOR_RESPONSE, |
| 83 | CMD_RESPONSE_TIMEDOUT, |
| 84 | CMD_RESPONSE_COPIED, |
| 85 | }; |
| 86 | |
| 87 | /** |
| 88 | * struct tee_ring_cmd - Structure of the command buffer in TEE ring |
| 89 | * @cmd_id: refers to &enum tee_cmd_id. Command id for the ring buffer |
| 90 | * interface |
| 91 | * @cmd_state: refers to &enum tee_cmd_state |
| 92 | * @status: status of TEE command execution |
| 93 | * @res0: reserved region |
| 94 | * @pdata: private data (currently unused) |
| 95 | * @res1: reserved region |
| 96 | * @buf: TEE command specific buffer |
| 97 | * @flag: refers to &enum cmd_resp_state |
| 98 | */ |
| 99 | struct tee_ring_cmd { |
| 100 | u32 cmd_id; |
| 101 | u32 cmd_state; |
| 102 | u32 status; |
| 103 | u32 res0[1]; |
| 104 | u64 pdata; |
| 105 | u32 res1[2]; |
| 106 | u8 buf[MAX_BUFFER_SIZE]; |
| 107 | u32 flag; |
| 108 | |
| 109 | /* Total size: 1024 bytes */ |
| 110 | } __packed; |
| 111 | |
| 112 | int tee_dev_init(struct psp_device *psp); |
| 113 | void tee_dev_destroy(struct psp_device *psp); |
| 114 | |
| 115 | #endif /* __TEE_DEV_H__ */ |
| 116 | |