1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2016, Linaro Limited
4 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
5 */
6
7#include <linux/cleanup.h>
8#include <linux/clk-provider.h>
9#include <linux/err.h>
10#include <linux/export.h>
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/mutex.h>
15#include <linux/mfd/qcom_rpm.h>
16#include <linux/of.h>
17#include <linux/platform_device.h>
18
19#include <dt-bindings/mfd/qcom-rpm.h>
20#include <dt-bindings/clock/qcom,rpmcc.h>
21
22#define QCOM_RPM_MISC_CLK_TYPE 0x306b6c63
23#define QCOM_RPM_SCALING_ENABLE_ID 0x2
24#define QCOM_RPM_XO_MODE_ON 0x2
25
26static const struct clk_parent_data gcc_pxo[] = {
27 { .fw_name = "pxo", .name = "pxo_board" },
28};
29
30static const struct clk_parent_data gcc_cxo[] = {
31 { .fw_name = "cxo", .name = "cxo_board" },
32};
33
34#define DEFINE_CLK_RPM(_name, r_id) \
35 static struct clk_rpm clk_rpm_##_name##_a_clk; \
36 static struct clk_rpm clk_rpm_##_name##_clk = { \
37 .rpm_clk_id = (r_id), \
38 .peer = &clk_rpm_##_name##_a_clk, \
39 .rate = INT_MAX, \
40 .hw.init = &(struct clk_init_data){ \
41 .ops = &clk_rpm_ops, \
42 .name = #_name "_clk", \
43 .parent_data = gcc_pxo, \
44 .num_parents = ARRAY_SIZE(gcc_pxo), \
45 }, \
46 }; \
47 static struct clk_rpm clk_rpm_##_name##_a_clk = { \
48 .rpm_clk_id = (r_id), \
49 .peer = &clk_rpm_##_name##_clk, \
50 .active_only = true, \
51 .rate = INT_MAX, \
52 .hw.init = &(struct clk_init_data){ \
53 .ops = &clk_rpm_ops, \
54 .name = #_name "_a_clk", \
55 .parent_data = gcc_pxo, \
56 .num_parents = ARRAY_SIZE(gcc_pxo), \
57 }, \
58 }
59
60#define DEFINE_CLK_RPM_XO_BUFFER(_name, offset) \
61 static struct clk_rpm clk_rpm_##_name##_clk = { \
62 .rpm_clk_id = QCOM_RPM_CXO_BUFFERS, \
63 .xo_offset = (offset), \
64 .hw.init = &(struct clk_init_data){ \
65 .ops = &clk_rpm_xo_ops, \
66 .name = #_name "_clk", \
67 .parent_data = gcc_cxo, \
68 .num_parents = ARRAY_SIZE(gcc_cxo), \
69 }, \
70 }
71
72#define DEFINE_CLK_RPM_FIXED(_name, r_id, r) \
73 static struct clk_rpm clk_rpm_##_name##_clk = { \
74 .rpm_clk_id = (r_id), \
75 .rate = (r), \
76 .hw.init = &(struct clk_init_data){ \
77 .ops = &clk_rpm_fixed_ops, \
78 .name = #_name "_clk", \
79 .parent_data = gcc_pxo, \
80 .num_parents = ARRAY_SIZE(gcc_pxo), \
81 }, \
82 }
83
84#define to_clk_rpm(_hw) container_of(_hw, struct clk_rpm, hw)
85
86struct rpm_cc;
87
88struct clk_rpm {
89 const int rpm_clk_id;
90 const int xo_offset;
91 const bool active_only;
92 unsigned long rate;
93 bool enabled;
94 bool branch;
95 struct clk_rpm *peer;
96 struct clk_hw hw;
97 struct qcom_rpm *rpm;
98 struct rpm_cc *rpm_cc;
99};
100
101struct rpm_cc {
102 struct clk_rpm **clks;
103 size_t num_clks;
104 u32 xo_buffer_value;
105 struct mutex xo_lock;
106};
107
108struct rpm_clk_desc {
109 struct clk_rpm **clks;
110 size_t num_clks;
111};
112
113static DEFINE_MUTEX(rpm_clk_lock);
114
115static int clk_rpm_handoff(struct clk_rpm *r)
116{
117 int ret;
118 u32 value = INT_MAX;
119
120 /*
121 * The vendor tree simply reads the status for this
122 * RPM clock.
123 */
124 if (r->rpm_clk_id == QCOM_RPM_PLL_4 ||
125 r->rpm_clk_id == QCOM_RPM_CXO_BUFFERS)
126 return 0;
127
128 ret = qcom_rpm_write(rpm: r->rpm, QCOM_RPM_ACTIVE_STATE,
129 resource: r->rpm_clk_id, buf: &value, count: 1);
130 if (ret)
131 return ret;
132 ret = qcom_rpm_write(rpm: r->rpm, QCOM_RPM_SLEEP_STATE,
133 resource: r->rpm_clk_id, buf: &value, count: 1);
134 if (ret)
135 return ret;
136
137 return 0;
138}
139
140static int clk_rpm_set_rate_active(struct clk_rpm *r, unsigned long rate)
141{
142 u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */
143
144 return qcom_rpm_write(rpm: r->rpm, QCOM_RPM_ACTIVE_STATE,
145 resource: r->rpm_clk_id, buf: &value, count: 1);
146}
147
148static int clk_rpm_set_rate_sleep(struct clk_rpm *r, unsigned long rate)
149{
150 u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */
151
152 return qcom_rpm_write(rpm: r->rpm, QCOM_RPM_SLEEP_STATE,
153 resource: r->rpm_clk_id, buf: &value, count: 1);
154}
155
156static void to_active_sleep(struct clk_rpm *r, unsigned long rate,
157 unsigned long *active, unsigned long *sleep)
158{
159 *active = rate;
160
161 /*
162 * Active-only clocks don't care what the rate is during sleep. So,
163 * they vote for zero.
164 */
165 if (r->active_only)
166 *sleep = 0;
167 else
168 *sleep = *active;
169}
170
171static int clk_rpm_prepare(struct clk_hw *hw)
172{
173 struct clk_rpm *r = to_clk_rpm(hw);
174 struct clk_rpm *peer = r->peer;
175 unsigned long this_rate = 0, this_sleep_rate = 0;
176 unsigned long peer_rate = 0, peer_sleep_rate = 0;
177 unsigned long active_rate, sleep_rate;
178 int ret = 0;
179
180 mutex_lock(&rpm_clk_lock);
181
182 /* Don't send requests to the RPM if the rate has not been set. */
183 if (!r->rate)
184 goto out;
185
186 to_active_sleep(r, rate: r->rate, active: &this_rate, sleep: &this_sleep_rate);
187
188 /* Take peer clock's rate into account only if it's enabled. */
189 if (peer->enabled)
190 to_active_sleep(r: peer, rate: peer->rate,
191 active: &peer_rate, sleep: &peer_sleep_rate);
192
193 active_rate = max(this_rate, peer_rate);
194
195 if (r->branch)
196 active_rate = !!active_rate;
197
198 ret = clk_rpm_set_rate_active(r, rate: active_rate);
199 if (ret)
200 goto out;
201
202 sleep_rate = max(this_sleep_rate, peer_sleep_rate);
203 if (r->branch)
204 sleep_rate = !!sleep_rate;
205
206 ret = clk_rpm_set_rate_sleep(r, rate: sleep_rate);
207 if (ret)
208 /* Undo the active set vote and restore it */
209 ret = clk_rpm_set_rate_active(r, rate: peer_rate);
210
211out:
212 if (!ret)
213 r->enabled = true;
214
215 mutex_unlock(lock: &rpm_clk_lock);
216
217 return ret;
218}
219
220static void clk_rpm_unprepare(struct clk_hw *hw)
221{
222 struct clk_rpm *r = to_clk_rpm(hw);
223 struct clk_rpm *peer = r->peer;
224 unsigned long peer_rate = 0, peer_sleep_rate = 0;
225 unsigned long active_rate, sleep_rate;
226 int ret;
227
228 guard(mutex)(T: &rpm_clk_lock);
229
230 if (!r->rate)
231 return;
232
233 /* Take peer clock's rate into account only if it's enabled. */
234 if (peer->enabled)
235 to_active_sleep(r: peer, rate: peer->rate, active: &peer_rate,
236 sleep: &peer_sleep_rate);
237
238 active_rate = r->branch ? !!peer_rate : peer_rate;
239 ret = clk_rpm_set_rate_active(r, rate: active_rate);
240 if (ret)
241 return;
242
243 sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
244 ret = clk_rpm_set_rate_sleep(r, rate: sleep_rate);
245 if (ret)
246 return;
247
248 r->enabled = false;
249}
250
251static int clk_rpm_xo_prepare(struct clk_hw *hw)
252{
253 struct clk_rpm *r = to_clk_rpm(hw);
254 struct rpm_cc *rcc = r->rpm_cc;
255 int ret, clk_id = r->rpm_clk_id;
256 u32 value;
257
258 mutex_lock(&rcc->xo_lock);
259
260 value = rcc->xo_buffer_value | (QCOM_RPM_XO_MODE_ON << r->xo_offset);
261 ret = qcom_rpm_write(rpm: r->rpm, QCOM_RPM_ACTIVE_STATE, resource: clk_id, buf: &value, count: 1);
262 if (!ret) {
263 r->enabled = true;
264 rcc->xo_buffer_value = value;
265 }
266
267 mutex_unlock(lock: &rcc->xo_lock);
268
269 return ret;
270}
271
272static void clk_rpm_xo_unprepare(struct clk_hw *hw)
273{
274 struct clk_rpm *r = to_clk_rpm(hw);
275 struct rpm_cc *rcc = r->rpm_cc;
276 int ret, clk_id = r->rpm_clk_id;
277 u32 value;
278
279 mutex_lock(&rcc->xo_lock);
280
281 value = rcc->xo_buffer_value & ~(QCOM_RPM_XO_MODE_ON << r->xo_offset);
282 ret = qcom_rpm_write(rpm: r->rpm, QCOM_RPM_ACTIVE_STATE, resource: clk_id, buf: &value, count: 1);
283 if (!ret) {
284 r->enabled = false;
285 rcc->xo_buffer_value = value;
286 }
287
288 mutex_unlock(lock: &rcc->xo_lock);
289}
290
291static int clk_rpm_fixed_prepare(struct clk_hw *hw)
292{
293 struct clk_rpm *r = to_clk_rpm(hw);
294 u32 value = 1;
295 int ret;
296
297 ret = qcom_rpm_write(rpm: r->rpm, QCOM_RPM_ACTIVE_STATE,
298 resource: r->rpm_clk_id, buf: &value, count: 1);
299 if (!ret)
300 r->enabled = true;
301
302 return ret;
303}
304
305static void clk_rpm_fixed_unprepare(struct clk_hw *hw)
306{
307 struct clk_rpm *r = to_clk_rpm(hw);
308 u32 value = 0;
309 int ret;
310
311 ret = qcom_rpm_write(rpm: r->rpm, QCOM_RPM_ACTIVE_STATE,
312 resource: r->rpm_clk_id, buf: &value, count: 1);
313 if (!ret)
314 r->enabled = false;
315}
316
317static int clk_rpm_set_rate(struct clk_hw *hw,
318 unsigned long rate, unsigned long parent_rate)
319{
320 struct clk_rpm *r = to_clk_rpm(hw);
321 struct clk_rpm *peer = r->peer;
322 unsigned long active_rate, sleep_rate;
323 unsigned long this_rate = 0, this_sleep_rate = 0;
324 unsigned long peer_rate = 0, peer_sleep_rate = 0;
325 int ret;
326
327 guard(mutex)(T: &rpm_clk_lock);
328
329 if (!r->enabled)
330 return 0;
331
332 to_active_sleep(r, rate, active: &this_rate, sleep: &this_sleep_rate);
333
334 /* Take peer clock's rate into account only if it's enabled. */
335 if (peer->enabled)
336 to_active_sleep(r: peer, rate: peer->rate,
337 active: &peer_rate, sleep: &peer_sleep_rate);
338
339 active_rate = max(this_rate, peer_rate);
340 ret = clk_rpm_set_rate_active(r, rate: active_rate);
341 if (ret)
342 return ret;
343
344 sleep_rate = max(this_sleep_rate, peer_sleep_rate);
345 ret = clk_rpm_set_rate_sleep(r, rate: sleep_rate);
346 if (ret)
347 return ret;
348
349 r->rate = rate;
350
351 return 0;
352}
353
354static int clk_rpm_determine_rate(struct clk_hw *hw,
355 struct clk_rate_request *req)
356{
357 /*
358 * RPM handles rate rounding and we don't have a way to
359 * know what the rate will be, so just return whatever
360 * rate is requested.
361 */
362 return 0;
363}
364
365static unsigned long clk_rpm_recalc_rate(struct clk_hw *hw,
366 unsigned long parent_rate)
367{
368 struct clk_rpm *r = to_clk_rpm(hw);
369
370 /*
371 * RPM handles rate rounding and we don't have a way to
372 * know what the rate will be, so just return whatever
373 * rate was set.
374 */
375 return r->rate;
376}
377
378static const struct clk_ops clk_rpm_xo_ops = {
379 .prepare = clk_rpm_xo_prepare,
380 .unprepare = clk_rpm_xo_unprepare,
381};
382
383static const struct clk_ops clk_rpm_fixed_ops = {
384 .prepare = clk_rpm_fixed_prepare,
385 .unprepare = clk_rpm_fixed_unprepare,
386 .determine_rate = clk_rpm_determine_rate,
387 .recalc_rate = clk_rpm_recalc_rate,
388};
389
390static const struct clk_ops clk_rpm_ops = {
391 .prepare = clk_rpm_prepare,
392 .unprepare = clk_rpm_unprepare,
393 .set_rate = clk_rpm_set_rate,
394 .determine_rate = clk_rpm_determine_rate,
395 .recalc_rate = clk_rpm_recalc_rate,
396};
397
398DEFINE_CLK_RPM(afab, QCOM_RPM_APPS_FABRIC_CLK);
399DEFINE_CLK_RPM(sfab, QCOM_RPM_SYS_FABRIC_CLK);
400DEFINE_CLK_RPM(mmfab, QCOM_RPM_MM_FABRIC_CLK);
401DEFINE_CLK_RPM(daytona, QCOM_RPM_DAYTONA_FABRIC_CLK);
402DEFINE_CLK_RPM(sfpb, QCOM_RPM_SFPB_CLK);
403DEFINE_CLK_RPM(cfpb, QCOM_RPM_CFPB_CLK);
404DEFINE_CLK_RPM(mmfpb, QCOM_RPM_MMFPB_CLK);
405DEFINE_CLK_RPM(smi, QCOM_RPM_SMI_CLK);
406DEFINE_CLK_RPM(ebi1, QCOM_RPM_EBI1_CLK);
407
408DEFINE_CLK_RPM(qdss, QCOM_RPM_QDSS_CLK);
409DEFINE_CLK_RPM(nss_fabric_0, QCOM_RPM_NSS_FABRIC_0_CLK);
410DEFINE_CLK_RPM(nss_fabric_1, QCOM_RPM_NSS_FABRIC_1_CLK);
411
412DEFINE_CLK_RPM_FIXED(pll4, QCOM_RPM_PLL_4, 540672000);
413
414DEFINE_CLK_RPM_XO_BUFFER(xo_d0, 0);
415DEFINE_CLK_RPM_XO_BUFFER(xo_d1, 8);
416DEFINE_CLK_RPM_XO_BUFFER(xo_a0, 16);
417DEFINE_CLK_RPM_XO_BUFFER(xo_a1, 24);
418DEFINE_CLK_RPM_XO_BUFFER(xo_a2, 28);
419
420static struct clk_rpm *msm8660_clks[] = {
421 [RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk,
422 [RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk,
423 [RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk,
424 [RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk,
425 [RPM_MM_FABRIC_CLK] = &clk_rpm_mmfab_clk,
426 [RPM_MM_FABRIC_A_CLK] = &clk_rpm_mmfab_a_clk,
427 [RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk,
428 [RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk,
429 [RPM_SFPB_CLK] = &clk_rpm_sfpb_clk,
430 [RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk,
431 [RPM_CFPB_CLK] = &clk_rpm_cfpb_clk,
432 [RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk,
433 [RPM_MMFPB_CLK] = &clk_rpm_mmfpb_clk,
434 [RPM_MMFPB_A_CLK] = &clk_rpm_mmfpb_a_clk,
435 [RPM_SMI_CLK] = &clk_rpm_smi_clk,
436 [RPM_SMI_A_CLK] = &clk_rpm_smi_a_clk,
437 [RPM_EBI1_CLK] = &clk_rpm_ebi1_clk,
438 [RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk,
439 [RPM_PLL4_CLK] = &clk_rpm_pll4_clk,
440};
441
442static const struct rpm_clk_desc rpm_clk_msm8660 = {
443 .clks = msm8660_clks,
444 .num_clks = ARRAY_SIZE(msm8660_clks),
445};
446
447static struct clk_rpm *apq8064_clks[] = {
448 [RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk,
449 [RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk,
450 [RPM_CFPB_CLK] = &clk_rpm_cfpb_clk,
451 [RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk,
452 [RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk,
453 [RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk,
454 [RPM_EBI1_CLK] = &clk_rpm_ebi1_clk,
455 [RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk,
456 [RPM_MM_FABRIC_CLK] = &clk_rpm_mmfab_clk,
457 [RPM_MM_FABRIC_A_CLK] = &clk_rpm_mmfab_a_clk,
458 [RPM_MMFPB_CLK] = &clk_rpm_mmfpb_clk,
459 [RPM_MMFPB_A_CLK] = &clk_rpm_mmfpb_a_clk,
460 [RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk,
461 [RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk,
462 [RPM_SFPB_CLK] = &clk_rpm_sfpb_clk,
463 [RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk,
464 [RPM_QDSS_CLK] = &clk_rpm_qdss_clk,
465 [RPM_QDSS_A_CLK] = &clk_rpm_qdss_a_clk,
466 [RPM_XO_D0] = &clk_rpm_xo_d0_clk,
467 [RPM_XO_D1] = &clk_rpm_xo_d1_clk,
468 [RPM_XO_A0] = &clk_rpm_xo_a0_clk,
469 [RPM_XO_A1] = &clk_rpm_xo_a1_clk,
470 [RPM_XO_A2] = &clk_rpm_xo_a2_clk,
471};
472
473static const struct rpm_clk_desc rpm_clk_apq8064 = {
474 .clks = apq8064_clks,
475 .num_clks = ARRAY_SIZE(apq8064_clks),
476};
477
478static struct clk_rpm *ipq806x_clks[] = {
479 [RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk,
480 [RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk,
481 [RPM_CFPB_CLK] = &clk_rpm_cfpb_clk,
482 [RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk,
483 [RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk,
484 [RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk,
485 [RPM_EBI1_CLK] = &clk_rpm_ebi1_clk,
486 [RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk,
487 [RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk,
488 [RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk,
489 [RPM_SFPB_CLK] = &clk_rpm_sfpb_clk,
490 [RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk,
491 [RPM_NSS_FABRIC_0_CLK] = &clk_rpm_nss_fabric_0_clk,
492 [RPM_NSS_FABRIC_0_A_CLK] = &clk_rpm_nss_fabric_0_a_clk,
493 [RPM_NSS_FABRIC_1_CLK] = &clk_rpm_nss_fabric_1_clk,
494 [RPM_NSS_FABRIC_1_A_CLK] = &clk_rpm_nss_fabric_1_a_clk,
495};
496
497static const struct rpm_clk_desc rpm_clk_ipq806x = {
498 .clks = ipq806x_clks,
499 .num_clks = ARRAY_SIZE(ipq806x_clks),
500};
501
502static const struct of_device_id rpm_clk_match_table[] = {
503 { .compatible = "qcom,rpmcc-msm8660", .data = &rpm_clk_msm8660 },
504 { .compatible = "qcom,rpmcc-apq8060", .data = &rpm_clk_msm8660 },
505 { .compatible = "qcom,rpmcc-apq8064", .data = &rpm_clk_apq8064 },
506 { .compatible = "qcom,rpmcc-ipq806x", .data = &rpm_clk_ipq806x },
507 { }
508};
509MODULE_DEVICE_TABLE(of, rpm_clk_match_table);
510
511static struct clk_hw *qcom_rpm_clk_hw_get(struct of_phandle_args *clkspec,
512 void *data)
513{
514 struct rpm_cc *rcc = data;
515 unsigned int idx = clkspec->args[0];
516
517 if (idx >= rcc->num_clks) {
518 pr_err("%s: invalid index %u\n", __func__, idx);
519 return ERR_PTR(error: -EINVAL);
520 }
521
522 return rcc->clks[idx] ? &rcc->clks[idx]->hw : ERR_PTR(error: -ENOENT);
523}
524
525static int rpm_clk_probe(struct platform_device *pdev)
526{
527 struct rpm_cc *rcc;
528 int ret;
529 size_t num_clks, i;
530 struct qcom_rpm *rpm;
531 struct clk_rpm **rpm_clks;
532 const struct rpm_clk_desc *desc;
533
534 rpm = dev_get_drvdata(dev: pdev->dev.parent);
535 if (!rpm) {
536 dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
537 return -ENODEV;
538 }
539
540 desc = of_device_get_match_data(dev: &pdev->dev);
541 if (!desc)
542 return -EINVAL;
543
544 rpm_clks = desc->clks;
545 num_clks = desc->num_clks;
546
547 rcc = devm_kzalloc(dev: &pdev->dev, size: sizeof(*rcc), GFP_KERNEL);
548 if (!rcc)
549 return -ENOMEM;
550
551 rcc->clks = rpm_clks;
552 rcc->num_clks = num_clks;
553 mutex_init(&rcc->xo_lock);
554
555 for (i = 0; i < num_clks; i++) {
556 if (!rpm_clks[i])
557 continue;
558
559 rpm_clks[i]->rpm = rpm;
560 rpm_clks[i]->rpm_cc = rcc;
561
562 ret = clk_rpm_handoff(r: rpm_clks[i]);
563 if (ret)
564 goto err;
565 }
566
567 for (i = 0; i < num_clks; i++) {
568 if (!rpm_clks[i])
569 continue;
570
571 ret = devm_clk_hw_register(dev: &pdev->dev, hw: &rpm_clks[i]->hw);
572 if (ret)
573 goto err;
574 }
575
576 ret = devm_of_clk_add_hw_provider(dev: &pdev->dev, get: qcom_rpm_clk_hw_get,
577 data: rcc);
578 if (ret)
579 goto err;
580
581 return 0;
582err:
583 dev_err(&pdev->dev, "Error registering RPM Clock driver (%d)\n", ret);
584 return ret;
585}
586
587static struct platform_driver rpm_clk_driver = {
588 .driver = {
589 .name = "qcom-clk-rpm",
590 .of_match_table = rpm_clk_match_table,
591 },
592 .probe = rpm_clk_probe,
593};
594
595static int __init rpm_clk_init(void)
596{
597 return platform_driver_register(&rpm_clk_driver);
598}
599core_initcall(rpm_clk_init);
600
601static void __exit rpm_clk_exit(void)
602{
603 platform_driver_unregister(&rpm_clk_driver);
604}
605module_exit(rpm_clk_exit);
606
607MODULE_DESCRIPTION("Qualcomm RPM Clock Controller Driver");
608MODULE_LICENSE("GPL v2");
609MODULE_ALIAS("platform:qcom-clk-rpm");
610

source code of linux/drivers/clk/qcom/clk-rpm.c