1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2015, 2018, 2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7
8#ifndef __QCOM_CLK_ALPHA_PLL_H__
9#define __QCOM_CLK_ALPHA_PLL_H__
10
11#include <linux/clk-provider.h>
12#include "clk-regmap.h"
13
14/* Alpha PLL types */
15enum {
16 CLK_ALPHA_PLL_TYPE_DEFAULT,
17 CLK_ALPHA_PLL_TYPE_HUAYRA,
18 CLK_ALPHA_PLL_TYPE_HUAYRA_APSS,
19 CLK_ALPHA_PLL_TYPE_HUAYRA_2290,
20 CLK_ALPHA_PLL_TYPE_BRAMMO,
21 CLK_ALPHA_PLL_TYPE_FABIA,
22 CLK_ALPHA_PLL_TYPE_TRION,
23 CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
24 CLK_ALPHA_PLL_TYPE_AGERA,
25 CLK_ALPHA_PLL_TYPE_ZONDA,
26 CLK_ALPHA_PLL_TYPE_REGERA = CLK_ALPHA_PLL_TYPE_ZONDA,
27 CLK_ALPHA_PLL_TYPE_ZONDA_OLE,
28 CLK_ALPHA_PLL_TYPE_LUCID_EVO,
29 CLK_ALPHA_PLL_TYPE_LUCID_OLE,
30 CLK_ALPHA_PLL_TYPE_PONGO_ELU,
31 CLK_ALPHA_PLL_TYPE_TAYCAN_ELU,
32 CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T = CLK_ALPHA_PLL_TYPE_TAYCAN_ELU,
33 CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
34 CLK_ALPHA_PLL_TYPE_DEFAULT_EVO,
35 CLK_ALPHA_PLL_TYPE_BRAMMO_EVO,
36 CLK_ALPHA_PLL_TYPE_STROMER,
37 CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
38 CLK_ALPHA_PLL_TYPE_NSS_HUAYRA,
39 CLK_ALPHA_PLL_TYPE_MAX,
40};
41
42enum {
43 PLL_OFF_L_VAL,
44 PLL_OFF_CAL_L_VAL,
45 PLL_OFF_ALPHA_VAL,
46 PLL_OFF_ALPHA_VAL_U,
47 PLL_OFF_USER_CTL,
48 PLL_OFF_USER_CTL_U,
49 PLL_OFF_USER_CTL_U1,
50 PLL_OFF_CONFIG_CTL,
51 PLL_OFF_CONFIG_CTL_U,
52 PLL_OFF_CONFIG_CTL_U1,
53 PLL_OFF_CONFIG_CTL_U2,
54 PLL_OFF_TEST_CTL,
55 PLL_OFF_TEST_CTL_U,
56 PLL_OFF_TEST_CTL_U1,
57 PLL_OFF_TEST_CTL_U2,
58 PLL_OFF_TEST_CTL_U3,
59 PLL_OFF_STATE,
60 PLL_OFF_STATUS,
61 PLL_OFF_OPMODE,
62 PLL_OFF_FRAC,
63 PLL_OFF_CAL_VAL,
64 PLL_OFF_MAX_REGS
65};
66
67extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS];
68
69struct pll_vco {
70 unsigned long min_freq;
71 unsigned long max_freq;
72 u32 val;
73};
74
75#define VCO(a, b, c) { \
76 .val = a,\
77 .min_freq = b,\
78 .max_freq = c,\
79}
80
81/**
82 * struct clk_alpha_pll - phase locked loop (PLL)
83 * @offset: base address of registers
84 * @regs: alpha pll register map (see @clk_alpha_pll_regs)
85 * @config: array of pll settings
86 * @vco_table: array of VCO settings
87 * @num_vco: number of VCO settings in @vco_table
88 * @flags: bitmask to indicate features supported by the hardware
89 * @clkr: regmap clock handle
90 */
91struct clk_alpha_pll {
92 u32 offset;
93 const u8 *regs;
94
95 const struct alpha_pll_config *config;
96 const struct pll_vco *vco_table;
97 size_t num_vco;
98#define SUPPORTS_OFFLINE_REQ BIT(0)
99#define SUPPORTS_FSM_MODE BIT(2)
100#define SUPPORTS_DYNAMIC_UPDATE BIT(3)
101#define SUPPORTS_FSM_LEGACY_MODE BIT(4)
102 u8 flags;
103
104 struct clk_regmap clkr;
105};
106
107/**
108 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
109 * @offset: base address of registers
110 * @regs: alpha pll register map (see @clk_alpha_pll_regs)
111 * @width: width of post-divider
112 * @post_div_shift: shift to differentiate between odd & even post-divider
113 * @post_div_table: table with PLL odd and even post-divider settings
114 * @num_post_div: Number of PLL post-divider settings
115 *
116 * @clkr: regmap clock handle
117 */
118struct clk_alpha_pll_postdiv {
119 u32 offset;
120 u8 width;
121 const u8 *regs;
122
123 struct clk_regmap clkr;
124 int post_div_shift;
125 const struct clk_div_table *post_div_table;
126 size_t num_post_div;
127};
128
129struct alpha_pll_config {
130 u32 l;
131 u32 alpha;
132 u32 alpha_hi;
133 u32 config_ctl_val;
134 u32 config_ctl_hi_val;
135 u32 config_ctl_hi1_val;
136 u32 config_ctl_hi2_val;
137 u32 user_ctl_val;
138 u32 user_ctl_hi_val;
139 u32 user_ctl_hi1_val;
140 u32 test_ctl_val;
141 u32 test_ctl_mask;
142 u32 test_ctl_hi_val;
143 u32 test_ctl_hi_mask;
144 u32 test_ctl_hi1_val;
145 u32 test_ctl_hi2_val;
146 u32 test_ctl_hi3_val;
147 u32 main_output_mask;
148 u32 aux_output_mask;
149 u32 aux2_output_mask;
150 u32 early_output_mask;
151 u32 alpha_en_mask;
152 u32 alpha_mode_mask;
153 u32 pre_div_val;
154 u32 pre_div_mask;
155 u32 post_div_val;
156 u32 post_div_mask;
157 u32 vco_val;
158 u32 vco_mask;
159 u32 status_val;
160 u32 status_mask;
161 u32 lock_det;
162};
163
164extern const struct clk_ops clk_alpha_pll_ops;
165extern const struct clk_ops clk_alpha_pll_fixed_ops;
166extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
167extern const struct clk_ops clk_alpha_pll_postdiv_ops;
168extern const struct clk_ops clk_alpha_pll_huayra_ops;
169extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
170extern const struct clk_ops clk_alpha_pll_stromer_ops;
171extern const struct clk_ops clk_alpha_pll_stromer_plus_ops;
172
173extern const struct clk_ops clk_alpha_pll_fabia_ops;
174extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
175extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;
176
177extern const struct clk_ops clk_alpha_pll_trion_ops;
178extern const struct clk_ops clk_alpha_pll_fixed_trion_ops;
179extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops;
180
181extern const struct clk_ops clk_alpha_pll_lucid_ops;
182#define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops
183extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops;
184extern const struct clk_ops clk_alpha_pll_agera_ops;
185
186extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops;
187extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops;
188extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops;
189
190extern const struct clk_ops clk_alpha_pll_zonda_ops;
191#define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops
192#define clk_alpha_pll_zonda_ole_ops clk_alpha_pll_zonda_ops
193
194extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;
195#define clk_alpha_pll_taycan_elu_ops clk_alpha_pll_lucid_evo_ops
196#define clk_alpha_pll_taycan_eko_t_ops clk_alpha_pll_lucid_evo_ops
197extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops;
198#define clk_alpha_pll_reset_lucid_ole_ops clk_alpha_pll_reset_lucid_evo_ops
199extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;
200#define clk_alpha_pll_fixed_lucid_ole_ops clk_alpha_pll_fixed_lucid_evo_ops
201#define clk_alpha_pll_fixed_taycan_elu_ops clk_alpha_pll_fixed_lucid_evo_ops
202#define clk_alpha_pll_fixed_taycan_eko_t_ops clk_alpha_pll_fixed_lucid_evo_ops
203extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
204#define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_evo_ops
205#define clk_alpha_pll_postdiv_taycan_elu_ops clk_alpha_pll_postdiv_lucid_evo_ops
206#define clk_alpha_pll_postdiv_taycan_eko_t_ops clk_alpha_pll_postdiv_lucid_evo_ops
207
208extern const struct clk_ops clk_alpha_pll_pongo_elu_ops;
209extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;
210#define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops
211
212extern const struct clk_ops clk_alpha_pll_regera_ops;
213extern const struct clk_ops clk_alpha_pll_slew_ops;
214
215void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
216 const struct alpha_pll_config *config);
217void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
218 const struct alpha_pll_config *config);
219void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
220 const struct alpha_pll_config *config);
221void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
222 const struct alpha_pll_config *config);
223void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
224 const struct alpha_pll_config *config);
225#define clk_lucid_pll_configure(pll, regmap, config) \
226 clk_trion_pll_configure(pll, regmap, config)
227
228void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
229 const struct alpha_pll_config *config);
230void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
231 const struct alpha_pll_config *config);
232void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
233 const struct alpha_pll_config *config);
234void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
235 const struct alpha_pll_config *config);
236void clk_pongo_elu_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
237 const struct alpha_pll_config *config);
238#define clk_taycan_elu_pll_configure(pll, regmap, config) \
239 clk_lucid_evo_pll_configure(pll, regmap, config)
240#define clk_taycan_eko_t_pll_configure(pll, regmap, config) \
241 clk_lucid_evo_pll_configure(pll, regmap, config)
242
243void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
244 const struct alpha_pll_config *config);
245void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
246 const struct alpha_pll_config *config);
247void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
248 const struct alpha_pll_config *config);
249void qcom_clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap);
250
251#endif
252

source code of linux/drivers/clk/qcom/clk-alpha-pll.h