1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for Silicon Labs Si5340, Si5341, Si5342, Si5344 and Si5345
4 * Copyright (C) 2019 Topic Embedded Products
5 * Author: Mike Looijmans <mike.looijmans@topic.nl>
6 *
7 * The Si5341 has 10 outputs and 5 synthesizers.
8 * The Si5340 is a smaller version of the Si5341 with only 4 outputs.
9 * The Si5345 is similar to the Si5341, with the addition of fractional input
10 * dividers and automatic input selection.
11 * The Si5342 and Si5344 are smaller versions of the Si5345.
12 */
13
14#include <linux/clk.h>
15#include <linux/clk-provider.h>
16#include <linux/delay.h>
17#include <linux/gcd.h>
18#include <linux/math64.h>
19#include <linux/i2c.h>
20#include <linux/module.h>
21#include <linux/regmap.h>
22#include <linux/regulator/consumer.h>
23#include <linux/slab.h>
24#include <linux/unaligned.h>
25
26#define SI5341_NUM_INPUTS 4
27
28#define SI5340_MAX_NUM_OUTPUTS 4
29#define SI5341_MAX_NUM_OUTPUTS 10
30#define SI5342_MAX_NUM_OUTPUTS 2
31#define SI5344_MAX_NUM_OUTPUTS 4
32#define SI5345_MAX_NUM_OUTPUTS 10
33
34#define SI5340_NUM_SYNTH 4
35#define SI5341_NUM_SYNTH 5
36#define SI5342_NUM_SYNTH 2
37#define SI5344_NUM_SYNTH 4
38#define SI5345_NUM_SYNTH 5
39
40/* Range of the synthesizer fractional divider */
41#define SI5341_SYNTH_N_MIN 10
42#define SI5341_SYNTH_N_MAX 4095
43
44/* The chip can get its input clock from 3 input pins or an XTAL */
45
46/* There is one PLL running at 13500–14256 MHz */
47#define SI5341_PLL_VCO_MIN 13500000000ull
48#define SI5341_PLL_VCO_MAX 14256000000ull
49
50/* The 5 frequency synthesizers obtain their input from the PLL */
51struct clk_si5341_synth {
52 struct clk_hw hw;
53 struct clk_si5341 *data;
54 u8 index;
55};
56#define to_clk_si5341_synth(_hw) \
57 container_of(_hw, struct clk_si5341_synth, hw)
58
59/* The output stages can be connected to any synth (full mux) */
60struct clk_si5341_output {
61 struct clk_hw hw;
62 struct clk_si5341 *data;
63 struct regulator *vddo_reg;
64 u8 index;
65};
66#define to_clk_si5341_output(_hw) \
67 container_of(_hw, struct clk_si5341_output, hw)
68
69struct clk_si5341 {
70 struct clk_hw hw;
71 struct regmap *regmap;
72 struct i2c_client *i2c_client;
73 struct clk_si5341_synth synth[SI5341_NUM_SYNTH];
74 struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS];
75 struct clk *input_clk[SI5341_NUM_INPUTS];
76 const char *input_clk_name[SI5341_NUM_INPUTS];
77 const u16 *reg_output_offset;
78 const u16 *reg_rdiv_offset;
79 u64 freq_vco; /* 13500–14256 MHz */
80 u8 num_outputs;
81 u8 num_synth;
82 u16 chip_id;
83 bool xaxb_ext_clk;
84 bool iovdd_33;
85};
86#define to_clk_si5341(_hw) container_of(_hw, struct clk_si5341, hw)
87
88struct clk_si5341_output_config {
89 u8 out_format_drv_bits;
90 u8 out_cm_ampl_bits;
91 u8 vdd_sel_bits;
92 bool synth_master;
93 bool always_on;
94};
95
96#define SI5341_PAGE 0x0001
97#define SI5341_PN_BASE 0x0002
98#define SI5341_DEVICE_REV 0x0005
99#define SI5341_STATUS 0x000C
100#define SI5341_LOS 0x000D
101#define SI5341_STATUS_STICKY 0x0011
102#define SI5341_LOS_STICKY 0x0012
103#define SI5341_SOFT_RST 0x001C
104#define SI5341_IN_SEL 0x0021
105#define SI5341_DEVICE_READY 0x00FE
106#define SI5341_XAXB_CFG 0x090E
107#define SI5341_IO_VDD_SEL 0x0943
108#define SI5341_IN_EN 0x0949
109#define SI5341_INX_TO_PFD_EN 0x094A
110
111/* Status bits */
112#define SI5341_STATUS_SYSINCAL BIT(0)
113#define SI5341_STATUS_LOSXAXB BIT(1)
114#define SI5341_STATUS_LOSREF BIT(2)
115#define SI5341_STATUS_LOL BIT(3)
116
117/* Input selection */
118#define SI5341_IN_SEL_MASK 0x06
119#define SI5341_IN_SEL_SHIFT 1
120#define SI5341_IN_SEL_REGCTRL 0x01
121#define SI5341_INX_TO_PFD_SHIFT 4
122
123/* XTAL config bits */
124#define SI5341_XAXB_CFG_EXTCLK_EN BIT(0)
125#define SI5341_XAXB_CFG_PDNB BIT(1)
126
127/* Input dividers (48-bit) */
128#define SI5341_IN_PDIV(x) (0x0208 + ((x) * 10))
129#define SI5341_IN_PSET(x) (0x020E + ((x) * 10))
130#define SI5341_PX_UPD 0x0230
131
132/* PLL configuration */
133#define SI5341_PLL_M_NUM 0x0235
134#define SI5341_PLL_M_DEN 0x023B
135
136/* Output configuration */
137#define SI5341_OUT_CONFIG(output) \
138 ((output)->data->reg_output_offset[(output)->index])
139#define SI5341_OUT_FORMAT(output) (SI5341_OUT_CONFIG(output) + 1)
140#define SI5341_OUT_CM(output) (SI5341_OUT_CONFIG(output) + 2)
141#define SI5341_OUT_MUX_SEL(output) (SI5341_OUT_CONFIG(output) + 3)
142#define SI5341_OUT_R_REG(output) \
143 ((output)->data->reg_rdiv_offset[(output)->index])
144
145#define SI5341_OUT_MUX_VDD_SEL_MASK 0x38
146
147/* Synthesize N divider */
148#define SI5341_SYNTH_N_NUM(x) (0x0302 + ((x) * 11))
149#define SI5341_SYNTH_N_DEN(x) (0x0308 + ((x) * 11))
150#define SI5341_SYNTH_N_UPD(x) (0x030C + ((x) * 11))
151
152/* Synthesizer output enable, phase bypass, power mode */
153#define SI5341_SYNTH_N_CLK_TO_OUTX_EN 0x0A03
154#define SI5341_SYNTH_N_PIBYP 0x0A04
155#define SI5341_SYNTH_N_PDNB 0x0A05
156#define SI5341_SYNTH_N_CLK_DIS 0x0B4A
157
158#define SI5341_REGISTER_MAX 0xBFF
159
160/* SI5341_OUT_CONFIG bits */
161#define SI5341_OUT_CFG_PDN BIT(0)
162#define SI5341_OUT_CFG_OE BIT(1)
163#define SI5341_OUT_CFG_RDIV_FORCE2 BIT(2)
164
165/* Static configuration (to be moved to firmware) */
166struct si5341_reg_default {
167 u16 address;
168 u8 value;
169};
170
171static const char * const si5341_input_clock_names[] = {
172 "in0", "in1", "in2", "xtal"
173};
174
175/* Output configuration registers 0..9 are not quite logically organized */
176/* Also for si5345 */
177static const u16 si5341_reg_output_offset[] = {
178 0x0108,
179 0x010D,
180 0x0112,
181 0x0117,
182 0x011C,
183 0x0121,
184 0x0126,
185 0x012B,
186 0x0130,
187 0x013A,
188};
189
190/* for si5340, si5342 and si5344 */
191static const u16 si5340_reg_output_offset[] = {
192 0x0112,
193 0x0117,
194 0x0126,
195 0x012B,
196};
197
198/* The location of the R divider registers */
199static const u16 si5341_reg_rdiv_offset[] = {
200 0x024A,
201 0x024D,
202 0x0250,
203 0x0253,
204 0x0256,
205 0x0259,
206 0x025C,
207 0x025F,
208 0x0262,
209 0x0268,
210};
211static const u16 si5340_reg_rdiv_offset[] = {
212 0x0250,
213 0x0253,
214 0x025C,
215 0x025F,
216};
217
218/*
219 * Programming sequence from ClockBuilder, settings to initialize the system
220 * using only the XTAL input, without pre-divider.
221 * This also contains settings that aren't mentioned anywhere in the datasheet.
222 * The "known" settings like synth and output configuration are done later.
223 */
224static const struct si5341_reg_default si5341_reg_defaults[] = {
225 { 0x0017, 0x3A }, /* INT mask (disable interrupts) */
226 { 0x0018, 0xFF }, /* INT mask */
227 { 0x0021, 0x0F }, /* Select XTAL as input */
228 { 0x0022, 0x00 }, /* Not in datasheet */
229 { 0x002B, 0x02 }, /* SPI config */
230 { 0x002C, 0x20 }, /* LOS enable for XTAL */
231 { 0x002D, 0x00 }, /* LOS timing */
232 { 0x002E, 0x00 },
233 { 0x002F, 0x00 },
234 { 0x0030, 0x00 },
235 { 0x0031, 0x00 },
236 { 0x0032, 0x00 },
237 { 0x0033, 0x00 },
238 { 0x0034, 0x00 },
239 { 0x0035, 0x00 },
240 { 0x0036, 0x00 },
241 { 0x0037, 0x00 },
242 { 0x0038, 0x00 }, /* LOS setting (thresholds) */
243 { 0x0039, 0x00 },
244 { 0x003A, 0x00 },
245 { 0x003B, 0x00 },
246 { 0x003C, 0x00 },
247 { 0x003D, 0x00 }, /* LOS setting (thresholds) end */
248 { 0x0041, 0x00 }, /* LOS0_DIV_SEL */
249 { 0x0042, 0x00 }, /* LOS1_DIV_SEL */
250 { 0x0043, 0x00 }, /* LOS2_DIV_SEL */
251 { 0x0044, 0x00 }, /* LOS3_DIV_SEL */
252 { 0x009E, 0x00 }, /* Not in datasheet */
253 { 0x0102, 0x01 }, /* Enable outputs */
254 { 0x013F, 0x00 }, /* Not in datasheet */
255 { 0x0140, 0x00 }, /* Not in datasheet */
256 { 0x0141, 0x40 }, /* OUT LOS */
257 { 0x0202, 0x00 }, /* XAXB_FREQ_OFFSET (=0)*/
258 { 0x0203, 0x00 },
259 { 0x0204, 0x00 },
260 { 0x0205, 0x00 },
261 { 0x0206, 0x00 }, /* PXAXB (2^x) */
262 { 0x0208, 0x00 }, /* Px divider setting (usually 0) */
263 { 0x0209, 0x00 },
264 { 0x020A, 0x00 },
265 { 0x020B, 0x00 },
266 { 0x020C, 0x00 },
267 { 0x020D, 0x00 },
268 { 0x020E, 0x00 },
269 { 0x020F, 0x00 },
270 { 0x0210, 0x00 },
271 { 0x0211, 0x00 },
272 { 0x0212, 0x00 },
273 { 0x0213, 0x00 },
274 { 0x0214, 0x00 },
275 { 0x0215, 0x00 },
276 { 0x0216, 0x00 },
277 { 0x0217, 0x00 },
278 { 0x0218, 0x00 },
279 { 0x0219, 0x00 },
280 { 0x021A, 0x00 },
281 { 0x021B, 0x00 },
282 { 0x021C, 0x00 },
283 { 0x021D, 0x00 },
284 { 0x021E, 0x00 },
285 { 0x021F, 0x00 },
286 { 0x0220, 0x00 },
287 { 0x0221, 0x00 },
288 { 0x0222, 0x00 },
289 { 0x0223, 0x00 },
290 { 0x0224, 0x00 },
291 { 0x0225, 0x00 },
292 { 0x0226, 0x00 },
293 { 0x0227, 0x00 },
294 { 0x0228, 0x00 },
295 { 0x0229, 0x00 },
296 { 0x022A, 0x00 },
297 { 0x022B, 0x00 },
298 { 0x022C, 0x00 },
299 { 0x022D, 0x00 },
300 { 0x022E, 0x00 },
301 { 0x022F, 0x00 }, /* Px divider setting (usually 0) end */
302 { 0x026B, 0x00 }, /* DESIGN_ID (ASCII string) */
303 { 0x026C, 0x00 },
304 { 0x026D, 0x00 },
305 { 0x026E, 0x00 },
306 { 0x026F, 0x00 },
307 { 0x0270, 0x00 },
308 { 0x0271, 0x00 },
309 { 0x0272, 0x00 }, /* DESIGN_ID (ASCII string) end */
310 { 0x0339, 0x1F }, /* N_FSTEP_MSK */
311 { 0x033B, 0x00 }, /* Nx_FSTEPW (Frequency step) */
312 { 0x033C, 0x00 },
313 { 0x033D, 0x00 },
314 { 0x033E, 0x00 },
315 { 0x033F, 0x00 },
316 { 0x0340, 0x00 },
317 { 0x0341, 0x00 },
318 { 0x0342, 0x00 },
319 { 0x0343, 0x00 },
320 { 0x0344, 0x00 },
321 { 0x0345, 0x00 },
322 { 0x0346, 0x00 },
323 { 0x0347, 0x00 },
324 { 0x0348, 0x00 },
325 { 0x0349, 0x00 },
326 { 0x034A, 0x00 },
327 { 0x034B, 0x00 },
328 { 0x034C, 0x00 },
329 { 0x034D, 0x00 },
330 { 0x034E, 0x00 },
331 { 0x034F, 0x00 },
332 { 0x0350, 0x00 },
333 { 0x0351, 0x00 },
334 { 0x0352, 0x00 },
335 { 0x0353, 0x00 },
336 { 0x0354, 0x00 },
337 { 0x0355, 0x00 },
338 { 0x0356, 0x00 },
339 { 0x0357, 0x00 },
340 { 0x0358, 0x00 }, /* Nx_FSTEPW (Frequency step) end */
341 { 0x0359, 0x00 }, /* Nx_DELAY */
342 { 0x035A, 0x00 },
343 { 0x035B, 0x00 },
344 { 0x035C, 0x00 },
345 { 0x035D, 0x00 },
346 { 0x035E, 0x00 },
347 { 0x035F, 0x00 },
348 { 0x0360, 0x00 },
349 { 0x0361, 0x00 },
350 { 0x0362, 0x00 }, /* Nx_DELAY end */
351 { 0x0802, 0x00 }, /* Not in datasheet */
352 { 0x0803, 0x00 }, /* Not in datasheet */
353 { 0x0804, 0x00 }, /* Not in datasheet */
354 { 0x090E, 0x02 }, /* XAXB_EXTCLK_EN=0 XAXB_PDNB=1 (use XTAL) */
355 { 0x091C, 0x04 }, /* ZDM_EN=4 (Normal mode) */
356 { 0x0949, 0x00 }, /* IN_EN (disable input clocks) */
357 { 0x094A, 0x00 }, /* INx_TO_PFD_EN (disabled) */
358 { 0x0A02, 0x00 }, /* Not in datasheet */
359 { 0x0B44, 0x0F }, /* PDIV_ENB (datasheet does not mention what it is) */
360 { 0x0B57, 0x10 }, /* VCO_RESET_CALCODE (not described in datasheet) */
361 { 0x0B58, 0x05 }, /* VCO_RESET_CALCODE (not described in datasheet) */
362};
363
364/* Read and interpret a 44-bit followed by a 32-bit value in the regmap */
365static int si5341_decode_44_32(struct regmap *regmap, unsigned int reg,
366 u64 *val1, u32 *val2)
367{
368 int err;
369 u8 r[10];
370
371 err = regmap_bulk_read(map: regmap, reg, val: r, val_count: 10);
372 if (err < 0)
373 return err;
374
375 *val1 = ((u64)((r[5] & 0x0f) << 8 | r[4]) << 32) |
376 (get_unaligned_le32(p: r));
377 *val2 = get_unaligned_le32(p: &r[6]);
378
379 return 0;
380}
381
382static int si5341_encode_44_32(struct regmap *regmap, unsigned int reg,
383 u64 n_num, u32 n_den)
384{
385 u8 r[10];
386
387 /* Shift left as far as possible without overflowing */
388 while (!(n_num & BIT_ULL(43)) && !(n_den & BIT(31))) {
389 n_num <<= 1;
390 n_den <<= 1;
391 }
392
393 /* 44 bits (6 bytes) numerator */
394 put_unaligned_le32(val: n_num, p: r);
395 r[4] = (n_num >> 32) & 0xff;
396 r[5] = (n_num >> 40) & 0x0f;
397 /* 32 bits denominator */
398 put_unaligned_le32(val: n_den, p: &r[6]);
399
400 /* Program the fraction */
401 return regmap_bulk_write(map: regmap, reg, val: r, val_count: sizeof(r));
402}
403
404/* VCO, we assume it runs at a constant frequency */
405static unsigned long si5341_clk_recalc_rate(struct clk_hw *hw,
406 unsigned long parent_rate)
407{
408 struct clk_si5341 *data = to_clk_si5341(hw);
409 int err;
410 u64 res;
411 u64 m_num;
412 u32 m_den;
413 unsigned int shift;
414
415 /* Assume that PDIV is not being used, just read the PLL setting */
416 err = si5341_decode_44_32(regmap: data->regmap, SI5341_PLL_M_NUM,
417 val1: &m_num, val2: &m_den);
418 if (err < 0)
419 return 0;
420
421 if (!m_num || !m_den)
422 return 0;
423
424 /*
425 * Though m_num is 64-bit, only the upper bits are actually used. While
426 * calculating m_num and m_den, they are shifted as far as possible to
427 * the left. To avoid 96-bit division here, we just shift them back so
428 * we can do with just 64 bits.
429 */
430 shift = 0;
431 res = m_num;
432 while (res & 0xffff00000000ULL) {
433 ++shift;
434 res >>= 1;
435 }
436 res *= parent_rate;
437 do_div(res, (m_den >> shift));
438
439 /* We cannot return the actual frequency in 32 bit, store it locally */
440 data->freq_vco = res;
441
442 /* Report kHz since the value is out of range */
443 do_div(res, 1000);
444
445 return (unsigned long)res;
446}
447
448static int si5341_clk_get_selected_input(struct clk_si5341 *data)
449{
450 int err;
451 u32 val;
452
453 err = regmap_read(map: data->regmap, SI5341_IN_SEL, val: &val);
454 if (err < 0)
455 return err;
456
457 return (val & SI5341_IN_SEL_MASK) >> SI5341_IN_SEL_SHIFT;
458}
459
460static u8 si5341_clk_get_parent(struct clk_hw *hw)
461{
462 struct clk_si5341 *data = to_clk_si5341(hw);
463 int res = si5341_clk_get_selected_input(data);
464
465 if (res < 0)
466 return 0; /* Apparently we cannot report errors */
467
468 return res;
469}
470
471static int si5341_clk_reparent(struct clk_si5341 *data, u8 index)
472{
473 int err;
474 u8 val;
475
476 val = (index << SI5341_IN_SEL_SHIFT) & SI5341_IN_SEL_MASK;
477 /* Enable register-based input selection */
478 val |= SI5341_IN_SEL_REGCTRL;
479
480 err = regmap_update_bits(map: data->regmap,
481 SI5341_IN_SEL, SI5341_IN_SEL_REGCTRL | SI5341_IN_SEL_MASK, val);
482 if (err < 0)
483 return err;
484
485 if (index < 3) {
486 /* Enable input buffer for selected input */
487 err = regmap_update_bits(map: data->regmap,
488 SI5341_IN_EN, mask: 0x07, BIT(index));
489 if (err < 0)
490 return err;
491
492 /* Enables the input to phase detector */
493 err = regmap_update_bits(map: data->regmap, SI5341_INX_TO_PFD_EN,
494 mask: 0x7 << SI5341_INX_TO_PFD_SHIFT,
495 BIT(index + SI5341_INX_TO_PFD_SHIFT));
496 if (err < 0)
497 return err;
498
499 /* Power down XTAL oscillator and buffer */
500 err = regmap_update_bits(map: data->regmap, SI5341_XAXB_CFG,
501 SI5341_XAXB_CFG_PDNB, val: 0);
502 if (err < 0)
503 return err;
504
505 /*
506 * Set the P divider to "1". There's no explanation in the
507 * datasheet of these registers, but the clockbuilder software
508 * programs a "1" when the input is being used.
509 */
510 err = regmap_write(map: data->regmap, SI5341_IN_PDIV(index), val: 1);
511 if (err < 0)
512 return err;
513
514 err = regmap_write(map: data->regmap, SI5341_IN_PSET(index), val: 1);
515 if (err < 0)
516 return err;
517
518 /* Set update PDIV bit */
519 err = regmap_write(map: data->regmap, SI5341_PX_UPD, BIT(index));
520 if (err < 0)
521 return err;
522 } else {
523 /* Disable all input buffers */
524 err = regmap_update_bits(map: data->regmap, SI5341_IN_EN, mask: 0x07, val: 0);
525 if (err < 0)
526 return err;
527
528 /* Disable input to phase detector */
529 err = regmap_update_bits(map: data->regmap, SI5341_INX_TO_PFD_EN,
530 mask: 0x7 << SI5341_INX_TO_PFD_SHIFT, val: 0);
531 if (err < 0)
532 return err;
533
534 /* Power up XTAL oscillator and buffer, select clock mode */
535 err = regmap_update_bits(map: data->regmap, SI5341_XAXB_CFG,
536 SI5341_XAXB_CFG_PDNB | SI5341_XAXB_CFG_EXTCLK_EN,
537 SI5341_XAXB_CFG_PDNB | (data->xaxb_ext_clk ?
538 SI5341_XAXB_CFG_EXTCLK_EN : 0));
539 if (err < 0)
540 return err;
541 }
542
543 return 0;
544}
545
546static int si5341_clk_set_parent(struct clk_hw *hw, u8 index)
547{
548 struct clk_si5341 *data = to_clk_si5341(hw);
549
550 return si5341_clk_reparent(data, index);
551}
552
553static const struct clk_ops si5341_clk_ops = {
554 .determine_rate = clk_hw_determine_rate_no_reparent,
555 .set_parent = si5341_clk_set_parent,
556 .get_parent = si5341_clk_get_parent,
557 .recalc_rate = si5341_clk_recalc_rate,
558};
559
560/* Synthesizers, there are 5 synthesizers that connect to any of the outputs */
561
562/* The synthesizer is on if all power and enable bits are set */
563static int si5341_synth_clk_is_on(struct clk_hw *hw)
564{
565 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
566 int err;
567 u32 val;
568 u8 index = synth->index;
569
570 err = regmap_read(map: synth->data->regmap,
571 SI5341_SYNTH_N_CLK_TO_OUTX_EN, val: &val);
572 if (err < 0)
573 return 0;
574
575 if (!(val & BIT(index)))
576 return 0;
577
578 err = regmap_read(map: synth->data->regmap, SI5341_SYNTH_N_PDNB, val: &val);
579 if (err < 0)
580 return 0;
581
582 if (!(val & BIT(index)))
583 return 0;
584
585 /* This bit must be 0 for the synthesizer to receive clock input */
586 err = regmap_read(map: synth->data->regmap, SI5341_SYNTH_N_CLK_DIS, val: &val);
587 if (err < 0)
588 return 0;
589
590 return !(val & BIT(index));
591}
592
593static void si5341_synth_clk_unprepare(struct clk_hw *hw)
594{
595 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
596 u8 index = synth->index; /* In range 0..5 */
597 u8 mask = BIT(index);
598
599 /* Disable output */
600 regmap_update_bits(map: synth->data->regmap,
601 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, val: 0);
602 /* Power down */
603 regmap_update_bits(map: synth->data->regmap,
604 SI5341_SYNTH_N_PDNB, mask, val: 0);
605 /* Disable clock input to synth (set to 1 to disable) */
606 regmap_update_bits(map: synth->data->regmap,
607 SI5341_SYNTH_N_CLK_DIS, mask, val: mask);
608}
609
610static int si5341_synth_clk_prepare(struct clk_hw *hw)
611{
612 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
613 int err;
614 u8 index = synth->index;
615 u8 mask = BIT(index);
616
617 /* Power up */
618 err = regmap_update_bits(map: synth->data->regmap,
619 SI5341_SYNTH_N_PDNB, mask, val: mask);
620 if (err < 0)
621 return err;
622
623 /* Enable clock input to synth (set bit to 0 to enable) */
624 err = regmap_update_bits(map: synth->data->regmap,
625 SI5341_SYNTH_N_CLK_DIS, mask, val: 0);
626 if (err < 0)
627 return err;
628
629 /* Enable output */
630 return regmap_update_bits(map: synth->data->regmap,
631 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, val: mask);
632}
633
634/* Synth clock frequency: Fvco * n_den / n_den, with Fvco in 13500-14256 MHz */
635static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw,
636 unsigned long parent_rate)
637{
638 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
639 u64 f;
640 u64 n_num;
641 u32 n_den;
642 int err;
643
644 err = si5341_decode_44_32(regmap: synth->data->regmap,
645 SI5341_SYNTH_N_NUM(synth->index), val1: &n_num, val2: &n_den);
646 if (err < 0)
647 return err;
648 /* Check for bogus/uninitialized settings */
649 if (!n_num || !n_den)
650 return 0;
651
652 /*
653 * n_num and n_den are shifted left as much as possible, so to prevent
654 * overflow in 64-bit math, we shift n_den 4 bits to the right
655 */
656 f = synth->data->freq_vco;
657 f *= n_den >> 4;
658
659 /* Now we need to do 64-bit division: f/n_num */
660 /* And compensate for the 4 bits we dropped */
661 f = div64_u64(dividend: f, divisor: (n_num >> 4));
662
663 return f;
664}
665
666static int si5341_synth_clk_determine_rate(struct clk_hw *hw,
667 struct clk_rate_request *req)
668{
669 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
670 u64 f;
671
672 /* The synthesizer accuracy is such that anything in range will work */
673 f = synth->data->freq_vco;
674 do_div(f, SI5341_SYNTH_N_MAX);
675 if (req->rate < f) {
676 req->rate = f;
677
678 return 0;
679 }
680
681 f = synth->data->freq_vco;
682 do_div(f, SI5341_SYNTH_N_MIN);
683 if (req->rate > f) {
684 req->rate = f;
685
686 return 0;
687 }
688
689 return 0;
690}
691
692static int si5341_synth_program(struct clk_si5341_synth *synth,
693 u64 n_num, u32 n_den, bool is_integer)
694{
695 int err;
696 u8 index = synth->index;
697
698 err = si5341_encode_44_32(regmap: synth->data->regmap,
699 SI5341_SYNTH_N_NUM(index), n_num, n_den);
700
701 err = regmap_update_bits(map: synth->data->regmap,
702 SI5341_SYNTH_N_PIBYP, BIT(index), val: is_integer ? BIT(index) : 0);
703 if (err < 0)
704 return err;
705
706 return regmap_write(map: synth->data->regmap,
707 SI5341_SYNTH_N_UPD(index), val: 0x01);
708}
709
710
711static int si5341_synth_clk_set_rate(struct clk_hw *hw, unsigned long rate,
712 unsigned long parent_rate)
713{
714 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
715 u64 n_num;
716 u32 n_den;
717 u32 r;
718 u32 g;
719 bool is_integer;
720
721 n_num = synth->data->freq_vco;
722
723 /* see if there's an integer solution */
724 r = do_div(n_num, rate);
725 is_integer = (r == 0);
726 if (is_integer) {
727 /* Integer divider equal to n_num */
728 n_den = 1;
729 } else {
730 /* Calculate a fractional solution */
731 g = gcd(a: r, b: rate);
732 n_den = rate / g;
733 n_num *= n_den;
734 n_num += r / g;
735 }
736
737 dev_dbg(&synth->data->i2c_client->dev,
738 "%s(%u): n=0x%llx d=0x%x %s\n", __func__,
739 synth->index, n_num, n_den,
740 is_integer ? "int" : "frac");
741
742 return si5341_synth_program(synth, n_num, n_den, is_integer);
743}
744
745static const struct clk_ops si5341_synth_clk_ops = {
746 .is_prepared = si5341_synth_clk_is_on,
747 .prepare = si5341_synth_clk_prepare,
748 .unprepare = si5341_synth_clk_unprepare,
749 .recalc_rate = si5341_synth_clk_recalc_rate,
750 .determine_rate = si5341_synth_clk_determine_rate,
751 .set_rate = si5341_synth_clk_set_rate,
752};
753
754static int si5341_output_clk_is_on(struct clk_hw *hw)
755{
756 struct clk_si5341_output *output = to_clk_si5341_output(hw);
757 int err;
758 u32 val;
759
760 err = regmap_read(map: output->data->regmap,
761 SI5341_OUT_CONFIG(output), val: &val);
762 if (err < 0)
763 return err;
764
765 /* Bit 0=PDN, 1=OE so only a value of 0x2 enables the output */
766 return (val & 0x03) == SI5341_OUT_CFG_OE;
767}
768
769/* Disables and then powers down the output */
770static void si5341_output_clk_unprepare(struct clk_hw *hw)
771{
772 struct clk_si5341_output *output = to_clk_si5341_output(hw);
773
774 regmap_update_bits(map: output->data->regmap,
775 SI5341_OUT_CONFIG(output),
776 SI5341_OUT_CFG_OE, val: 0);
777 regmap_update_bits(map: output->data->regmap,
778 SI5341_OUT_CONFIG(output),
779 SI5341_OUT_CFG_PDN, SI5341_OUT_CFG_PDN);
780}
781
782/* Powers up and then enables the output */
783static int si5341_output_clk_prepare(struct clk_hw *hw)
784{
785 struct clk_si5341_output *output = to_clk_si5341_output(hw);
786 int err;
787
788 err = regmap_update_bits(map: output->data->regmap,
789 SI5341_OUT_CONFIG(output),
790 SI5341_OUT_CFG_PDN, val: 0);
791 if (err < 0)
792 return err;
793
794 return regmap_update_bits(map: output->data->regmap,
795 SI5341_OUT_CONFIG(output),
796 SI5341_OUT_CFG_OE, SI5341_OUT_CFG_OE);
797}
798
799static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw,
800 unsigned long parent_rate)
801{
802 struct clk_si5341_output *output = to_clk_si5341_output(hw);
803 int err;
804 u32 val;
805 u32 r_divider;
806 u8 r[3];
807
808 err = regmap_read(map: output->data->regmap,
809 SI5341_OUT_CONFIG(output), val: &val);
810 if (err < 0)
811 return err;
812
813 /* If SI5341_OUT_CFG_RDIV_FORCE2 is set, r_divider is 2 */
814 if (val & SI5341_OUT_CFG_RDIV_FORCE2)
815 return parent_rate / 2;
816
817 err = regmap_bulk_read(map: output->data->regmap,
818 SI5341_OUT_R_REG(output), val: r, val_count: 3);
819 if (err < 0)
820 return err;
821
822 /* Calculate value as 24-bit integer*/
823 r_divider = r[2] << 16 | r[1] << 8 | r[0];
824
825 /* If Rx_REG is zero, the divider is disabled, so return a "0" rate */
826 if (!r_divider)
827 return 0;
828
829 /* Divider is 2*(Rx_REG+1) */
830 r_divider += 1;
831 r_divider <<= 1;
832
833
834 return parent_rate / r_divider;
835}
836
837static int si5341_output_clk_determine_rate(struct clk_hw *hw,
838 struct clk_rate_request *req)
839{
840 unsigned long rate = req->rate;
841 unsigned long r;
842
843 if (!rate)
844 return 0;
845
846 r = req->best_parent_rate >> 1;
847
848 /* If rate is an even divisor, no changes to parent required */
849 if (r && !(r % rate))
850 return 0;
851
852 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
853 if (rate > 200000000) {
854 /* minimum r-divider is 2 */
855 r = 2;
856 } else {
857 /* Take a parent frequency near 400 MHz */
858 r = (400000000u / rate) & ~1;
859 }
860 req->best_parent_rate = r * rate;
861 } else {
862 /* We cannot change our parent's rate, report what we can do */
863 r /= rate;
864 rate = req->best_parent_rate / (r << 1);
865 }
866
867 req->rate = rate;
868 return 0;
869}
870
871static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate,
872 unsigned long parent_rate)
873{
874 struct clk_si5341_output *output = to_clk_si5341_output(hw);
875 u32 r_div;
876 int err;
877 u8 r[3];
878
879 if (!rate)
880 return -EINVAL;
881
882 /* Frequency divider is (r_div + 1) * 2 */
883 r_div = (parent_rate / rate) >> 1;
884
885 if (r_div <= 1)
886 r_div = 0;
887 else if (r_div >= BIT(24))
888 r_div = BIT(24) - 1;
889 else
890 --r_div;
891
892 /* For a value of "2", we set the "OUT0_RDIV_FORCE2" bit */
893 err = regmap_update_bits(map: output->data->regmap,
894 SI5341_OUT_CONFIG(output),
895 SI5341_OUT_CFG_RDIV_FORCE2,
896 val: (r_div == 0) ? SI5341_OUT_CFG_RDIV_FORCE2 : 0);
897 if (err < 0)
898 return err;
899
900 /* Always write Rx_REG, because a zero value disables the divider */
901 r[0] = r_div ? (r_div & 0xff) : 1;
902 r[1] = (r_div >> 8) & 0xff;
903 r[2] = (r_div >> 16) & 0xff;
904 return regmap_bulk_write(map: output->data->regmap,
905 SI5341_OUT_R_REG(output), val: r, val_count: 3);
906}
907
908static int si5341_output_reparent(struct clk_si5341_output *output, u8 index)
909{
910 return regmap_update_bits(map: output->data->regmap,
911 SI5341_OUT_MUX_SEL(output), mask: 0x07, val: index);
912}
913
914static int si5341_output_set_parent(struct clk_hw *hw, u8 index)
915{
916 struct clk_si5341_output *output = to_clk_si5341_output(hw);
917
918 if (index >= output->data->num_synth)
919 return -EINVAL;
920
921 return si5341_output_reparent(output, index);
922}
923
924static u8 si5341_output_get_parent(struct clk_hw *hw)
925{
926 struct clk_si5341_output *output = to_clk_si5341_output(hw);
927 u32 val;
928
929 regmap_read(map: output->data->regmap, SI5341_OUT_MUX_SEL(output), val: &val);
930
931 return val & 0x7;
932}
933
934static const struct clk_ops si5341_output_clk_ops = {
935 .is_prepared = si5341_output_clk_is_on,
936 .prepare = si5341_output_clk_prepare,
937 .unprepare = si5341_output_clk_unprepare,
938 .recalc_rate = si5341_output_clk_recalc_rate,
939 .determine_rate = si5341_output_clk_determine_rate,
940 .set_rate = si5341_output_clk_set_rate,
941 .set_parent = si5341_output_set_parent,
942 .get_parent = si5341_output_get_parent,
943};
944
945/*
946 * The chip can be bought in a pre-programmed version, or one can program the
947 * NVM in the chip to boot up in a preset mode. This routine tries to determine
948 * if that's the case, or if we need to reset and program everything from
949 * scratch. Returns negative error, or true/false.
950 */
951static int si5341_is_programmed_already(struct clk_si5341 *data)
952{
953 int err;
954 u8 r[4];
955
956 /* Read the PLL divider value, it must have a non-zero value */
957 err = regmap_bulk_read(map: data->regmap, SI5341_PLL_M_DEN,
958 val: r, ARRAY_SIZE(r));
959 if (err < 0)
960 return err;
961
962 return !!get_unaligned_le32(p: r);
963}
964
965static struct clk_hw *
966of_clk_si5341_get(struct of_phandle_args *clkspec, void *_data)
967{
968 struct clk_si5341 *data = _data;
969 unsigned int idx = clkspec->args[1];
970 unsigned int group = clkspec->args[0];
971
972 switch (group) {
973 case 0:
974 if (idx >= data->num_outputs) {
975 dev_err(&data->i2c_client->dev,
976 "invalid output index %u\n", idx);
977 return ERR_PTR(error: -EINVAL);
978 }
979 return &data->clk[idx].hw;
980 case 1:
981 if (idx >= data->num_synth) {
982 dev_err(&data->i2c_client->dev,
983 "invalid synthesizer index %u\n", idx);
984 return ERR_PTR(error: -EINVAL);
985 }
986 return &data->synth[idx].hw;
987 case 2:
988 if (idx > 0) {
989 dev_err(&data->i2c_client->dev,
990 "invalid PLL index %u\n", idx);
991 return ERR_PTR(error: -EINVAL);
992 }
993 return &data->hw;
994 default:
995 dev_err(&data->i2c_client->dev, "invalid group %u\n", group);
996 return ERR_PTR(error: -EINVAL);
997 }
998}
999
1000static int si5341_probe_chip_id(struct clk_si5341 *data)
1001{
1002 int err;
1003 u8 reg[4];
1004 u16 model;
1005
1006 err = regmap_bulk_read(map: data->regmap, SI5341_PN_BASE, val: reg,
1007 ARRAY_SIZE(reg));
1008 if (err < 0) {
1009 dev_err(&data->i2c_client->dev, "Failed to read chip ID\n");
1010 return err;
1011 }
1012
1013 model = get_unaligned_le16(p: reg);
1014
1015 dev_info(&data->i2c_client->dev, "Chip: %x Grade: %u Rev: %u\n",
1016 model, reg[2], reg[3]);
1017
1018 switch (model) {
1019 case 0x5340:
1020 data->num_outputs = SI5340_MAX_NUM_OUTPUTS;
1021 data->num_synth = SI5340_NUM_SYNTH;
1022 data->reg_output_offset = si5340_reg_output_offset;
1023 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1024 break;
1025 case 0x5341:
1026 data->num_outputs = SI5341_MAX_NUM_OUTPUTS;
1027 data->num_synth = SI5341_NUM_SYNTH;
1028 data->reg_output_offset = si5341_reg_output_offset;
1029 data->reg_rdiv_offset = si5341_reg_rdiv_offset;
1030 break;
1031 case 0x5342:
1032 data->num_outputs = SI5342_MAX_NUM_OUTPUTS;
1033 data->num_synth = SI5342_NUM_SYNTH;
1034 data->reg_output_offset = si5340_reg_output_offset;
1035 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1036 break;
1037 case 0x5344:
1038 data->num_outputs = SI5344_MAX_NUM_OUTPUTS;
1039 data->num_synth = SI5344_NUM_SYNTH;
1040 data->reg_output_offset = si5340_reg_output_offset;
1041 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1042 break;
1043 case 0x5345:
1044 data->num_outputs = SI5345_MAX_NUM_OUTPUTS;
1045 data->num_synth = SI5345_NUM_SYNTH;
1046 data->reg_output_offset = si5341_reg_output_offset;
1047 data->reg_rdiv_offset = si5341_reg_rdiv_offset;
1048 break;
1049 default:
1050 dev_err(&data->i2c_client->dev, "Model '%x' not supported\n",
1051 model);
1052 return -EINVAL;
1053 }
1054
1055 data->chip_id = model;
1056
1057 return 0;
1058}
1059
1060/* Read active settings into the regmap cache for later reference */
1061static int si5341_read_settings(struct clk_si5341 *data)
1062{
1063 int err;
1064 u8 i;
1065 u8 r[10];
1066
1067 err = regmap_bulk_read(map: data->regmap, SI5341_PLL_M_NUM, val: r, val_count: 10);
1068 if (err < 0)
1069 return err;
1070
1071 err = regmap_bulk_read(map: data->regmap,
1072 SI5341_SYNTH_N_CLK_TO_OUTX_EN, val: r, val_count: 3);
1073 if (err < 0)
1074 return err;
1075
1076 err = regmap_bulk_read(map: data->regmap,
1077 SI5341_SYNTH_N_CLK_DIS, val: r, val_count: 1);
1078 if (err < 0)
1079 return err;
1080
1081 for (i = 0; i < data->num_synth; ++i) {
1082 err = regmap_bulk_read(map: data->regmap,
1083 SI5341_SYNTH_N_NUM(i), val: r, val_count: 10);
1084 if (err < 0)
1085 return err;
1086 }
1087
1088 for (i = 0; i < data->num_outputs; ++i) {
1089 err = regmap_bulk_read(map: data->regmap,
1090 reg: data->reg_output_offset[i], val: r, val_count: 4);
1091 if (err < 0)
1092 return err;
1093
1094 err = regmap_bulk_read(map: data->regmap,
1095 reg: data->reg_rdiv_offset[i], val: r, val_count: 3);
1096 if (err < 0)
1097 return err;
1098 }
1099
1100 return 0;
1101}
1102
1103static int si5341_write_multiple(struct clk_si5341 *data,
1104 const struct si5341_reg_default *values, unsigned int num_values)
1105{
1106 unsigned int i;
1107 int res;
1108
1109 for (i = 0; i < num_values; ++i) {
1110 res = regmap_write(map: data->regmap,
1111 reg: values[i].address, val: values[i].value);
1112 if (res < 0) {
1113 dev_err(&data->i2c_client->dev,
1114 "Failed to write %#x:%#x\n",
1115 values[i].address, values[i].value);
1116 return res;
1117 }
1118 }
1119
1120 return 0;
1121}
1122
1123static const struct si5341_reg_default si5341_preamble[] = {
1124 { 0x0B25, 0x00 },
1125 { 0x0502, 0x01 },
1126 { 0x0505, 0x03 },
1127 { 0x0957, 0x17 },
1128 { 0x0B4E, 0x1A },
1129};
1130
1131static const struct si5341_reg_default si5345_preamble[] = {
1132 { 0x0B25, 0x00 },
1133 { 0x0540, 0x01 },
1134};
1135
1136static int si5341_send_preamble(struct clk_si5341 *data)
1137{
1138 int res;
1139 u32 revision;
1140
1141 /* For revision 2 and up, the values are slightly different */
1142 res = regmap_read(map: data->regmap, SI5341_DEVICE_REV, val: &revision);
1143 if (res < 0)
1144 return res;
1145
1146 /* Write "preamble" as specified by datasheet */
1147 res = regmap_write(map: data->regmap, reg: 0xB24, val: revision < 2 ? 0xD8 : 0xC0);
1148 if (res < 0)
1149 return res;
1150
1151 /* The si5342..si5345 require a different preamble */
1152 if (data->chip_id > 0x5341)
1153 res = si5341_write_multiple(data,
1154 values: si5345_preamble, ARRAY_SIZE(si5345_preamble));
1155 else
1156 res = si5341_write_multiple(data,
1157 values: si5341_preamble, ARRAY_SIZE(si5341_preamble));
1158 if (res < 0)
1159 return res;
1160
1161 /* Datasheet specifies a 300ms wait after sending the preamble */
1162 msleep(msecs: 300);
1163
1164 return 0;
1165}
1166
1167/* Perform a soft reset and write post-amble */
1168static int si5341_finalize_defaults(struct clk_si5341 *data)
1169{
1170 int res;
1171 u32 revision;
1172
1173 res = regmap_write(map: data->regmap, SI5341_IO_VDD_SEL,
1174 val: data->iovdd_33 ? 1 : 0);
1175 if (res < 0)
1176 return res;
1177
1178 res = regmap_read(map: data->regmap, SI5341_DEVICE_REV, val: &revision);
1179 if (res < 0)
1180 return res;
1181
1182 dev_dbg(&data->i2c_client->dev, "%s rev=%u\n", __func__, revision);
1183
1184 res = regmap_write(map: data->regmap, SI5341_SOFT_RST, val: 0x01);
1185 if (res < 0)
1186 return res;
1187
1188 /* The si5342..si5345 have an additional post-amble */
1189 if (data->chip_id > 0x5341) {
1190 res = regmap_write(map: data->regmap, reg: 0x540, val: 0x0);
1191 if (res < 0)
1192 return res;
1193 }
1194
1195 /* Datasheet does not explain these nameless registers */
1196 res = regmap_write(map: data->regmap, reg: 0xB24, val: revision < 2 ? 0xDB : 0xC3);
1197 if (res < 0)
1198 return res;
1199 res = regmap_write(map: data->regmap, reg: 0x0B25, val: 0x02);
1200 if (res < 0)
1201 return res;
1202
1203 return 0;
1204}
1205
1206
1207static const struct regmap_range si5341_regmap_volatile_range[] = {
1208 regmap_reg_range(0x000C, 0x0012), /* Status */
1209 regmap_reg_range(0x001C, 0x001E), /* reset, finc/fdec */
1210 regmap_reg_range(0x00E2, 0x00FE), /* NVM, interrupts, device ready */
1211 /* Update bits for P divider and synth config */
1212 regmap_reg_range(SI5341_PX_UPD, SI5341_PX_UPD),
1213 regmap_reg_range(SI5341_SYNTH_N_UPD(0), SI5341_SYNTH_N_UPD(0)),
1214 regmap_reg_range(SI5341_SYNTH_N_UPD(1), SI5341_SYNTH_N_UPD(1)),
1215 regmap_reg_range(SI5341_SYNTH_N_UPD(2), SI5341_SYNTH_N_UPD(2)),
1216 regmap_reg_range(SI5341_SYNTH_N_UPD(3), SI5341_SYNTH_N_UPD(3)),
1217 regmap_reg_range(SI5341_SYNTH_N_UPD(4), SI5341_SYNTH_N_UPD(4)),
1218};
1219
1220static const struct regmap_access_table si5341_regmap_volatile = {
1221 .yes_ranges = si5341_regmap_volatile_range,
1222 .n_yes_ranges = ARRAY_SIZE(si5341_regmap_volatile_range),
1223};
1224
1225/* Pages 0, 1, 2, 3, 9, A, B are valid, so there are 12 pages */
1226static const struct regmap_range_cfg si5341_regmap_ranges[] = {
1227 {
1228 .range_min = 0,
1229 .range_max = SI5341_REGISTER_MAX,
1230 .selector_reg = SI5341_PAGE,
1231 .selector_mask = 0xff,
1232 .selector_shift = 0,
1233 .window_start = 0,
1234 .window_len = 256,
1235 },
1236};
1237
1238static int si5341_wait_device_ready(struct i2c_client *client)
1239{
1240 int count;
1241
1242 /* Datasheet warns: Any attempt to read or write any register other
1243 * than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt the
1244 * NVM programming and may corrupt the register contents, as they are
1245 * read from NVM. Note that this includes accesses to the PAGE register.
1246 * Also: DEVICE_READY is available on every register page, so no page
1247 * change is needed to read it.
1248 * Do this outside regmap to avoid automatic PAGE register access.
1249 * May take up to 300ms to complete.
1250 */
1251 for (count = 0; count < 15; ++count) {
1252 s32 result = i2c_smbus_read_byte_data(client,
1253 SI5341_DEVICE_READY);
1254 if (result < 0)
1255 return result;
1256 if (result == 0x0F)
1257 return 0;
1258 msleep(msecs: 20);
1259 }
1260 dev_err(&client->dev, "timeout waiting for DEVICE_READY\n");
1261 return -EIO;
1262}
1263
1264static const struct regmap_config si5341_regmap_config = {
1265 .reg_bits = 8,
1266 .val_bits = 8,
1267 .cache_type = REGCACHE_MAPLE,
1268 .ranges = si5341_regmap_ranges,
1269 .num_ranges = ARRAY_SIZE(si5341_regmap_ranges),
1270 .max_register = SI5341_REGISTER_MAX,
1271 .volatile_table = &si5341_regmap_volatile,
1272};
1273
1274static int si5341_dt_parse_dt(struct clk_si5341 *data,
1275 struct clk_si5341_output_config *config)
1276{
1277 struct device_node *child;
1278 struct device_node *np = data->i2c_client->dev.of_node;
1279 u32 num;
1280 u32 val;
1281
1282 memset(config, 0, sizeof(struct clk_si5341_output_config) *
1283 SI5341_MAX_NUM_OUTPUTS);
1284
1285 for_each_child_of_node(np, child) {
1286 if (of_property_read_u32(np: child, propname: "reg", out_value: &num)) {
1287 dev_err(&data->i2c_client->dev, "missing reg property of %s\n",
1288 child->name);
1289 goto put_child;
1290 }
1291
1292 if (num >= SI5341_MAX_NUM_OUTPUTS) {
1293 dev_err(&data->i2c_client->dev, "invalid clkout %d\n", num);
1294 goto put_child;
1295 }
1296
1297 if (!of_property_read_u32(np: child, propname: "silabs,format", out_value: &val)) {
1298 /* Set cm and ampl conservatively to 3v3 settings */
1299 switch (val) {
1300 case 1: /* normal differential */
1301 config[num].out_cm_ampl_bits = 0x33;
1302 break;
1303 case 2: /* low-power differential */
1304 config[num].out_cm_ampl_bits = 0x13;
1305 break;
1306 case 4: /* LVCMOS */
1307 config[num].out_cm_ampl_bits = 0x33;
1308 /* Set SI recommended impedance for LVCMOS */
1309 config[num].out_format_drv_bits |= 0xc0;
1310 break;
1311 default:
1312 dev_err(&data->i2c_client->dev,
1313 "invalid silabs,format %u for %u\n",
1314 val, num);
1315 goto put_child;
1316 }
1317 config[num].out_format_drv_bits &= ~0x07;
1318 config[num].out_format_drv_bits |= val & 0x07;
1319 /* Always enable the SYNC feature */
1320 config[num].out_format_drv_bits |= 0x08;
1321 }
1322
1323 if (!of_property_read_u32(np: child, propname: "silabs,common-mode", out_value: &val)) {
1324 if (val > 0xf) {
1325 dev_err(&data->i2c_client->dev,
1326 "invalid silabs,common-mode %u\n",
1327 val);
1328 goto put_child;
1329 }
1330 config[num].out_cm_ampl_bits &= 0xf0;
1331 config[num].out_cm_ampl_bits |= val & 0x0f;
1332 }
1333
1334 if (!of_property_read_u32(np: child, propname: "silabs,amplitude", out_value: &val)) {
1335 if (val > 0xf) {
1336 dev_err(&data->i2c_client->dev,
1337 "invalid silabs,amplitude %u\n",
1338 val);
1339 goto put_child;
1340 }
1341 config[num].out_cm_ampl_bits &= 0x0f;
1342 config[num].out_cm_ampl_bits |= (val << 4) & 0xf0;
1343 }
1344
1345 if (of_property_read_bool(np: child, propname: "silabs,disable-high"))
1346 config[num].out_format_drv_bits |= 0x10;
1347
1348 config[num].synth_master =
1349 of_property_read_bool(np: child, propname: "silabs,synth-master");
1350
1351 config[num].always_on =
1352 of_property_read_bool(np: child, propname: "always-on");
1353
1354 config[num].vdd_sel_bits = 0x08;
1355 if (data->clk[num].vddo_reg) {
1356 int vdd = regulator_get_voltage(regulator: data->clk[num].vddo_reg);
1357
1358 switch (vdd) {
1359 case 3300000:
1360 config[num].vdd_sel_bits |= 0 << 4;
1361 break;
1362 case 1800000:
1363 config[num].vdd_sel_bits |= 1 << 4;
1364 break;
1365 case 2500000:
1366 config[num].vdd_sel_bits |= 2 << 4;
1367 break;
1368 default:
1369 dev_err(&data->i2c_client->dev,
1370 "unsupported vddo voltage %d for %s\n",
1371 vdd, child->name);
1372 goto put_child;
1373 }
1374 } else {
1375 /* chip seems to default to 2.5V when not set */
1376 dev_warn(&data->i2c_client->dev,
1377 "no regulator set, defaulting vdd_sel to 2.5V for %s\n",
1378 child->name);
1379 config[num].vdd_sel_bits |= 2 << 4;
1380 }
1381 }
1382
1383 return 0;
1384
1385put_child:
1386 of_node_put(node: child);
1387 return -EINVAL;
1388}
1389
1390/*
1391 * If not pre-configured, calculate and set the PLL configuration manually.
1392 * For low-jitter performance, the PLL should be set such that the synthesizers
1393 * only need integer division.
1394 * Without any user guidance, we'll set the PLL to 14GHz, which still allows
1395 * the chip to generate any frequency on its outputs, but jitter performance
1396 * may be sub-optimal.
1397 */
1398static int si5341_initialize_pll(struct clk_si5341 *data)
1399{
1400 struct device_node *np = data->i2c_client->dev.of_node;
1401 u32 m_num = 0;
1402 u32 m_den = 0;
1403 int sel;
1404
1405 if (of_property_read_u32(np, propname: "silabs,pll-m-num", out_value: &m_num)) {
1406 dev_err(&data->i2c_client->dev,
1407 "PLL configuration requires silabs,pll-m-num\n");
1408 }
1409 if (of_property_read_u32(np, propname: "silabs,pll-m-den", out_value: &m_den)) {
1410 dev_err(&data->i2c_client->dev,
1411 "PLL configuration requires silabs,pll-m-den\n");
1412 }
1413
1414 if (!m_num || !m_den) {
1415 dev_err(&data->i2c_client->dev,
1416 "PLL configuration invalid, assume 14GHz\n");
1417 sel = si5341_clk_get_selected_input(data);
1418 if (sel < 0)
1419 return sel;
1420
1421 m_den = clk_get_rate(clk: data->input_clk[sel]) / 10;
1422 m_num = 1400000000;
1423 }
1424
1425 return si5341_encode_44_32(regmap: data->regmap,
1426 SI5341_PLL_M_NUM, n_num: m_num, n_den: m_den);
1427}
1428
1429static int si5341_clk_select_active_input(struct clk_si5341 *data)
1430{
1431 int res;
1432 int err;
1433 int i;
1434
1435 res = si5341_clk_get_selected_input(data);
1436 if (res < 0)
1437 return res;
1438
1439 /* If the current register setting is invalid, pick the first input */
1440 if (!data->input_clk[res]) {
1441 dev_dbg(&data->i2c_client->dev,
1442 "Input %d not connected, rerouting\n", res);
1443 res = -ENODEV;
1444 for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
1445 if (data->input_clk[i]) {
1446 res = i;
1447 break;
1448 }
1449 }
1450 if (res < 0) {
1451 dev_err(&data->i2c_client->dev,
1452 "No clock input available\n");
1453 return res;
1454 }
1455 }
1456
1457 /* Make sure the selected clock is also enabled and routed */
1458 err = si5341_clk_reparent(data, index: res);
1459 if (err < 0)
1460 return err;
1461
1462 err = clk_prepare_enable(clk: data->input_clk[res]);
1463 if (err < 0)
1464 return err;
1465
1466 return res;
1467}
1468
1469static ssize_t input_present_show(struct device *dev,
1470 struct device_attribute *attr,
1471 char *buf)
1472{
1473 struct clk_si5341 *data = dev_get_drvdata(dev);
1474 u32 status;
1475 int res = regmap_read(map: data->regmap, SI5341_STATUS, val: &status);
1476
1477 if (res < 0)
1478 return res;
1479 res = !(status & SI5341_STATUS_LOSREF);
1480 return sysfs_emit(buf, fmt: "%d\n", res);
1481}
1482static DEVICE_ATTR_RO(input_present);
1483
1484static ssize_t input_present_sticky_show(struct device *dev,
1485 struct device_attribute *attr,
1486 char *buf)
1487{
1488 struct clk_si5341 *data = dev_get_drvdata(dev);
1489 u32 status;
1490 int res = regmap_read(map: data->regmap, SI5341_STATUS_STICKY, val: &status);
1491
1492 if (res < 0)
1493 return res;
1494 res = !(status & SI5341_STATUS_LOSREF);
1495 return sysfs_emit(buf, fmt: "%d\n", res);
1496}
1497static DEVICE_ATTR_RO(input_present_sticky);
1498
1499static ssize_t pll_locked_show(struct device *dev,
1500 struct device_attribute *attr,
1501 char *buf)
1502{
1503 struct clk_si5341 *data = dev_get_drvdata(dev);
1504 u32 status;
1505 int res = regmap_read(map: data->regmap, SI5341_STATUS, val: &status);
1506
1507 if (res < 0)
1508 return res;
1509 res = !(status & SI5341_STATUS_LOL);
1510 return sysfs_emit(buf, fmt: "%d\n", res);
1511}
1512static DEVICE_ATTR_RO(pll_locked);
1513
1514static ssize_t pll_locked_sticky_show(struct device *dev,
1515 struct device_attribute *attr,
1516 char *buf)
1517{
1518 struct clk_si5341 *data = dev_get_drvdata(dev);
1519 u32 status;
1520 int res = regmap_read(map: data->regmap, SI5341_STATUS_STICKY, val: &status);
1521
1522 if (res < 0)
1523 return res;
1524 res = !(status & SI5341_STATUS_LOL);
1525 return sysfs_emit(buf, fmt: "%d\n", res);
1526}
1527static DEVICE_ATTR_RO(pll_locked_sticky);
1528
1529static ssize_t clear_sticky_store(struct device *dev,
1530 struct device_attribute *attr,
1531 const char *buf, size_t count)
1532{
1533 struct clk_si5341 *data = dev_get_drvdata(dev);
1534 long val;
1535
1536 if (kstrtol(s: buf, base: 10, res: &val))
1537 return -EINVAL;
1538 if (val) {
1539 int res = regmap_write(map: data->regmap, SI5341_STATUS_STICKY, val: 0);
1540
1541 if (res < 0)
1542 return res;
1543 }
1544 return count;
1545}
1546static DEVICE_ATTR_WO(clear_sticky);
1547
1548static const struct attribute *si5341_attributes[] = {
1549 &dev_attr_input_present.attr,
1550 &dev_attr_input_present_sticky.attr,
1551 &dev_attr_pll_locked.attr,
1552 &dev_attr_pll_locked_sticky.attr,
1553 &dev_attr_clear_sticky.attr,
1554 NULL
1555};
1556
1557static int si5341_probe(struct i2c_client *client)
1558{
1559 struct clk_si5341 *data;
1560 struct clk_init_data init;
1561 struct clk *input;
1562 const char *root_clock_name;
1563 const char *synth_clock_names[SI5341_NUM_SYNTH] = { NULL };
1564 int err;
1565 unsigned int i;
1566 struct clk_si5341_output_config config[SI5341_MAX_NUM_OUTPUTS];
1567 bool initialization_required;
1568 u32 status;
1569
1570 data = devm_kzalloc(dev: &client->dev, size: sizeof(*data), GFP_KERNEL);
1571 if (!data)
1572 return -ENOMEM;
1573
1574 data->i2c_client = client;
1575
1576 /* Must be done before otherwise touching hardware */
1577 err = si5341_wait_device_ready(client);
1578 if (err)
1579 return err;
1580
1581 for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
1582 input = devm_clk_get(dev: &client->dev, id: si5341_input_clock_names[i]);
1583 if (IS_ERR(ptr: input)) {
1584 if (PTR_ERR(ptr: input) == -EPROBE_DEFER)
1585 return -EPROBE_DEFER;
1586 data->input_clk_name[i] = si5341_input_clock_names[i];
1587 } else {
1588 data->input_clk[i] = input;
1589 data->input_clk_name[i] = __clk_get_name(clk: input);
1590 }
1591 }
1592
1593 for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) {
1594 char reg_name[10];
1595
1596 snprintf(buf: reg_name, size: sizeof(reg_name), fmt: "vddo%d", i);
1597 data->clk[i].vddo_reg = devm_regulator_get_optional(
1598 dev: &client->dev, id: reg_name);
1599 if (IS_ERR(ptr: data->clk[i].vddo_reg)) {
1600 err = PTR_ERR(ptr: data->clk[i].vddo_reg);
1601 data->clk[i].vddo_reg = NULL;
1602 if (err == -ENODEV)
1603 continue;
1604 goto cleanup;
1605 } else {
1606 err = regulator_enable(regulator: data->clk[i].vddo_reg);
1607 if (err) {
1608 dev_err(&client->dev,
1609 "failed to enable %s regulator: %d\n",
1610 reg_name, err);
1611 data->clk[i].vddo_reg = NULL;
1612 goto cleanup;
1613 }
1614 }
1615 }
1616
1617 err = si5341_dt_parse_dt(data, config);
1618 if (err)
1619 goto cleanup;
1620
1621 if (of_property_read_string(np: client->dev.of_node, propname: "clock-output-names",
1622 out_string: &init.name))
1623 init.name = client->dev.of_node->name;
1624 root_clock_name = init.name;
1625
1626 data->regmap = devm_regmap_init_i2c(client, &si5341_regmap_config);
1627 if (IS_ERR(ptr: data->regmap)) {
1628 err = PTR_ERR(ptr: data->regmap);
1629 goto cleanup;
1630 }
1631
1632 i2c_set_clientdata(client, data);
1633
1634 err = si5341_probe_chip_id(data);
1635 if (err < 0)
1636 goto cleanup;
1637
1638 if (of_property_read_bool(np: client->dev.of_node, propname: "silabs,reprogram")) {
1639 initialization_required = true;
1640 } else {
1641 err = si5341_is_programmed_already(data);
1642 if (err < 0)
1643 goto cleanup;
1644
1645 initialization_required = !err;
1646 }
1647 data->xaxb_ext_clk = of_property_read_bool(np: client->dev.of_node,
1648 propname: "silabs,xaxb-ext-clk");
1649 data->iovdd_33 = of_property_read_bool(np: client->dev.of_node,
1650 propname: "silabs,iovdd-33");
1651
1652 if (initialization_required) {
1653 /* Populate the regmap cache in preparation for "cache only" */
1654 err = si5341_read_settings(data);
1655 if (err < 0)
1656 goto cleanup;
1657
1658 err = si5341_send_preamble(data);
1659 if (err < 0)
1660 goto cleanup;
1661
1662 /*
1663 * We intend to send all 'final' register values in a single
1664 * transaction. So cache all register writes until we're done
1665 * configuring.
1666 */
1667 regcache_cache_only(map: data->regmap, enable: true);
1668
1669 /* Write the configuration pairs from the firmware blob */
1670 err = si5341_write_multiple(data, values: si5341_reg_defaults,
1671 ARRAY_SIZE(si5341_reg_defaults));
1672 if (err < 0)
1673 goto cleanup;
1674 }
1675
1676 /* Input must be up and running at this point */
1677 err = si5341_clk_select_active_input(data);
1678 if (err < 0)
1679 goto cleanup;
1680
1681 if (initialization_required) {
1682 /* PLL configuration is required */
1683 err = si5341_initialize_pll(data);
1684 if (err < 0)
1685 goto cleanup;
1686 }
1687
1688 /* Register the PLL */
1689 init.parent_names = data->input_clk_name;
1690 init.num_parents = SI5341_NUM_INPUTS;
1691 init.ops = &si5341_clk_ops;
1692 init.flags = 0;
1693 data->hw.init = &init;
1694
1695 err = devm_clk_hw_register(dev: &client->dev, hw: &data->hw);
1696 if (err) {
1697 dev_err(&client->dev, "clock registration failed\n");
1698 goto cleanup;
1699 }
1700
1701 init.num_parents = 1;
1702 init.parent_names = &root_clock_name;
1703 init.ops = &si5341_synth_clk_ops;
1704 for (i = 0; i < data->num_synth; ++i) {
1705 synth_clock_names[i] = devm_kasprintf(dev: &client->dev, GFP_KERNEL,
1706 fmt: "%s.N%u", client->dev.of_node->name, i);
1707 if (!synth_clock_names[i]) {
1708 err = -ENOMEM;
1709 goto free_clk_names;
1710 }
1711 init.name = synth_clock_names[i];
1712 data->synth[i].index = i;
1713 data->synth[i].data = data;
1714 data->synth[i].hw.init = &init;
1715 err = devm_clk_hw_register(dev: &client->dev, hw: &data->synth[i].hw);
1716 if (err) {
1717 dev_err(&client->dev,
1718 "synth N%u registration failed\n", i);
1719 goto free_clk_names;
1720 }
1721 }
1722
1723 init.num_parents = data->num_synth;
1724 init.parent_names = synth_clock_names;
1725 init.ops = &si5341_output_clk_ops;
1726 for (i = 0; i < data->num_outputs; ++i) {
1727 init.name = kasprintf(GFP_KERNEL, fmt: "%s.%d",
1728 client->dev.of_node->name, i);
1729 if (!init.name) {
1730 err = -ENOMEM;
1731 goto free_clk_names;
1732 }
1733 init.flags = config[i].synth_master ? CLK_SET_RATE_PARENT : 0;
1734 data->clk[i].index = i;
1735 data->clk[i].data = data;
1736 data->clk[i].hw.init = &init;
1737 if (config[i].out_format_drv_bits & 0x07) {
1738 regmap_write(map: data->regmap,
1739 SI5341_OUT_FORMAT(&data->clk[i]),
1740 val: config[i].out_format_drv_bits);
1741 regmap_write(map: data->regmap,
1742 SI5341_OUT_CM(&data->clk[i]),
1743 val: config[i].out_cm_ampl_bits);
1744 regmap_update_bits(map: data->regmap,
1745 SI5341_OUT_MUX_SEL(&data->clk[i]),
1746 SI5341_OUT_MUX_VDD_SEL_MASK,
1747 val: config[i].vdd_sel_bits);
1748 }
1749 err = devm_clk_hw_register(dev: &client->dev, hw: &data->clk[i].hw);
1750 kfree(objp: init.name); /* clock framework made a copy of the name */
1751 if (err) {
1752 dev_err(&client->dev,
1753 "output %u registration failed\n", i);
1754 goto free_clk_names;
1755 }
1756 if (config[i].always_on)
1757 clk_prepare(clk: data->clk[i].hw.clk);
1758 }
1759
1760 err = devm_of_clk_add_hw_provider(dev: &client->dev, get: of_clk_si5341_get,
1761 data);
1762 if (err) {
1763 dev_err(&client->dev, "unable to add clk provider\n");
1764 goto free_clk_names;
1765 }
1766
1767 if (initialization_required) {
1768 /* Synchronize */
1769 regcache_cache_only(map: data->regmap, enable: false);
1770 err = regcache_sync(map: data->regmap);
1771 if (err < 0)
1772 goto free_clk_names;
1773
1774 err = si5341_finalize_defaults(data);
1775 if (err < 0)
1776 goto free_clk_names;
1777 }
1778
1779 /* wait for device to report input clock present and PLL lock */
1780 err = regmap_read_poll_timeout(data->regmap, SI5341_STATUS, status,
1781 !(status & (SI5341_STATUS_LOSREF | SI5341_STATUS_LOL)),
1782 10000, 250000);
1783 if (err) {
1784 dev_err(&client->dev, "Error waiting for input clock or PLL lock\n");
1785 goto free_clk_names;
1786 }
1787
1788 /* clear sticky alarm bits from initialization */
1789 err = regmap_write(map: data->regmap, SI5341_STATUS_STICKY, val: 0);
1790 if (err) {
1791 dev_err(&client->dev, "unable to clear sticky status\n");
1792 goto free_clk_names;
1793 }
1794
1795 err = sysfs_create_files(kobj: &client->dev.kobj, attr: si5341_attributes);
1796 if (err)
1797 dev_err(&client->dev, "unable to create sysfs files\n");
1798
1799free_clk_names:
1800 /* Free the names, clk framework makes copies */
1801 for (i = 0; i < data->num_synth; ++i)
1802 devm_kfree(dev: &client->dev, p: (void *)synth_clock_names[i]);
1803
1804cleanup:
1805 if (err) {
1806 for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) {
1807 if (data->clk[i].vddo_reg)
1808 regulator_disable(regulator: data->clk[i].vddo_reg);
1809 }
1810 }
1811 return err;
1812}
1813
1814static void si5341_remove(struct i2c_client *client)
1815{
1816 struct clk_si5341 *data = i2c_get_clientdata(client);
1817 int i;
1818
1819 sysfs_remove_files(kobj: &client->dev.kobj, attr: si5341_attributes);
1820
1821 for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) {
1822 if (data->clk[i].vddo_reg)
1823 regulator_disable(regulator: data->clk[i].vddo_reg);
1824 }
1825}
1826
1827static const struct i2c_device_id si5341_id[] = {
1828 { "si5340", 0 },
1829 { "si5341", 1 },
1830 { "si5342", 2 },
1831 { "si5344", 4 },
1832 { "si5345", 5 },
1833 { }
1834};
1835MODULE_DEVICE_TABLE(i2c, si5341_id);
1836
1837static const struct of_device_id clk_si5341_of_match[] = {
1838 { .compatible = "silabs,si5340" },
1839 { .compatible = "silabs,si5341" },
1840 { .compatible = "silabs,si5342" },
1841 { .compatible = "silabs,si5344" },
1842 { .compatible = "silabs,si5345" },
1843 { }
1844};
1845MODULE_DEVICE_TABLE(of, clk_si5341_of_match);
1846
1847static struct i2c_driver si5341_driver = {
1848 .driver = {
1849 .name = "si5341",
1850 .of_match_table = clk_si5341_of_match,
1851 },
1852 .probe = si5341_probe,
1853 .remove = si5341_remove,
1854 .id_table = si5341_id,
1855};
1856module_i2c_driver(si5341_driver);
1857
1858MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
1859MODULE_DESCRIPTION("Si5341 driver");
1860MODULE_LICENSE("GPL");
1861

source code of linux/drivers/clk/clk-si5341.c