1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 Socionext Inc.
4 * Copyright (C) 2016 Linaro Ltd.
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/err.h>
9#include <linux/io.h>
10#include <linux/iopoll.h>
11#include <linux/of_address.h>
12#include <linux/platform_device.h>
13#include <linux/slab.h>
14#include <linux/spinlock.h>
15
16#define M10V_CLKSEL1 0x0
17#define CLKSEL(n) (((n) - 1) * 4 + M10V_CLKSEL1)
18
19#define M10V_PLL1 "pll1"
20#define M10V_PLL1DIV2 "pll1-2"
21#define M10V_PLL2 "pll2"
22#define M10V_PLL2DIV2 "pll2-2"
23#define M10V_PLL6 "pll6"
24#define M10V_PLL6DIV2 "pll6-2"
25#define M10V_PLL6DIV3 "pll6-3"
26#define M10V_PLL7 "pll7"
27#define M10V_PLL7DIV2 "pll7-2"
28#define M10V_PLL7DIV5 "pll7-5"
29#define M10V_PLL9 "pll9"
30#define M10V_PLL10 "pll10"
31#define M10V_PLL10DIV2 "pll10-2"
32#define M10V_PLL11 "pll11"
33
34#define M10V_SPI_PARENT0 "spi-parent0"
35#define M10V_SPI_PARENT1 "spi-parent1"
36#define M10V_SPI_PARENT2 "spi-parent2"
37#define M10V_UHS1CLK2_PARENT0 "uhs1clk2-parent0"
38#define M10V_UHS1CLK2_PARENT1 "uhs1clk2-parent1"
39#define M10V_UHS1CLK2_PARENT2 "uhs1clk2-parent2"
40#define M10V_UHS1CLK1_PARENT0 "uhs1clk1-parent0"
41#define M10V_UHS1CLK1_PARENT1 "uhs1clk1-parent1"
42#define M10V_NFCLK_PARENT0 "nfclk-parent0"
43#define M10V_NFCLK_PARENT1 "nfclk-parent1"
44#define M10V_NFCLK_PARENT2 "nfclk-parent2"
45#define M10V_NFCLK_PARENT3 "nfclk-parent3"
46#define M10V_NFCLK_PARENT4 "nfclk-parent4"
47#define M10V_NFCLK_PARENT5 "nfclk-parent5"
48
49#define M10V_DCHREQ 1
50#define M10V_UPOLL_RATE 1
51#define M10V_UTIMEOUT 250
52
53#define M10V_EMMCCLK_ID 0
54#define M10V_ACLK_ID 1
55#define M10V_HCLK_ID 2
56#define M10V_PCLK_ID 3
57#define M10V_RCLK_ID 4
58#define M10V_SPICLK_ID 5
59#define M10V_NFCLK_ID 6
60#define M10V_UHS1CLK2_ID 7
61#define M10V_NUM_CLKS 8
62
63#define to_m10v_div(_hw) container_of(_hw, struct m10v_clk_divider, hw)
64
65static struct clk_hw_onecell_data *m10v_clk_data;
66
67static DEFINE_SPINLOCK(m10v_crglock);
68
69struct m10v_clk_div_factors {
70 const char *name;
71 const char *parent_name;
72 u32 offset;
73 u8 shift;
74 u8 width;
75 const struct clk_div_table *table;
76 unsigned long div_flags;
77 int onecell_idx;
78};
79
80struct m10v_clk_div_fixed_data {
81 const char *name;
82 const char *parent_name;
83 u8 div;
84 u8 mult;
85 int onecell_idx;
86};
87
88struct m10v_clk_mux_factors {
89 const char *name;
90 const char * const *parent_names;
91 u8 num_parents;
92 u32 offset;
93 u8 shift;
94 u8 mask;
95 u32 *table;
96 unsigned long mux_flags;
97 int onecell_idx;
98};
99
100static const struct clk_div_table emmcclk_table[] = {
101 { .val = 0, .div = 8 },
102 { .val = 1, .div = 9 },
103 { .val = 2, .div = 10 },
104 { .val = 3, .div = 15 },
105 { .div = 0 },
106};
107
108static const struct clk_div_table mclk400_table[] = {
109 { .val = 1, .div = 2 },
110 { .val = 3, .div = 4 },
111 { .div = 0 },
112};
113
114static const struct clk_div_table mclk200_table[] = {
115 { .val = 3, .div = 4 },
116 { .val = 7, .div = 8 },
117 { .div = 0 },
118};
119
120static const struct clk_div_table aclk400_table[] = {
121 { .val = 1, .div = 2 },
122 { .val = 3, .div = 4 },
123 { .div = 0 },
124};
125
126static const struct clk_div_table aclk300_table[] = {
127 { .val = 0, .div = 2 },
128 { .val = 1, .div = 3 },
129 { .div = 0 },
130};
131
132static const struct clk_div_table aclk_table[] = {
133 { .val = 3, .div = 4 },
134 { .val = 7, .div = 8 },
135 { .div = 0 },
136};
137
138static const struct clk_div_table aclkexs_table[] = {
139 { .val = 3, .div = 4 },
140 { .val = 4, .div = 5 },
141 { .val = 5, .div = 6 },
142 { .val = 7, .div = 8 },
143 { .div = 0 },
144};
145
146static const struct clk_div_table hclk_table[] = {
147 { .val = 7, .div = 8 },
148 { .val = 15, .div = 16 },
149 { .div = 0 },
150};
151
152static const struct clk_div_table hclkbmh_table[] = {
153 { .val = 3, .div = 4 },
154 { .val = 7, .div = 8 },
155 { .div = 0 },
156};
157
158static const struct clk_div_table pclk_table[] = {
159 { .val = 15, .div = 16 },
160 { .val = 31, .div = 32 },
161 { .div = 0 },
162};
163
164static const struct clk_div_table rclk_table[] = {
165 { .val = 0, .div = 8 },
166 { .val = 1, .div = 16 },
167 { .val = 2, .div = 24 },
168 { .val = 3, .div = 32 },
169 { .div = 0 },
170};
171
172static const struct clk_div_table uhs1clk0_table[] = {
173 { .val = 0, .div = 2 },
174 { .val = 1, .div = 3 },
175 { .val = 2, .div = 4 },
176 { .val = 3, .div = 8 },
177 { .val = 4, .div = 16 },
178 { .div = 0 },
179};
180
181static const struct clk_div_table uhs2clk_table[] = {
182 { .val = 0, .div = 9 },
183 { .val = 1, .div = 10 },
184 { .val = 2, .div = 11 },
185 { .val = 3, .div = 12 },
186 { .val = 4, .div = 13 },
187 { .val = 5, .div = 14 },
188 { .val = 6, .div = 16 },
189 { .val = 7, .div = 18 },
190 { .div = 0 },
191};
192
193static u32 spi_mux_table[] = {0, 1, 2};
194static const char * const spi_mux_names[] = {
195 M10V_SPI_PARENT0, M10V_SPI_PARENT1, M10V_SPI_PARENT2
196};
197
198static u32 uhs1clk2_mux_table[] = {2, 3, 4, 8};
199static const char * const uhs1clk2_mux_names[] = {
200 M10V_UHS1CLK2_PARENT0, M10V_UHS1CLK2_PARENT1,
201 M10V_UHS1CLK2_PARENT2, M10V_PLL6DIV2
202};
203
204static u32 uhs1clk1_mux_table[] = {3, 4, 8};
205static const char * const uhs1clk1_mux_names[] = {
206 M10V_UHS1CLK1_PARENT0, M10V_UHS1CLK1_PARENT1, M10V_PLL6DIV2
207};
208
209static u32 nfclk_mux_table[] = {0, 1, 2, 3, 4, 8};
210static const char * const nfclk_mux_names[] = {
211 M10V_NFCLK_PARENT0, M10V_NFCLK_PARENT1, M10V_NFCLK_PARENT2,
212 M10V_NFCLK_PARENT3, M10V_NFCLK_PARENT4, M10V_NFCLK_PARENT5
213};
214
215static const struct m10v_clk_div_fixed_data m10v_pll_fixed_data[] = {
216 {M10V_PLL1, NULL, 1, 40, -1},
217 {M10V_PLL2, NULL, 1, 30, -1},
218 {M10V_PLL6, NULL, 1, 35, -1},
219 {M10V_PLL7, NULL, 1, 40, -1},
220 {M10V_PLL9, NULL, 1, 33, -1},
221 {M10V_PLL10, NULL, 5, 108, -1},
222 {M10V_PLL10DIV2, M10V_PLL10, 2, 1, -1},
223 {M10V_PLL11, NULL, 2, 75, -1},
224};
225
226static const struct m10v_clk_div_fixed_data m10v_div_fixed_data[] = {
227 {"usb2", NULL, 2, 1, -1},
228 {"pcisuppclk", NULL, 20, 1, -1},
229 {M10V_PLL1DIV2, M10V_PLL1, 2, 1, -1},
230 {M10V_PLL2DIV2, M10V_PLL2, 2, 1, -1},
231 {M10V_PLL6DIV2, M10V_PLL6, 2, 1, -1},
232 {M10V_PLL6DIV3, M10V_PLL6, 3, 1, -1},
233 {M10V_PLL7DIV2, M10V_PLL7, 2, 1, -1},
234 {M10V_PLL7DIV5, M10V_PLL7, 5, 1, -1},
235 {"ca7wd", M10V_PLL2DIV2, 12, 1, -1},
236 {"pclkca7wd", M10V_PLL1DIV2, 16, 1, -1},
237 {M10V_SPI_PARENT0, M10V_PLL10DIV2, 2, 1, -1},
238 {M10V_SPI_PARENT1, M10V_PLL10DIV2, 4, 1, -1},
239 {M10V_SPI_PARENT2, M10V_PLL7DIV2, 8, 1, -1},
240 {M10V_UHS1CLK2_PARENT0, M10V_PLL7, 4, 1, -1},
241 {M10V_UHS1CLK2_PARENT1, M10V_PLL7, 8, 1, -1},
242 {M10V_UHS1CLK2_PARENT2, M10V_PLL7, 16, 1, -1},
243 {M10V_UHS1CLK1_PARENT0, M10V_PLL7, 8, 1, -1},
244 {M10V_UHS1CLK1_PARENT1, M10V_PLL7, 16, 1, -1},
245 {M10V_NFCLK_PARENT0, M10V_PLL7DIV2, 8, 1, -1},
246 {M10V_NFCLK_PARENT1, M10V_PLL7DIV2, 10, 1, -1},
247 {M10V_NFCLK_PARENT2, M10V_PLL7DIV2, 13, 1, -1},
248 {M10V_NFCLK_PARENT3, M10V_PLL7DIV2, 16, 1, -1},
249 {M10V_NFCLK_PARENT4, M10V_PLL7DIV2, 40, 1, -1},
250 {M10V_NFCLK_PARENT5, M10V_PLL7DIV5, 10, 1, -1},
251};
252
253static const struct m10v_clk_div_factors m10v_div_factor_data[] = {
254 {"emmc", M10V_PLL11, CLKSEL(1), 28, 3, emmcclk_table, 0,
255 M10V_EMMCCLK_ID},
256 {"mclk400", M10V_PLL1DIV2, CLKSEL(10), 7, 3, mclk400_table, 0, -1},
257 {"mclk200", M10V_PLL1DIV2, CLKSEL(10), 3, 4, mclk200_table, 0, -1},
258 {"aclk400", M10V_PLL1DIV2, CLKSEL(10), 0, 3, aclk400_table, 0, -1},
259 {"aclk300", M10V_PLL2DIV2, CLKSEL(12), 0, 2, aclk300_table, 0, -1},
260 {"aclk", M10V_PLL1DIV2, CLKSEL(9), 20, 4, aclk_table, 0, M10V_ACLK_ID},
261 {"aclkexs", M10V_PLL1DIV2, CLKSEL(9), 16, 4, aclkexs_table, 0, -1},
262 {"hclk", M10V_PLL1DIV2, CLKSEL(9), 7, 5, hclk_table, 0, M10V_HCLK_ID},
263 {"hclkbmh", M10V_PLL1DIV2, CLKSEL(9), 12, 4, hclkbmh_table, 0, -1},
264 {"pclk", M10V_PLL1DIV2, CLKSEL(9), 0, 7, pclk_table, 0, M10V_PCLK_ID},
265 {"uhs1clk0", M10V_PLL7, CLKSEL(1), 3, 5, uhs1clk0_table, 0, -1},
266 {"uhs2clk", M10V_PLL6DIV3, CLKSEL(1), 18, 4, uhs2clk_table, 0, -1},
267};
268
269static const struct m10v_clk_mux_factors m10v_mux_factor_data[] = {
270 {"spi", spi_mux_names, ARRAY_SIZE(spi_mux_names),
271 CLKSEL(8), 3, 7, spi_mux_table, 0, M10V_SPICLK_ID},
272 {"uhs1clk2", uhs1clk2_mux_names, ARRAY_SIZE(uhs1clk2_mux_names),
273 CLKSEL(1), 13, 31, uhs1clk2_mux_table, 0, M10V_UHS1CLK2_ID},
274 {"uhs1clk1", uhs1clk1_mux_names, ARRAY_SIZE(uhs1clk1_mux_names),
275 CLKSEL(1), 8, 31, uhs1clk1_mux_table, 0, -1},
276 {"nfclk", nfclk_mux_names, ARRAY_SIZE(nfclk_mux_names),
277 CLKSEL(1), 22, 127, nfclk_mux_table, 0, M10V_NFCLK_ID},
278};
279
280static u8 m10v_mux_get_parent(struct clk_hw *hw)
281{
282 struct clk_mux *mux = to_clk_mux(hw);
283 u32 val;
284
285 val = readl(addr: mux->reg) >> mux->shift;
286 val &= mux->mask;
287
288 return clk_mux_val_to_index(hw, table: mux->table, flags: mux->flags, val);
289}
290
291static int m10v_mux_set_parent(struct clk_hw *hw, u8 index)
292{
293 struct clk_mux *mux = to_clk_mux(hw);
294 u32 val = clk_mux_index_to_val(table: mux->table, flags: mux->flags, index);
295 unsigned long flags = 0;
296 u32 reg;
297 u32 write_en = BIT(fls(mux->mask) - 1);
298
299 if (mux->lock)
300 spin_lock_irqsave(mux->lock, flags);
301 else
302 __acquire(mux->lock);
303
304 reg = readl(addr: mux->reg);
305 reg &= ~(mux->mask << mux->shift);
306
307 val = (val | write_en) << mux->shift;
308 reg |= val;
309 writel(val: reg, addr: mux->reg);
310
311 if (mux->lock)
312 spin_unlock_irqrestore(lock: mux->lock, flags);
313 else
314 __release(mux->lock);
315
316 return 0;
317}
318
319static const struct clk_ops m10v_mux_ops = {
320 .get_parent = m10v_mux_get_parent,
321 .set_parent = m10v_mux_set_parent,
322 .determine_rate = __clk_mux_determine_rate,
323};
324
325static struct clk_hw *m10v_clk_hw_register_mux(struct device *dev,
326 const char *name, const char * const *parent_names,
327 u8 num_parents, unsigned long flags, void __iomem *reg,
328 u8 shift, u32 mask, u8 clk_mux_flags, u32 *table,
329 spinlock_t *lock)
330{
331 struct clk_mux *mux;
332 struct clk_hw *hw;
333 struct clk_init_data init;
334 int ret;
335
336 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
337 if (!mux)
338 return ERR_PTR(error: -ENOMEM);
339
340 init.name = name;
341 init.ops = &m10v_mux_ops;
342 init.flags = flags;
343 init.parent_names = parent_names;
344 init.num_parents = num_parents;
345
346 mux->reg = reg;
347 mux->shift = shift;
348 mux->mask = mask;
349 mux->flags = clk_mux_flags;
350 mux->lock = lock;
351 mux->table = table;
352 mux->hw.init = &init;
353
354 hw = &mux->hw;
355 ret = clk_hw_register(dev, hw);
356 if (ret) {
357 kfree(objp: mux);
358 hw = ERR_PTR(error: ret);
359 }
360
361 return hw;
362
363}
364
365struct m10v_clk_divider {
366 struct clk_hw hw;
367 void __iomem *reg;
368 u8 shift;
369 u8 width;
370 u8 flags;
371 const struct clk_div_table *table;
372 spinlock_t *lock;
373 void __iomem *write_valid_reg;
374};
375
376static unsigned long m10v_clk_divider_recalc_rate(struct clk_hw *hw,
377 unsigned long parent_rate)
378{
379 struct m10v_clk_divider *divider = to_m10v_div(hw);
380 unsigned int val;
381
382 val = readl(addr: divider->reg) >> divider->shift;
383 val &= clk_div_mask(divider->width);
384
385 return divider_recalc_rate(hw, parent_rate, val, table: divider->table,
386 flags: divider->flags, width: divider->width);
387}
388
389static int m10v_clk_divider_determine_rate(struct clk_hw *hw,
390 struct clk_rate_request *req)
391{
392 struct m10v_clk_divider *divider = to_m10v_div(hw);
393
394 /* if read only, just return current value */
395 if (divider->flags & CLK_DIVIDER_READ_ONLY) {
396 u32 val;
397
398 val = readl(addr: divider->reg) >> divider->shift;
399 val &= clk_div_mask(divider->width);
400
401 req->rate = divider_ro_round_rate(hw, rate: req->rate,
402 prate: &req->best_parent_rate,
403 table: divider->table,
404 width: divider->width,
405 flags: divider->flags, val);
406
407 return 0;
408 }
409
410 req->rate = divider_round_rate(hw, rate: req->rate, prate: &req->best_parent_rate,
411 table: divider->table, width: divider->width, flags: divider->flags);
412
413 return 0;
414}
415
416static int m10v_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
417 unsigned long parent_rate)
418{
419 struct m10v_clk_divider *divider = to_m10v_div(hw);
420 int value;
421 unsigned long flags = 0;
422 u32 val;
423 u32 write_en = BIT(divider->width - 1);
424
425 value = divider_get_val(rate, parent_rate, table: divider->table,
426 width: divider->width, flags: divider->flags);
427 if (value < 0)
428 return value;
429
430 if (divider->lock)
431 spin_lock_irqsave(divider->lock, flags);
432 else
433 __acquire(divider->lock);
434
435 val = readl(addr: divider->reg);
436 val &= ~(clk_div_mask(divider->width) << divider->shift);
437
438 val |= ((u32)value | write_en) << divider->shift;
439 writel(val, addr: divider->reg);
440
441 if (divider->write_valid_reg) {
442 writel(M10V_DCHREQ, addr: divider->write_valid_reg);
443 if (readl_poll_timeout(divider->write_valid_reg, val,
444 !val, M10V_UPOLL_RATE, M10V_UTIMEOUT))
445 pr_err("%s:%s couldn't stabilize\n",
446 __func__, clk_hw_get_name(hw));
447 }
448
449 if (divider->lock)
450 spin_unlock_irqrestore(lock: divider->lock, flags);
451 else
452 __release(divider->lock);
453
454 return 0;
455}
456
457static const struct clk_ops m10v_clk_divider_ops = {
458 .recalc_rate = m10v_clk_divider_recalc_rate,
459 .determine_rate = m10v_clk_divider_determine_rate,
460 .set_rate = m10v_clk_divider_set_rate,
461};
462
463static struct clk_hw *m10v_clk_hw_register_divider(struct device *dev,
464 const char *name, const char *parent_name, unsigned long flags,
465 void __iomem *reg, u8 shift, u8 width,
466 u8 clk_divider_flags, const struct clk_div_table *table,
467 spinlock_t *lock, void __iomem *write_valid_reg)
468{
469 struct m10v_clk_divider *div;
470 struct clk_hw *hw;
471 struct clk_init_data init;
472 int ret;
473
474 div = kzalloc(sizeof(*div), GFP_KERNEL);
475 if (!div)
476 return ERR_PTR(error: -ENOMEM);
477
478 init.name = name;
479 init.ops = &m10v_clk_divider_ops;
480 init.flags = flags;
481 init.parent_names = &parent_name;
482 init.num_parents = 1;
483
484 div->reg = reg;
485 div->shift = shift;
486 div->width = width;
487 div->flags = clk_divider_flags;
488 div->lock = lock;
489 div->hw.init = &init;
490 div->table = table;
491 div->write_valid_reg = write_valid_reg;
492
493 /* register the clock */
494 hw = &div->hw;
495 ret = clk_hw_register(dev, hw);
496 if (ret) {
497 kfree(objp: div);
498 hw = ERR_PTR(error: ret);
499 }
500
501 return hw;
502}
503
504static void m10v_reg_div_pre(const struct m10v_clk_div_factors *factors,
505 struct clk_hw_onecell_data *clk_data,
506 void __iomem *base)
507{
508 struct clk_hw *hw;
509 void __iomem *write_valid_reg;
510
511 /*
512 * The registers on CLKSEL(9) or CLKSEL(10) need additional
513 * writing to become valid.
514 */
515 if ((factors->offset == CLKSEL(9)) || (factors->offset == CLKSEL(10)))
516 write_valid_reg = base + CLKSEL(11);
517 else
518 write_valid_reg = NULL;
519
520 hw = m10v_clk_hw_register_divider(NULL, name: factors->name,
521 parent_name: factors->parent_name,
522 CLK_SET_RATE_PARENT,
523 reg: base + factors->offset,
524 shift: factors->shift,
525 width: factors->width, clk_divider_flags: factors->div_flags,
526 table: factors->table,
527 lock: &m10v_crglock, write_valid_reg);
528
529 if (factors->onecell_idx >= 0)
530 clk_data->hws[factors->onecell_idx] = hw;
531}
532
533static void m10v_reg_fixed_pre(const struct m10v_clk_div_fixed_data *factors,
534 struct clk_hw_onecell_data *clk_data,
535 const char *parent_name)
536{
537 struct clk_hw *hw;
538 const char *pn = factors->parent_name ?
539 factors->parent_name : parent_name;
540
541 hw = clk_hw_register_fixed_factor(NULL, name: factors->name, parent_name: pn, flags: 0,
542 mult: factors->mult, div: factors->div);
543
544 if (factors->onecell_idx >= 0)
545 clk_data->hws[factors->onecell_idx] = hw;
546}
547
548static void m10v_reg_mux_pre(const struct m10v_clk_mux_factors *factors,
549 struct clk_hw_onecell_data *clk_data,
550 void __iomem *base)
551{
552 struct clk_hw *hw;
553
554 hw = m10v_clk_hw_register_mux(NULL, name: factors->name,
555 parent_names: factors->parent_names,
556 num_parents: factors->num_parents,
557 CLK_SET_RATE_PARENT,
558 reg: base + factors->offset, shift: factors->shift,
559 mask: factors->mask, clk_mux_flags: factors->mux_flags,
560 table: factors->table, lock: &m10v_crglock);
561
562 if (factors->onecell_idx >= 0)
563 clk_data->hws[factors->onecell_idx] = hw;
564}
565
566static int m10v_clk_probe(struct platform_device *pdev)
567{
568 int id;
569 struct device *dev = &pdev->dev;
570 struct device_node *np = dev->of_node;
571 void __iomem *base;
572 const char *parent_name;
573
574 base = devm_platform_get_and_ioremap_resource(pdev, index: 0, NULL);
575 if (IS_ERR(ptr: base))
576 return PTR_ERR(ptr: base);
577
578 parent_name = of_clk_get_parent_name(np, index: 0);
579
580 for (id = 0; id < ARRAY_SIZE(m10v_div_factor_data); ++id)
581 m10v_reg_div_pre(factors: &m10v_div_factor_data[id],
582 clk_data: m10v_clk_data, base);
583
584 for (id = 0; id < ARRAY_SIZE(m10v_div_fixed_data); ++id)
585 m10v_reg_fixed_pre(factors: &m10v_div_fixed_data[id],
586 clk_data: m10v_clk_data, parent_name);
587
588 for (id = 0; id < ARRAY_SIZE(m10v_mux_factor_data); ++id)
589 m10v_reg_mux_pre(factors: &m10v_mux_factor_data[id],
590 clk_data: m10v_clk_data, base);
591
592 for (id = 0; id < M10V_NUM_CLKS; id++) {
593 if (IS_ERR(ptr: m10v_clk_data->hws[id]))
594 return PTR_ERR(ptr: m10v_clk_data->hws[id]);
595 }
596
597 return 0;
598}
599
600static const struct of_device_id m10v_clk_dt_ids[] = {
601 { .compatible = "socionext,milbeaut-m10v-ccu", },
602 { }
603};
604
605static struct platform_driver m10v_clk_driver = {
606 .probe = m10v_clk_probe,
607 .driver = {
608 .name = "m10v-ccu",
609 .of_match_table = m10v_clk_dt_ids,
610 },
611};
612builtin_platform_driver(m10v_clk_driver);
613
614static void __init m10v_cc_init(struct device_node *np)
615{
616 int id;
617 void __iomem *base;
618 const char *parent_name;
619 struct clk_hw *hw;
620
621 m10v_clk_data = kzalloc(struct_size(m10v_clk_data, hws,
622 M10V_NUM_CLKS),
623 GFP_KERNEL);
624
625 if (!m10v_clk_data)
626 return;
627 m10v_clk_data->num = M10V_NUM_CLKS;
628
629 base = of_iomap(node: np, index: 0);
630 if (!base) {
631 kfree(objp: m10v_clk_data);
632 return;
633 }
634
635 parent_name = of_clk_get_parent_name(np, index: 0);
636 if (!parent_name) {
637 kfree(objp: m10v_clk_data);
638 iounmap(addr: base);
639 return;
640 }
641
642 /*
643 * This way all clocks fetched before the platform device probes,
644 * except those we assign here for early use, will be deferred.
645 */
646 for (id = 0; id < M10V_NUM_CLKS; id++)
647 m10v_clk_data->hws[id] = ERR_PTR(error: -EPROBE_DEFER);
648
649 /*
650 * PLLs are set by bootloader so this driver registers them as the
651 * fixed factor.
652 */
653 for (id = 0; id < ARRAY_SIZE(m10v_pll_fixed_data); ++id)
654 m10v_reg_fixed_pre(factors: &m10v_pll_fixed_data[id],
655 clk_data: m10v_clk_data, parent_name);
656
657 /*
658 * timer consumes "rclk" so it needs to register here.
659 */
660 hw = m10v_clk_hw_register_divider(NULL, name: "rclk", M10V_PLL10DIV2, flags: 0,
661 reg: base + CLKSEL(1), shift: 0, width: 3, clk_divider_flags: 0, table: rclk_table,
662 lock: &m10v_crglock, NULL);
663 m10v_clk_data->hws[M10V_RCLK_ID] = hw;
664 of_clk_add_hw_provider(np, get: of_clk_hw_onecell_get, data: m10v_clk_data);
665}
666CLK_OF_DECLARE_DRIVER(m10v_cc, "socionext,milbeaut-m10v-ccu", m10v_cc_init);
667

source code of linux/drivers/clk/clk-milbeaut.c