1// SPDX-License-Identifier: GPL-2.0
2
3#include <linux/module.h>
4#include <linux/kernel.h>
5#include <linux/clk.h>
6#include <linux/clk-provider.h>
7#include <linux/err.h>
8#include <linux/errno.h>
9#include <linux/gpio/consumer.h>
10#include <linux/i2c.h>
11#include <linux/regulator/consumer.h>
12
13#include <dt-bindings/clock/maxim,max9485.h>
14
15#define MAX9485_NUM_CLKS 4
16
17/* This chip has only one register of 8 bit width. */
18
19#define MAX9485_FS_12KHZ (0 << 0)
20#define MAX9485_FS_32KHZ (1 << 0)
21#define MAX9485_FS_44_1KHZ (2 << 0)
22#define MAX9485_FS_48KHZ (3 << 0)
23
24#define MAX9485_SCALE_256 (0 << 2)
25#define MAX9485_SCALE_384 (1 << 2)
26#define MAX9485_SCALE_768 (2 << 2)
27
28#define MAX9485_DOUBLE BIT(4)
29#define MAX9485_CLKOUT1_ENABLE BIT(5)
30#define MAX9485_CLKOUT2_ENABLE BIT(6)
31#define MAX9485_MCLK_ENABLE BIT(7)
32#define MAX9485_FREQ_MASK 0x1f
33
34struct max9485_rate {
35 unsigned long out;
36 u8 reg_value;
37};
38
39/*
40 * Ordered by frequency. For frequency the hardware can generate with
41 * multiple settings, the one with lowest jitter is listed first.
42 */
43static const struct max9485_rate max9485_rates[] = {
44 { 3072000, MAX9485_FS_12KHZ | MAX9485_SCALE_256 },
45 { 4608000, MAX9485_FS_12KHZ | MAX9485_SCALE_384 },
46 { 8192000, MAX9485_FS_32KHZ | MAX9485_SCALE_256 },
47 { 9126000, MAX9485_FS_12KHZ | MAX9485_SCALE_768 },
48 { 11289600, MAX9485_FS_44_1KHZ | MAX9485_SCALE_256 },
49 { 12288000, MAX9485_FS_48KHZ | MAX9485_SCALE_256 },
50 { 12288000, MAX9485_FS_32KHZ | MAX9485_SCALE_384 },
51 { 16384000, MAX9485_FS_32KHZ | MAX9485_SCALE_256 | MAX9485_DOUBLE },
52 { 16934400, MAX9485_FS_44_1KHZ | MAX9485_SCALE_384 },
53 { 18384000, MAX9485_FS_48KHZ | MAX9485_SCALE_384 },
54 { 22579200, MAX9485_FS_44_1KHZ | MAX9485_SCALE_256 | MAX9485_DOUBLE },
55 { 24576000, MAX9485_FS_48KHZ | MAX9485_SCALE_256 | MAX9485_DOUBLE },
56 { 24576000, MAX9485_FS_32KHZ | MAX9485_SCALE_384 | MAX9485_DOUBLE },
57 { 24576000, MAX9485_FS_32KHZ | MAX9485_SCALE_768 },
58 { 33868800, MAX9485_FS_44_1KHZ | MAX9485_SCALE_384 | MAX9485_DOUBLE },
59 { 33868800, MAX9485_FS_44_1KHZ | MAX9485_SCALE_768 },
60 { 36864000, MAX9485_FS_48KHZ | MAX9485_SCALE_384 | MAX9485_DOUBLE },
61 { 36864000, MAX9485_FS_48KHZ | MAX9485_SCALE_768 },
62 { 49152000, MAX9485_FS_32KHZ | MAX9485_SCALE_768 | MAX9485_DOUBLE },
63 { 67737600, MAX9485_FS_44_1KHZ | MAX9485_SCALE_768 | MAX9485_DOUBLE },
64 { 73728000, MAX9485_FS_48KHZ | MAX9485_SCALE_768 | MAX9485_DOUBLE },
65 { } /* sentinel */
66};
67
68struct max9485_driver_data;
69
70struct max9485_clk_hw {
71 struct clk_hw hw;
72 struct clk_init_data init;
73 u8 enable_bit;
74 struct max9485_driver_data *drvdata;
75};
76
77struct max9485_driver_data {
78 struct clk *xclk;
79 struct i2c_client *client;
80 u8 reg_value;
81 struct regulator *supply;
82 struct gpio_desc *reset_gpio;
83 struct max9485_clk_hw hw[MAX9485_NUM_CLKS];
84};
85
86static inline struct max9485_clk_hw *to_max9485_clk(struct clk_hw *hw)
87{
88 return container_of(hw, struct max9485_clk_hw, hw);
89}
90
91static int max9485_update_bits(struct max9485_driver_data *drvdata,
92 u8 mask, u8 value)
93{
94 int ret;
95
96 drvdata->reg_value &= ~mask;
97 drvdata->reg_value |= value;
98
99 dev_dbg(&drvdata->client->dev,
100 "updating mask 0x%02x value 0x%02x -> 0x%02x\n",
101 mask, value, drvdata->reg_value);
102
103 ret = i2c_master_send(client: drvdata->client,
104 buf: &drvdata->reg_value,
105 count: sizeof(drvdata->reg_value));
106
107 return ret < 0 ? ret : 0;
108}
109
110static int max9485_clk_prepare(struct clk_hw *hw)
111{
112 struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);
113
114 return max9485_update_bits(drvdata: clk_hw->drvdata,
115 mask: clk_hw->enable_bit,
116 value: clk_hw->enable_bit);
117}
118
119static void max9485_clk_unprepare(struct clk_hw *hw)
120{
121 struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);
122
123 max9485_update_bits(drvdata: clk_hw->drvdata, mask: clk_hw->enable_bit, value: 0);
124}
125
126/*
127 * CLKOUT - configurable clock output
128 */
129static int max9485_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
130 unsigned long parent_rate)
131{
132 struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);
133 const struct max9485_rate *entry;
134
135 for (entry = max9485_rates; entry->out != 0; entry++)
136 if (entry->out == rate)
137 break;
138
139 if (entry->out == 0)
140 return -EINVAL;
141
142 return max9485_update_bits(drvdata: clk_hw->drvdata,
143 MAX9485_FREQ_MASK,
144 value: entry->reg_value);
145}
146
147static unsigned long max9485_clkout_recalc_rate(struct clk_hw *hw,
148 unsigned long parent_rate)
149{
150 struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);
151 struct max9485_driver_data *drvdata = clk_hw->drvdata;
152 u8 val = drvdata->reg_value & MAX9485_FREQ_MASK;
153 const struct max9485_rate *entry;
154
155 for (entry = max9485_rates; entry->out != 0; entry++)
156 if (val == entry->reg_value)
157 return entry->out;
158
159 return 0;
160}
161
162static int max9485_clkout_determine_rate(struct clk_hw *hw,
163 struct clk_rate_request *req)
164{
165 const struct max9485_rate *curr, *prev = NULL;
166
167 for (curr = max9485_rates; curr->out != 0; curr++) {
168 /* Exact matches */
169 if (curr->out == req->rate)
170 return 0;
171
172 /*
173 * Find the first entry that has a frequency higher than the
174 * requested one.
175 */
176 if (curr->out > req->rate) {
177 unsigned int mid;
178
179 /*
180 * If this is the first entry, clamp the value to the
181 * lowest possible frequency.
182 */
183 if (!prev) {
184 req->rate = curr->out;
185
186 return 0;
187 }
188
189 /*
190 * Otherwise, determine whether the previous entry or
191 * current one is closer.
192 */
193 mid = prev->out + ((curr->out - prev->out) / 2);
194
195 req->rate = mid > req->rate ? prev->out : curr->out;
196
197 return 0;
198 }
199
200 prev = curr;
201 }
202
203 /* If the last entry was still too high, clamp the value */
204 req->rate = prev->out;
205
206 return 0;
207}
208
209struct max9485_clk {
210 const char *name;
211 int parent_index;
212 const struct clk_ops ops;
213 u8 enable_bit;
214};
215
216static const struct max9485_clk max9485_clks[MAX9485_NUM_CLKS] = {
217 [MAX9485_MCLKOUT] = {
218 .name = "mclkout",
219 .parent_index = -1,
220 .enable_bit = MAX9485_MCLK_ENABLE,
221 .ops = {
222 .prepare = max9485_clk_prepare,
223 .unprepare = max9485_clk_unprepare,
224 },
225 },
226 [MAX9485_CLKOUT] = {
227 .name = "clkout",
228 .parent_index = -1,
229 .ops = {
230 .set_rate = max9485_clkout_set_rate,
231 .determine_rate = max9485_clkout_determine_rate,
232 .recalc_rate = max9485_clkout_recalc_rate,
233 },
234 },
235 [MAX9485_CLKOUT1] = {
236 .name = "clkout1",
237 .parent_index = MAX9485_CLKOUT,
238 .enable_bit = MAX9485_CLKOUT1_ENABLE,
239 .ops = {
240 .prepare = max9485_clk_prepare,
241 .unprepare = max9485_clk_unprepare,
242 },
243 },
244 [MAX9485_CLKOUT2] = {
245 .name = "clkout2",
246 .parent_index = MAX9485_CLKOUT,
247 .enable_bit = MAX9485_CLKOUT2_ENABLE,
248 .ops = {
249 .prepare = max9485_clk_prepare,
250 .unprepare = max9485_clk_unprepare,
251 },
252 },
253};
254
255static struct clk_hw *
256max9485_of_clk_get(struct of_phandle_args *clkspec, void *data)
257{
258 struct max9485_driver_data *drvdata = data;
259 unsigned int idx = clkspec->args[0];
260
261 return &drvdata->hw[idx].hw;
262}
263
264static int max9485_i2c_probe(struct i2c_client *client)
265{
266 struct max9485_driver_data *drvdata;
267 struct device *dev = &client->dev;
268 const char *xclk_name;
269 int i, ret;
270
271 drvdata = devm_kzalloc(dev, size: sizeof(*drvdata), GFP_KERNEL);
272 if (!drvdata)
273 return -ENOMEM;
274
275 drvdata->xclk = devm_clk_get(dev, id: "xclk");
276 if (IS_ERR(ptr: drvdata->xclk))
277 return PTR_ERR(ptr: drvdata->xclk);
278
279 xclk_name = __clk_get_name(clk: drvdata->xclk);
280
281 drvdata->supply = devm_regulator_get(dev, id: "vdd");
282 if (IS_ERR(ptr: drvdata->supply))
283 return PTR_ERR(ptr: drvdata->supply);
284
285 ret = regulator_enable(regulator: drvdata->supply);
286 if (ret < 0)
287 return ret;
288
289 drvdata->reset_gpio =
290 devm_gpiod_get_optional(dev, con_id: "reset", flags: GPIOD_OUT_HIGH);
291 if (IS_ERR(ptr: drvdata->reset_gpio))
292 return PTR_ERR(ptr: drvdata->reset_gpio);
293
294 i2c_set_clientdata(client, data: drvdata);
295 drvdata->client = client;
296
297 ret = i2c_master_recv(client: drvdata->client, buf: &drvdata->reg_value,
298 count: sizeof(drvdata->reg_value));
299 if (ret < 0) {
300 dev_warn(dev, "Unable to read device register: %d\n", ret);
301 return ret;
302 }
303
304 for (i = 0; i < MAX9485_NUM_CLKS; i++) {
305 int parent_index = max9485_clks[i].parent_index;
306 const char *name;
307
308 if (of_property_read_string_index(np: dev->of_node,
309 propname: "clock-output-names",
310 index: i, output: &name) == 0) {
311 drvdata->hw[i].init.name = name;
312 } else {
313 drvdata->hw[i].init.name = max9485_clks[i].name;
314 }
315
316 drvdata->hw[i].init.ops = &max9485_clks[i].ops;
317 drvdata->hw[i].init.num_parents = 1;
318 drvdata->hw[i].init.flags = 0;
319
320 if (parent_index > 0) {
321 drvdata->hw[i].init.parent_names =
322 &drvdata->hw[parent_index].init.name;
323 drvdata->hw[i].init.flags |= CLK_SET_RATE_PARENT;
324 } else {
325 drvdata->hw[i].init.parent_names = &xclk_name;
326 }
327
328 drvdata->hw[i].enable_bit = max9485_clks[i].enable_bit;
329 drvdata->hw[i].hw.init = &drvdata->hw[i].init;
330 drvdata->hw[i].drvdata = drvdata;
331
332 ret = devm_clk_hw_register(dev, hw: &drvdata->hw[i].hw);
333 if (ret < 0)
334 return ret;
335 }
336
337 return devm_of_clk_add_hw_provider(dev, get: max9485_of_clk_get, data: drvdata);
338}
339
340static int __maybe_unused max9485_suspend(struct device *dev)
341{
342 struct i2c_client *client = to_i2c_client(dev);
343 struct max9485_driver_data *drvdata = i2c_get_clientdata(client);
344
345 gpiod_set_value_cansleep(desc: drvdata->reset_gpio, value: 0);
346
347 return 0;
348}
349
350static int __maybe_unused max9485_resume(struct device *dev)
351{
352 struct i2c_client *client = to_i2c_client(dev);
353 struct max9485_driver_data *drvdata = i2c_get_clientdata(client);
354 int ret;
355
356 gpiod_set_value_cansleep(desc: drvdata->reset_gpio, value: 1);
357
358 ret = i2c_master_send(client, buf: &drvdata->reg_value,
359 count: sizeof(drvdata->reg_value));
360
361 return ret < 0 ? ret : 0;
362}
363
364static const struct dev_pm_ops max9485_pm_ops = {
365 SET_SYSTEM_SLEEP_PM_OPS(max9485_suspend, max9485_resume)
366};
367
368static const struct of_device_id max9485_dt_ids[] = {
369 { .compatible = "maxim,max9485", },
370 { }
371};
372MODULE_DEVICE_TABLE(of, max9485_dt_ids);
373
374static const struct i2c_device_id max9485_i2c_ids[] = {
375 { .name = "max9485", },
376 { }
377};
378MODULE_DEVICE_TABLE(i2c, max9485_i2c_ids);
379
380static struct i2c_driver max9485_driver = {
381 .driver = {
382 .name = "max9485",
383 .pm = &max9485_pm_ops,
384 .of_match_table = max9485_dt_ids,
385 },
386 .probe = max9485_i2c_probe,
387 .id_table = max9485_i2c_ids,
388};
389module_i2c_driver(max9485_driver);
390
391MODULE_AUTHOR("Daniel Mack <daniel@zonque.org>");
392MODULE_DESCRIPTION("MAX9485 Programmable Audio Clock Generator");
393MODULE_LICENSE("GPL v2");
394

source code of linux/drivers/clk/clk-max9485.c