| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | #ifndef _ASM_X86_MICROCODE_H |
| 3 | #define _ASM_X86_MICROCODE_H |
| 4 | |
| 5 | #include <asm/msr.h> |
| 6 | |
| 7 | struct cpu_signature { |
| 8 | unsigned int sig; |
| 9 | unsigned int pf; |
| 10 | unsigned int rev; |
| 11 | }; |
| 12 | |
| 13 | struct ucode_cpu_info { |
| 14 | struct cpu_signature cpu_sig; |
| 15 | void *mc; |
| 16 | }; |
| 17 | |
| 18 | #ifdef CONFIG_MICROCODE |
| 19 | void load_ucode_bsp(void); |
| 20 | void load_ucode_ap(void); |
| 21 | void microcode_bsp_resume(void); |
| 22 | bool __init microcode_loader_disabled(void); |
| 23 | #else |
| 24 | static inline void load_ucode_bsp(void) { } |
| 25 | static inline void load_ucode_ap(void) { } |
| 26 | static inline void microcode_bsp_resume(void) { } |
| 27 | static inline bool __init microcode_loader_disabled(void) { return false; } |
| 28 | #endif |
| 29 | |
| 30 | extern unsigned long initrd_start_early; |
| 31 | |
| 32 | #ifdef CONFIG_CPU_SUP_INTEL |
| 33 | /* Intel specific microcode defines. Public for IFS */ |
| 34 | struct { |
| 35 | unsigned int ; |
| 36 | unsigned int ; |
| 37 | unsigned int ; |
| 38 | unsigned int ; |
| 39 | unsigned int ; |
| 40 | unsigned int ; |
| 41 | unsigned int ; |
| 42 | unsigned int ; |
| 43 | unsigned int ; |
| 44 | unsigned int ; |
| 45 | unsigned int ; |
| 46 | unsigned int ; |
| 47 | }; |
| 48 | |
| 49 | struct microcode_intel { |
| 50 | struct microcode_header_intel hdr; |
| 51 | unsigned int bits[]; |
| 52 | }; |
| 53 | |
| 54 | #define DEFAULT_UCODE_DATASIZE (2000) |
| 55 | #define (sizeof(struct microcode_header_intel)) |
| 56 | #define 1 |
| 57 | #define 2 |
| 58 | |
| 59 | static inline int intel_microcode_get_datasize(struct microcode_header_intel *hdr) |
| 60 | { |
| 61 | return hdr->datasize ? : DEFAULT_UCODE_DATASIZE; |
| 62 | } |
| 63 | |
| 64 | static inline u32 intel_get_microcode_revision(void) |
| 65 | { |
| 66 | u32 rev, dummy; |
| 67 | |
| 68 | native_wrmsrq(MSR_IA32_UCODE_REV, 0); |
| 69 | |
| 70 | /* As documented in the SDM: Do a CPUID 1 here */ |
| 71 | native_cpuid_eax(op: 1); |
| 72 | |
| 73 | /* get the current revision from MSR 0x8B */ |
| 74 | native_rdmsr(MSR_IA32_UCODE_REV, dummy, rev); |
| 75 | |
| 76 | return rev; |
| 77 | } |
| 78 | #endif /* !CONFIG_CPU_SUP_INTEL */ |
| 79 | |
| 80 | bool microcode_nmi_handler(void); |
| 81 | void microcode_offline_nmi_handler(void); |
| 82 | |
| 83 | #ifdef CONFIG_MICROCODE_LATE_LOADING |
| 84 | DECLARE_STATIC_KEY_FALSE(microcode_nmi_handler_enable); |
| 85 | static __always_inline bool microcode_nmi_handler_enabled(void) |
| 86 | { |
| 87 | return static_branch_unlikely(µcode_nmi_handler_enable); |
| 88 | } |
| 89 | #else |
| 90 | static __always_inline bool microcode_nmi_handler_enabled(void) { return false; } |
| 91 | #endif |
| 92 | |
| 93 | #endif /* _ASM_X86_MICROCODE_H */ |
| 94 | |