1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_X86_AMD_NB_H
3#define _ASM_X86_AMD_NB_H
4
5#include <linux/ioport.h>
6#include <linux/pci.h>
7#include <asm/amd/node.h>
8
9struct amd_nb_bus_dev_range {
10 u8 bus;
11 u8 dev_base;
12 u8 dev_limit;
13};
14
15extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];
16
17extern bool early_is_amd_nb(u32 value);
18extern struct resource *amd_get_mmconfig_range(struct resource *res);
19extern void amd_flush_garts(void);
20extern int amd_numa_init(void);
21extern int amd_get_subcaches(int);
22extern int amd_set_subcaches(int, unsigned long);
23
24struct amd_l3_cache {
25 unsigned indices;
26 u8 subcaches[4];
27};
28
29struct amd_northbridge {
30 struct pci_dev *misc;
31 struct pci_dev *link;
32 struct amd_l3_cache l3_cache;
33};
34
35struct amd_northbridge_info {
36 u16 num;
37 u64 flags;
38 struct amd_northbridge *nb;
39};
40
41#define AMD_NB_GART BIT(0)
42#define AMD_NB_L3_INDEX_DISABLE BIT(1)
43#define AMD_NB_L3_PARTITIONING BIT(2)
44
45#ifdef CONFIG_AMD_NB
46
47u16 amd_nb_num(void);
48bool amd_nb_has_feature(unsigned int feature);
49struct amd_northbridge *node_to_amd_nb(int node);
50
51static inline bool amd_gart_present(void)
52{
53 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
54 return false;
55
56 /* GART present only on Fam15h, up to model 0fh */
57 if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 ||
58 (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model < 0x10))
59 return true;
60
61 return false;
62}
63
64#else
65
66#define amd_nb_num(x) 0
67#define amd_nb_has_feature(x) false
68static inline struct amd_northbridge *node_to_amd_nb(int node)
69{
70 return NULL;
71}
72#define amd_gart_present(x) false
73
74#endif
75
76
77#endif /* _ASM_X86_AMD_NB_H */
78

source code of linux/arch/x86/include/asm/amd/nb.h