1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright IBM Corp. 2004, 2011
4 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
5 * Holger Smolinski <Holger.Smolinski@de.ibm.com>,
6 * Thomas Spatzier <tspat@de.ibm.com>,
7 *
8 * This file contains interrupt related functions.
9 */
10
11#include <linux/kernel_stat.h>
12#include <linux/cpufeature.h>
13#include <linux/interrupt.h>
14#include <linux/seq_file.h>
15#include <linux/proc_fs.h>
16#include <linux/profile.h>
17#include <linux/export.h>
18#include <linux/kernel.h>
19#include <linux/ftrace.h>
20#include <linux/errno.h>
21#include <linux/slab.h>
22#include <linux/init.h>
23#include <linux/cpu.h>
24#include <linux/irq.h>
25#include <linux/entry-common.h>
26#include <asm/irq_regs.h>
27#include <asm/cputime.h>
28#include <asm/lowcore.h>
29#include <asm/machine.h>
30#include <asm/irq.h>
31#include <asm/hw_irq.h>
32#include <asm/stacktrace.h>
33#include <asm/softirq_stack.h>
34#include <asm/vtime.h>
35#include <asm/asm.h>
36#include "entry.h"
37
38DEFINE_PER_CPU_SHARED_ALIGNED(struct irq_stat, irq_stat);
39EXPORT_PER_CPU_SYMBOL_GPL(irq_stat);
40
41struct irq_class {
42 int irq;
43 char *name;
44 char *desc;
45};
46
47/*
48 * The list of "main" irq classes on s390. This is the list of interrupts
49 * that appear both in /proc/stat ("intr" line) and /proc/interrupts.
50 * Historically only external and I/O interrupts have been part of /proc/stat.
51 * We can't add the split external and I/O sub classes since the first field
52 * in the "intr" line in /proc/stat is supposed to be the sum of all other
53 * fields.
54 * Since the external and I/O interrupt fields are already sums we would end
55 * up with having a sum which accounts each interrupt twice.
56 */
57static const struct irq_class irqclass_main_desc[NR_IRQS_BASE] = {
58 {.irq = EXT_INTERRUPT, .name = "EXT"},
59 {.irq = IO_INTERRUPT, .name = "I/O"},
60 {.irq = THIN_INTERRUPT, .name = "AIO"},
61};
62
63/*
64 * The list of split external and I/O interrupts that appear only in
65 * /proc/interrupts.
66 * In addition this list contains non external / I/O events like NMIs.
67 */
68static const struct irq_class irqclass_sub_desc[] = {
69 {.irq = IRQEXT_CLK, .name = "CLK", .desc = "[EXT] Clock Comparator"},
70 {.irq = IRQEXT_EXC, .name = "EXC", .desc = "[EXT] External Call"},
71 {.irq = IRQEXT_EMS, .name = "EMS", .desc = "[EXT] Emergency Signal"},
72 {.irq = IRQEXT_TMR, .name = "TMR", .desc = "[EXT] CPU Timer"},
73 {.irq = IRQEXT_TLA, .name = "TAL", .desc = "[EXT] Timing Alert"},
74 {.irq = IRQEXT_PFL, .name = "PFL", .desc = "[EXT] Pseudo Page Fault"},
75 {.irq = IRQEXT_DSD, .name = "DSD", .desc = "[EXT] DASD Diag"},
76 {.irq = IRQEXT_VRT, .name = "VRT", .desc = "[EXT] Virtio"},
77 {.irq = IRQEXT_SCP, .name = "SCP", .desc = "[EXT] Service Call"},
78 {.irq = IRQEXT_IUC, .name = "IUC", .desc = "[EXT] IUCV"},
79 {.irq = IRQEXT_CMS, .name = "CMS", .desc = "[EXT] CPU-Measurement: Sampling"},
80 {.irq = IRQEXT_CMC, .name = "CMC", .desc = "[EXT] CPU-Measurement: Counter"},
81 {.irq = IRQEXT_FTP, .name = "FTP", .desc = "[EXT] HMC FTP Service"},
82 {.irq = IRQEXT_WTI, .name = "WTI", .desc = "[EXT] Warning Track"},
83 {.irq = IRQIO_CIO, .name = "CIO", .desc = "[I/O] Common I/O Layer Interrupt"},
84 {.irq = IRQIO_DAS, .name = "DAS", .desc = "[I/O] DASD"},
85 {.irq = IRQIO_C15, .name = "C15", .desc = "[I/O] 3215"},
86 {.irq = IRQIO_C70, .name = "C70", .desc = "[I/O] 3270"},
87 {.irq = IRQIO_TAP, .name = "TAP", .desc = "[I/O] Tape"},
88 {.irq = IRQIO_VMR, .name = "VMR", .desc = "[I/O] Unit Record Devices"},
89 {.irq = IRQIO_CTC, .name = "CTC", .desc = "[I/O] CTC"},
90 {.irq = IRQIO_ADM, .name = "ADM", .desc = "[I/O] EADM Subchannel"},
91 {.irq = IRQIO_CSC, .name = "CSC", .desc = "[I/O] CHSC Subchannel"},
92 {.irq = IRQIO_VIR, .name = "VIR", .desc = "[I/O] Virtual I/O Devices"},
93 {.irq = IRQIO_QAI, .name = "QAI", .desc = "[AIO] QDIO Adapter Interrupt"},
94 {.irq = IRQIO_APB, .name = "APB", .desc = "[AIO] AP Bus"},
95 {.irq = IRQIO_PCF, .name = "PCF", .desc = "[AIO] PCI Floating Interrupt"},
96 {.irq = IRQIO_PCD, .name = "PCD", .desc = "[AIO] PCI Directed Interrupt"},
97 {.irq = IRQIO_MSI, .name = "MSI", .desc = "[AIO] MSI Interrupt"},
98 {.irq = IRQIO_VAI, .name = "VAI", .desc = "[AIO] Virtual I/O Devices AI"},
99 {.irq = IRQIO_GAL, .name = "GAL", .desc = "[AIO] GIB Alert"},
100 {.irq = NMI_NMI, .name = "NMI", .desc = "[NMI] Machine Check"},
101 {.irq = CPU_RST, .name = "RST", .desc = "[CPU] CPU Restart"},
102};
103
104static void do_IRQ(struct pt_regs *regs, int irq)
105{
106 if (tod_after_eq(get_lowcore()->int_clock,
107 get_lowcore()->clock_comparator))
108 /* Serve timer interrupts first. */
109 clock_comparator_work();
110 generic_handle_irq(irq);
111}
112
113static int on_async_stack(void)
114{
115 unsigned long frame = current_frame_address();
116
117 return ((get_lowcore()->async_stack ^ frame) & ~(THREAD_SIZE - 1)) == 0;
118}
119
120static void do_irq_async(struct pt_regs *regs, int irq)
121{
122 if (on_async_stack()) {
123 do_IRQ(regs, irq);
124 } else {
125 call_on_stack(2, get_lowcore()->async_stack, void, do_IRQ,
126 struct pt_regs *, regs, int, irq);
127 }
128}
129
130static int irq_pending(struct pt_regs *regs)
131{
132 int cc;
133
134 asm volatile(
135 " tpi 0\n"
136 CC_IPM(cc)
137 : CC_OUT(cc, cc)
138 :
139 : CC_CLOBBER);
140 return CC_TRANSFORM(cc);
141}
142
143void noinstr do_io_irq(struct pt_regs *regs)
144{
145 irqentry_state_t state = irqentry_enter(regs);
146 struct pt_regs *old_regs = set_irq_regs(regs);
147 bool from_idle;
148
149 irq_enter_rcu();
150
151 if (user_mode(regs)) {
152 update_timer_sys();
153 if (cpu_has_bear())
154 current->thread.last_break = regs->last_break;
155 }
156
157 from_idle = test_and_clear_cpu_flag(CIF_ENABLED_WAIT);
158 if (from_idle)
159 account_idle_time_irq();
160
161 set_cpu_flag(CIF_NOHZ_DELAY);
162 do {
163 regs->tpi_info = get_lowcore()->tpi_info;
164 if (get_lowcore()->tpi_info.adapter_IO)
165 do_irq_async(regs, THIN_INTERRUPT);
166 else
167 do_irq_async(regs, IO_INTERRUPT);
168 } while (machine_is_lpar() && irq_pending(regs));
169
170 irq_exit_rcu();
171
172 set_irq_regs(old_regs);
173 irqentry_exit(regs, state);
174
175 if (from_idle)
176 regs->psw.mask &= ~(PSW_MASK_EXT | PSW_MASK_IO | PSW_MASK_WAIT);
177}
178
179void noinstr do_ext_irq(struct pt_regs *regs)
180{
181 irqentry_state_t state = irqentry_enter(regs);
182 struct pt_regs *old_regs = set_irq_regs(regs);
183 bool from_idle;
184
185 irq_enter_rcu();
186
187 if (user_mode(regs)) {
188 update_timer_sys();
189 if (cpu_has_bear())
190 current->thread.last_break = regs->last_break;
191 }
192
193 regs->int_code = get_lowcore()->ext_int_code_addr;
194 regs->int_parm = get_lowcore()->ext_params;
195 regs->int_parm_long = get_lowcore()->ext_params2;
196
197 from_idle = test_and_clear_cpu_flag(CIF_ENABLED_WAIT);
198 if (from_idle)
199 account_idle_time_irq();
200
201 do_irq_async(regs, EXT_INTERRUPT);
202
203 irq_exit_rcu();
204 set_irq_regs(old_regs);
205 irqentry_exit(regs, state);
206
207 if (from_idle)
208 regs->psw.mask &= ~(PSW_MASK_EXT | PSW_MASK_IO | PSW_MASK_WAIT);
209}
210
211static void show_msi_interrupt(struct seq_file *p, int irq)
212{
213 struct irq_desc *desc;
214 unsigned long flags;
215 int cpu;
216
217 rcu_read_lock();
218 desc = irq_to_desc(irq);
219 if (!desc)
220 goto out;
221
222 raw_spin_lock_irqsave(&desc->lock, flags);
223 seq_printf(m: p, fmt: "%3d: ", irq);
224 for_each_online_cpu(cpu)
225 seq_printf(m: p, fmt: "%10u ", irq_desc_kstat_cpu(desc, cpu));
226
227 if (desc->irq_data.chip)
228 seq_printf(m: p, fmt: " %8s", desc->irq_data.chip->name);
229
230 if (desc->action)
231 seq_printf(m: p, fmt: " %s", desc->action->name);
232
233 seq_putc(m: p, c: '\n');
234 raw_spin_unlock_irqrestore(&desc->lock, flags);
235out:
236 rcu_read_unlock();
237}
238
239/*
240 * show_interrupts is needed by /proc/interrupts.
241 */
242int show_interrupts(struct seq_file *p, void *v)
243{
244 int index = *(loff_t *) v;
245 int cpu, irq;
246
247 cpus_read_lock();
248 if (index == 0) {
249 seq_puts(m: p, s: " ");
250 for_each_online_cpu(cpu)
251 seq_printf(m: p, fmt: "CPU%-8d", cpu);
252 seq_putc(m: p, c: '\n');
253 }
254 if (index < NR_IRQS_BASE) {
255 seq_printf(m: p, fmt: "%s: ", irqclass_main_desc[index].name);
256 irq = irqclass_main_desc[index].irq;
257 for_each_online_cpu(cpu)
258 seq_printf(m: p, fmt: "%10u ", kstat_irqs_cpu(irq, cpu));
259 seq_putc(m: p, c: '\n');
260 goto out;
261 }
262 if (index < irq_get_nr_irqs()) {
263 show_msi_interrupt(p, irq: index);
264 goto out;
265 }
266 for (index = 0; index < NR_ARCH_IRQS; index++) {
267 seq_printf(p, "%s: ", irqclass_sub_desc[index].name);
268 irq = irqclass_sub_desc[index].irq;
269 for_each_online_cpu(cpu)
270 seq_printf(p, "%10u ",
271 per_cpu(irq_stat, cpu).irqs[irq]);
272 if (irqclass_sub_desc[index].desc)
273 seq_printf(p, " %s", irqclass_sub_desc[index].desc);
274 seq_putc(p, '\n');
275 }
276out:
277 cpus_read_unlock();
278 return 0;
279}
280
281unsigned int arch_dynirq_lower_bound(unsigned int from)
282{
283 return from < NR_IRQS_BASE ? NR_IRQS_BASE : from;
284}
285
286/*
287 * ext_int_hash[index] is the list head for all external interrupts that hash
288 * to this index.
289 */
290static struct hlist_head ext_int_hash[32] ____cacheline_aligned;
291
292struct ext_int_info {
293 ext_int_handler_t handler;
294 struct hlist_node entry;
295 struct rcu_head rcu;
296 u16 code;
297};
298
299/* ext_int_hash_lock protects the handler lists for external interrupts */
300static DEFINE_SPINLOCK(ext_int_hash_lock);
301
302static inline int ext_hash(u16 code)
303{
304 BUILD_BUG_ON(!is_power_of_2(ARRAY_SIZE(ext_int_hash)));
305
306 return (code + (code >> 9)) & (ARRAY_SIZE(ext_int_hash) - 1);
307}
308
309int register_external_irq(u16 code, ext_int_handler_t handler)
310{
311 struct ext_int_info *p;
312 unsigned long flags;
313 int index;
314
315 p = kmalloc(sizeof(*p), GFP_ATOMIC);
316 if (!p)
317 return -ENOMEM;
318 p->code = code;
319 p->handler = handler;
320 index = ext_hash(code);
321
322 spin_lock_irqsave(&ext_int_hash_lock, flags);
323 hlist_add_head_rcu(n: &p->entry, h: &ext_int_hash[index]);
324 spin_unlock_irqrestore(lock: &ext_int_hash_lock, flags);
325 return 0;
326}
327EXPORT_SYMBOL(register_external_irq);
328
329int unregister_external_irq(u16 code, ext_int_handler_t handler)
330{
331 struct ext_int_info *p;
332 unsigned long flags;
333 int index = ext_hash(code);
334
335 spin_lock_irqsave(&ext_int_hash_lock, flags);
336 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
337 if (p->code == code && p->handler == handler) {
338 hlist_del_rcu(n: &p->entry);
339 kfree_rcu(p, rcu);
340 }
341 }
342 spin_unlock_irqrestore(lock: &ext_int_hash_lock, flags);
343 return 0;
344}
345EXPORT_SYMBOL(unregister_external_irq);
346
347static irqreturn_t do_ext_interrupt(int irq, void *dummy)
348{
349 struct pt_regs *regs = get_irq_regs();
350 struct ext_code ext_code;
351 struct ext_int_info *p;
352 int index;
353
354 ext_code.int_code = regs->int_code;
355 if (ext_code.code != EXT_IRQ_CLK_COMP)
356 set_cpu_flag(CIF_NOHZ_DELAY);
357
358 index = ext_hash(code: ext_code.code);
359 rcu_read_lock();
360 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
361 if (unlikely(p->code != ext_code.code))
362 continue;
363 p->handler(ext_code, regs->int_parm, regs->int_parm_long);
364 }
365 rcu_read_unlock();
366 return IRQ_HANDLED;
367}
368
369static void __init init_ext_interrupts(void)
370{
371 int idx;
372
373 for (idx = 0; idx < ARRAY_SIZE(ext_int_hash); idx++)
374 INIT_HLIST_HEAD(&ext_int_hash[idx]);
375
376 irq_set_chip_and_handler(EXT_INTERRUPT,
377 &dummy_irq_chip, handle_percpu_irq);
378 if (request_irq(EXT_INTERRUPT, do_ext_interrupt, 0, "EXT", NULL))
379 panic(fmt: "Failed to register EXT interrupt\n");
380}
381
382void __init init_IRQ(void)
383{
384 BUILD_BUG_ON(ARRAY_SIZE(irqclass_sub_desc) != NR_ARCH_IRQS);
385 init_cio_interrupts();
386 init_airq_interrupts();
387 init_ext_interrupts();
388}
389
390static DEFINE_SPINLOCK(irq_subclass_lock);
391static unsigned char irq_subclass_refcount[64];
392
393void irq_subclass_register(enum irq_subclass subclass)
394{
395 spin_lock(lock: &irq_subclass_lock);
396 if (!irq_subclass_refcount[subclass])
397 system_ctl_set_bit(0, subclass);
398 irq_subclass_refcount[subclass]++;
399 spin_unlock(lock: &irq_subclass_lock);
400}
401EXPORT_SYMBOL(irq_subclass_register);
402
403void irq_subclass_unregister(enum irq_subclass subclass)
404{
405 spin_lock(lock: &irq_subclass_lock);
406 irq_subclass_refcount[subclass]--;
407 if (!irq_subclass_refcount[subclass])
408 system_ctl_clear_bit(0, subclass);
409 spin_unlock(lock: &irq_subclass_lock);
410}
411EXPORT_SYMBOL(irq_subclass_unregister);
412

source code of linux/arch/s390/kernel/irq.c