1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2016,2017 IBM Corporation.
4 */
5
6#define pr_fmt(fmt) "xive: " fmt
7
8#include <linux/types.h>
9#include <linux/threads.h>
10#include <linux/kernel.h>
11#include <linux/irq.h>
12#include <linux/irqdomain.h>
13#include <linux/debugfs.h>
14#include <linux/smp.h>
15#include <linux/interrupt.h>
16#include <linux/seq_file.h>
17#include <linux/init.h>
18#include <linux/cpu.h>
19#include <linux/of.h>
20#include <linux/slab.h>
21#include <linux/spinlock.h>
22#include <linux/msi.h>
23#include <linux/vmalloc.h>
24
25#include <asm/io.h>
26#include <asm/smp.h>
27#include <asm/machdep.h>
28#include <asm/irq.h>
29#include <asm/errno.h>
30#include <asm/xive.h>
31#include <asm/xive-regs.h>
32#include <asm/xmon.h>
33
34#include "xive-internal.h"
35
36#undef DEBUG_FLUSH
37#undef DEBUG_ALL
38
39#ifdef DEBUG_ALL
40#define DBG_VERBOSE(fmt, ...) pr_devel("cpu %d - " fmt, \
41 smp_processor_id(), ## __VA_ARGS__)
42#else
43#define DBG_VERBOSE(fmt...) do { } while(0)
44#endif
45
46bool __xive_enabled;
47EXPORT_SYMBOL_GPL(__xive_enabled);
48bool xive_cmdline_disabled;
49
50/* We use only one priority for now */
51static u8 xive_irq_priority;
52
53/* TIMA exported to KVM */
54void __iomem *xive_tima;
55EXPORT_SYMBOL_GPL(xive_tima);
56u32 xive_tima_offset;
57
58/* Backend ops */
59static const struct xive_ops *xive_ops;
60
61/* Our global interrupt domain */
62static struct irq_domain *xive_irq_domain;
63
64#ifdef CONFIG_SMP
65/* The IPIs use the same logical irq number when on the same chip */
66static struct xive_ipi_desc {
67 unsigned int irq;
68 char name[16];
69 atomic_t started;
70} *xive_ipis;
71
72/*
73 * Use early_cpu_to_node() for hot-plugged CPUs
74 */
75static unsigned int xive_ipi_cpu_to_irq(unsigned int cpu)
76{
77 return xive_ipis[early_cpu_to_node(cpu)].irq;
78}
79#endif
80
81/* Xive state for each CPU */
82static DEFINE_PER_CPU(struct xive_cpu *, xive_cpu);
83
84/* An invalid CPU target */
85#define XIVE_INVALID_TARGET (-1)
86
87/*
88 * Global toggle to switch on/off StoreEOI
89 */
90static bool xive_store_eoi = true;
91
92static bool xive_is_store_eoi(struct xive_irq_data *xd)
93{
94 return xd->flags & XIVE_IRQ_FLAG_STORE_EOI && xive_store_eoi;
95}
96
97/*
98 * Read the next entry in a queue, return its content if it's valid
99 * or 0 if there is no new entry.
100 *
101 * The queue pointer is moved forward unless "just_peek" is set
102 */
103static u32 xive_read_eq(struct xive_q *q, bool just_peek)
104{
105 u32 cur;
106
107 if (!q->qpage)
108 return 0;
109 cur = be32_to_cpup(p: q->qpage + q->idx);
110
111 /* Check valid bit (31) vs current toggle polarity */
112 if ((cur >> 31) == q->toggle)
113 return 0;
114
115 /* If consuming from the queue ... */
116 if (!just_peek) {
117 /* Next entry */
118 q->idx = (q->idx + 1) & q->msk;
119
120 /* Wrap around: flip valid toggle */
121 if (q->idx == 0)
122 q->toggle ^= 1;
123 }
124 /* Mask out the valid bit (31) */
125 return cur & 0x7fffffff;
126}
127
128/*
129 * Scans all the queue that may have interrupts in them
130 * (based on "pending_prio") in priority order until an
131 * interrupt is found or all the queues are empty.
132 *
133 * Then updates the CPPR (Current Processor Priority
134 * Register) based on the most favored interrupt found
135 * (0xff if none) and return what was found (0 if none).
136 *
137 * If just_peek is set, return the most favored pending
138 * interrupt if any but don't update the queue pointers.
139 *
140 * Note: This function can operate generically on any number
141 * of queues (up to 8). The current implementation of the XIVE
142 * driver only uses a single queue however.
143 *
144 * Note2: This will also "flush" "the pending_count" of a queue
145 * into the "count" when that queue is observed to be empty.
146 * This is used to keep track of the amount of interrupts
147 * targetting a queue. When an interrupt is moved away from
148 * a queue, we only decrement that queue count once the queue
149 * has been observed empty to avoid races.
150 */
151static u32 xive_scan_interrupts(struct xive_cpu *xc, bool just_peek)
152{
153 u32 irq = 0;
154 u8 prio = 0;
155
156 /* Find highest pending priority */
157 while (xc->pending_prio != 0) {
158 struct xive_q *q;
159
160 prio = ffs(xc->pending_prio) - 1;
161 DBG_VERBOSE("scan_irq: trying prio %d\n", prio);
162
163 /* Try to fetch */
164 irq = xive_read_eq(q: &xc->queue[prio], just_peek);
165
166 /* Found something ? That's it */
167 if (irq) {
168 if (just_peek || irq_to_desc(irq))
169 break;
170 /*
171 * We should never get here; if we do then we must
172 * have failed to synchronize the interrupt properly
173 * when shutting it down.
174 */
175 pr_crit("xive: got interrupt %d without descriptor, dropping\n",
176 irq);
177 WARN_ON(1);
178 continue;
179 }
180
181 /* Clear pending bits */
182 xc->pending_prio &= ~(1 << prio);
183
184 /*
185 * Check if the queue count needs adjusting due to
186 * interrupts being moved away. See description of
187 * xive_dec_target_count()
188 */
189 q = &xc->queue[prio];
190 if (atomic_read(v: &q->pending_count)) {
191 int p = atomic_xchg(v: &q->pending_count, new: 0);
192 if (p) {
193 WARN_ON(p > atomic_read(&q->count));
194 atomic_sub(i: p, v: &q->count);
195 }
196 }
197 }
198
199 /* If nothing was found, set CPPR to 0xff */
200 if (irq == 0)
201 prio = 0xff;
202
203 /* Update HW CPPR to match if necessary */
204 if (prio != xc->cppr) {
205 DBG_VERBOSE("scan_irq: adjusting CPPR to %d\n", prio);
206 xc->cppr = prio;
207 out_8(xive_tima + xive_tima_offset + TM_CPPR, prio);
208 }
209
210 return irq;
211}
212
213/*
214 * This is used to perform the magic loads from an ESB
215 * described in xive-regs.h
216 */
217static notrace u8 xive_esb_read(struct xive_irq_data *xd, u32 offset)
218{
219 u64 val;
220
221 if (offset == XIVE_ESB_SET_PQ_10 && xive_is_store_eoi(xd))
222 offset |= XIVE_ESB_LD_ST_MO;
223
224 if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
225 val = xive_ops->esb_rw(xd->hw_irq, offset, 0, 0);
226 else
227 val = in_be64(xd->eoi_mmio + offset);
228
229 return (u8)val;
230}
231
232static void xive_esb_write(struct xive_irq_data *xd, u32 offset, u64 data)
233{
234 if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
235 xive_ops->esb_rw(xd->hw_irq, offset, data, 1);
236 else
237 out_be64(xd->eoi_mmio + offset, data);
238}
239
240#if defined(CONFIG_XMON) || defined(CONFIG_DEBUG_FS)
241static void xive_irq_data_dump(struct xive_irq_data *xd, char *buffer, size_t size)
242{
243 u64 val = xive_esb_read(xd, offset: XIVE_ESB_GET);
244
245 snprintf(buf: buffer, size, fmt: "flags=%c%c%c PQ=%c%c 0x%016llx 0x%016llx",
246 xive_is_store_eoi(xd) ? 'S' : ' ',
247 xd->flags & XIVE_IRQ_FLAG_LSI ? 'L' : ' ',
248 xd->flags & XIVE_IRQ_FLAG_H_INT_ESB ? 'H' : ' ',
249 val & XIVE_ESB_VAL_P ? 'P' : '-',
250 val & XIVE_ESB_VAL_Q ? 'Q' : '-',
251 xd->trig_page, xd->eoi_page);
252}
253#endif
254
255#ifdef CONFIG_XMON
256static notrace void xive_dump_eq(const char *name, struct xive_q *q)
257{
258 u32 i0, i1, idx;
259
260 if (!q->qpage)
261 return;
262 idx = q->idx;
263 i0 = be32_to_cpup(q->qpage + idx);
264 idx = (idx + 1) & q->msk;
265 i1 = be32_to_cpup(q->qpage + idx);
266 xmon_printf("%s idx=%d T=%d %08x %08x ...", name,
267 q->idx, q->toggle, i0, i1);
268}
269
270notrace void xmon_xive_do_dump(int cpu)
271{
272 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
273
274 xmon_printf("CPU %d:", cpu);
275 if (xc) {
276 xmon_printf("pp=%02x CPPR=%02x ", xc->pending_prio, xc->cppr);
277
278#ifdef CONFIG_SMP
279 {
280 char buffer[128];
281
282 xive_irq_data_dump(&xc->ipi_data, buffer, sizeof(buffer));
283 xmon_printf("IPI=0x%08x %s", xc->hw_ipi, buffer);
284 }
285#endif
286 xive_dump_eq("EQ", &xc->queue[xive_irq_priority]);
287 }
288 xmon_printf("\n");
289}
290
291static struct irq_data *xive_get_irq_data(u32 hw_irq)
292{
293 unsigned int irq = irq_find_mapping(xive_irq_domain, hw_irq);
294
295 return irq ? irq_get_irq_data(irq) : NULL;
296}
297
298int xmon_xive_get_irq_config(u32 hw_irq, struct irq_data *d)
299{
300 int rc;
301 u32 target;
302 u8 prio;
303 u32 lirq;
304
305 rc = xive_ops->get_irq_config(hw_irq, &target, &prio, &lirq);
306 if (rc) {
307 xmon_printf("IRQ 0x%08x : no config rc=%d\n", hw_irq, rc);
308 return rc;
309 }
310
311 xmon_printf("IRQ 0x%08x : target=0x%x prio=%02x lirq=0x%x ",
312 hw_irq, target, prio, lirq);
313
314 if (!d)
315 d = xive_get_irq_data(hw_irq);
316
317 if (d) {
318 char buffer[128];
319
320 xive_irq_data_dump(irq_data_get_irq_chip_data(d),
321 buffer, sizeof(buffer));
322 xmon_printf("%s", buffer);
323 }
324
325 xmon_printf("\n");
326 return 0;
327}
328
329void xmon_xive_get_irq_all(void)
330{
331 unsigned int i;
332 struct irq_desc *desc;
333
334 for_each_irq_desc(i, desc) {
335 struct irq_data *d = irq_domain_get_irq_data(xive_irq_domain, i);
336
337 if (d)
338 xmon_xive_get_irq_config(irqd_to_hwirq(d), d);
339 }
340}
341
342#endif /* CONFIG_XMON */
343
344static unsigned int xive_get_irq(void)
345{
346 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
347 u32 irq;
348
349 /*
350 * This can be called either as a result of a HW interrupt or
351 * as a "replay" because EOI decided there was still something
352 * in one of the queues.
353 *
354 * First we perform an ACK cycle in order to update our mask
355 * of pending priorities. This will also have the effect of
356 * updating the CPPR to the most favored pending interrupts.
357 *
358 * In the future, if we have a way to differentiate a first
359 * entry (on HW interrupt) from a replay triggered by EOI,
360 * we could skip this on replays unless we soft-mask tells us
361 * that a new HW interrupt occurred.
362 */
363 xive_ops->update_pending(xc);
364
365 DBG_VERBOSE("get_irq: pending=%02x\n", xc->pending_prio);
366
367 /* Scan our queue(s) for interrupts */
368 irq = xive_scan_interrupts(xc, just_peek: false);
369
370 DBG_VERBOSE("get_irq: got irq 0x%x, new pending=0x%02x\n",
371 irq, xc->pending_prio);
372
373 /* Return pending interrupt if any */
374 if (irq == XIVE_BAD_IRQ)
375 return 0;
376 return irq;
377}
378
379/*
380 * After EOI'ing an interrupt, we need to re-check the queue
381 * to see if another interrupt is pending since multiple
382 * interrupts can coalesce into a single notification to the
383 * CPU.
384 *
385 * If we find that there is indeed more in there, we call
386 * force_external_irq_replay() to make Linux synthesize an
387 * external interrupt on the next call to local_irq_restore().
388 */
389static void xive_do_queue_eoi(struct xive_cpu *xc)
390{
391 if (xive_scan_interrupts(xc, just_peek: true) != 0) {
392 DBG_VERBOSE("eoi: pending=0x%02x\n", xc->pending_prio);
393 force_external_irq_replay();
394 }
395}
396
397/*
398 * EOI an interrupt at the source. There are several methods
399 * to do this depending on the HW version and source type
400 */
401static void xive_do_source_eoi(struct xive_irq_data *xd)
402{
403 u8 eoi_val;
404
405 xd->stale_p = false;
406
407 /* If the XIVE supports the new "store EOI facility, use it */
408 if (xive_is_store_eoi(xd)) {
409 xive_esb_write(xd, offset: XIVE_ESB_STORE_EOI, data: 0);
410 return;
411 }
412
413 /*
414 * For LSIs, we use the "EOI cycle" special load rather than
415 * PQ bits, as they are automatically re-triggered in HW when
416 * still pending.
417 */
418 if (xd->flags & XIVE_IRQ_FLAG_LSI) {
419 xive_esb_read(xd, offset: XIVE_ESB_LOAD_EOI);
420 return;
421 }
422
423 /*
424 * Otherwise, we use the special MMIO that does a clear of
425 * both P and Q and returns the old Q. This allows us to then
426 * do a re-trigger if Q was set rather than synthesizing an
427 * interrupt in software
428 */
429 eoi_val = xive_esb_read(xd, offset: XIVE_ESB_SET_PQ_00);
430 DBG_VERBOSE("eoi_val=%x\n", eoi_val);
431
432 /* Re-trigger if needed */
433 if ((eoi_val & XIVE_ESB_VAL_Q) && xd->trig_mmio)
434 out_be64(xd->trig_mmio, 0);
435}
436
437/* irq_chip eoi callback, called with irq descriptor lock held */
438static void xive_irq_eoi(struct irq_data *d)
439{
440 struct xive_irq_data *xd = irq_data_get_irq_chip_data(d);
441 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
442
443 DBG_VERBOSE("eoi_irq: irq=%d [0x%lx] pending=%02x\n",
444 d->irq, irqd_to_hwirq(d), xc->pending_prio);
445
446 /*
447 * EOI the source if it hasn't been disabled and hasn't
448 * been passed-through to a KVM guest
449 */
450 if (!irqd_irq_disabled(d) && !irqd_is_forwarded_to_vcpu(d) &&
451 !(xd->flags & XIVE_IRQ_FLAG_NO_EOI))
452 xive_do_source_eoi(xd);
453 else
454 xd->stale_p = true;
455
456 /*
457 * Clear saved_p to indicate that it's no longer occupying
458 * a queue slot on the target queue
459 */
460 xd->saved_p = false;
461
462 /* Check for more work in the queue */
463 xive_do_queue_eoi(xc);
464}
465
466/*
467 * Helper used to mask and unmask an interrupt source.
468 */
469static void xive_do_source_set_mask(struct xive_irq_data *xd,
470 bool mask)
471{
472 u64 val;
473
474 pr_debug("%s: HW 0x%x %smask\n", __func__, xd->hw_irq, mask ? "" : "un");
475
476 /*
477 * If the interrupt had P set, it may be in a queue.
478 *
479 * We need to make sure we don't re-enable it until it
480 * has been fetched from that queue and EOId. We keep
481 * a copy of that P state and use it to restore the
482 * ESB accordingly on unmask.
483 */
484 if (mask) {
485 val = xive_esb_read(xd, offset: XIVE_ESB_SET_PQ_01);
486 if (!xd->stale_p && !!(val & XIVE_ESB_VAL_P))
487 xd->saved_p = true;
488 xd->stale_p = false;
489 } else if (xd->saved_p) {
490 xive_esb_read(xd, offset: XIVE_ESB_SET_PQ_10);
491 xd->saved_p = false;
492 } else {
493 xive_esb_read(xd, offset: XIVE_ESB_SET_PQ_00);
494 xd->stale_p = false;
495 }
496}
497
498/*
499 * Try to chose "cpu" as a new interrupt target. Increments
500 * the queue accounting for that target if it's not already
501 * full.
502 */
503static bool xive_try_pick_target(int cpu)
504{
505 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
506 struct xive_q *q = &xc->queue[xive_irq_priority];
507 int max;
508
509 /*
510 * Calculate max number of interrupts in that queue.
511 *
512 * We leave a gap of 1 just in case...
513 */
514 max = (q->msk + 1) - 1;
515 return !!atomic_add_unless(v: &q->count, a: 1, u: max);
516}
517
518/*
519 * Un-account an interrupt for a target CPU. We don't directly
520 * decrement q->count since the interrupt might still be present
521 * in the queue.
522 *
523 * Instead increment a separate counter "pending_count" which
524 * will be substracted from "count" later when that CPU observes
525 * the queue to be empty.
526 */
527static void xive_dec_target_count(int cpu)
528{
529 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
530 struct xive_q *q = &xc->queue[xive_irq_priority];
531
532 if (WARN_ON(cpu < 0 || !xc)) {
533 pr_err("%s: cpu=%d xc=%p\n", __func__, cpu, xc);
534 return;
535 }
536
537 /*
538 * We increment the "pending count" which will be used
539 * to decrement the target queue count whenever it's next
540 * processed and found empty. This ensure that we don't
541 * decrement while we still have the interrupt there
542 * occupying a slot.
543 */
544 atomic_inc(v: &q->pending_count);
545}
546
547/* Find a tentative CPU target in a CPU mask */
548static int xive_find_target_in_mask(const struct cpumask *mask,
549 unsigned int fuzz)
550{
551 int cpu, first, num, i;
552
553 /* Pick up a starting point CPU in the mask based on fuzz */
554 num = min_t(int, cpumask_weight(mask), nr_cpu_ids);
555 first = fuzz % num;
556
557 /* Locate it */
558 cpu = cpumask_first(srcp: mask);
559 for (i = 0; i < first && cpu < nr_cpu_ids; i++)
560 cpu = cpumask_next(n: cpu, srcp: mask);
561
562 /* Sanity check */
563 if (WARN_ON(cpu >= nr_cpu_ids))
564 cpu = cpumask_first(cpu_online_mask);
565
566 /* Remember first one to handle wrap-around */
567 first = cpu;
568
569 /*
570 * Now go through the entire mask until we find a valid
571 * target.
572 */
573 do {
574 /*
575 * We re-check online as the fallback case passes us
576 * an untested affinity mask
577 */
578 if (cpu_online(cpu) && xive_try_pick_target(cpu))
579 return cpu;
580 cpu = cpumask_next(n: cpu, srcp: mask);
581 /* Wrap around */
582 if (cpu >= nr_cpu_ids)
583 cpu = cpumask_first(srcp: mask);
584 } while (cpu != first);
585
586 return -1;
587}
588
589/*
590 * Pick a target CPU for an interrupt. This is done at
591 * startup or if the affinity is changed in a way that
592 * invalidates the current target.
593 */
594static int xive_pick_irq_target(struct irq_data *d,
595 const struct cpumask *affinity)
596{
597 static unsigned int fuzz;
598 struct xive_irq_data *xd = irq_data_get_irq_chip_data(d);
599 cpumask_var_t mask;
600 int cpu = -1;
601
602 /*
603 * If we have chip IDs, first we try to build a mask of
604 * CPUs matching the CPU and find a target in there
605 */
606 if (xd->src_chip != XIVE_INVALID_CHIP_ID &&
607 zalloc_cpumask_var(mask: &mask, GFP_ATOMIC)) {
608 /* Build a mask of matching chip IDs */
609 for_each_cpu_and(cpu, affinity, cpu_online_mask) {
610 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
611 if (xc->chip_id == xd->src_chip)
612 cpumask_set_cpu(cpu, dstp: mask);
613 }
614 /* Try to find a target */
615 if (cpumask_empty(srcp: mask))
616 cpu = -1;
617 else
618 cpu = xive_find_target_in_mask(mask, fuzz: fuzz++);
619 free_cpumask_var(mask);
620 if (cpu >= 0)
621 return cpu;
622 fuzz--;
623 }
624
625 /* No chip IDs, fallback to using the affinity mask */
626 return xive_find_target_in_mask(mask: affinity, fuzz: fuzz++);
627}
628
629static unsigned int xive_irq_startup(struct irq_data *d)
630{
631 struct xive_irq_data *xd = irq_data_get_irq_chip_data(d);
632 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
633 int target, rc;
634
635 xd->saved_p = false;
636 xd->stale_p = false;
637
638 pr_debug("%s: irq %d [0x%x] data @%p\n", __func__, d->irq, hw_irq, d);
639
640 /* Pick a target */
641 target = xive_pick_irq_target(d, affinity: irq_data_get_affinity_mask(d));
642 if (target == XIVE_INVALID_TARGET) {
643 /* Try again breaking affinity */
644 target = xive_pick_irq_target(d, cpu_online_mask);
645 if (target == XIVE_INVALID_TARGET)
646 return -ENXIO;
647 pr_warn("irq %d started with broken affinity\n", d->irq);
648 }
649
650 /* Sanity check */
651 if (WARN_ON(target == XIVE_INVALID_TARGET ||
652 target >= nr_cpu_ids))
653 target = smp_processor_id();
654
655 xd->target = target;
656
657 /*
658 * Configure the logical number to be the Linux IRQ number
659 * and set the target queue
660 */
661 rc = xive_ops->configure_irq(hw_irq,
662 get_hard_smp_processor_id(target),
663 xive_irq_priority, d->irq);
664 if (rc)
665 return rc;
666
667 /* Unmask the ESB */
668 xive_do_source_set_mask(xd, mask: false);
669
670 return 0;
671}
672
673/* called with irq descriptor lock held */
674static void xive_irq_shutdown(struct irq_data *d)
675{
676 struct xive_irq_data *xd = irq_data_get_irq_chip_data(d);
677 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
678
679 pr_debug("%s: irq %d [0x%x] data @%p\n", __func__, d->irq, hw_irq, d);
680
681 if (WARN_ON(xd->target == XIVE_INVALID_TARGET))
682 return;
683
684 /* Mask the interrupt at the source */
685 xive_do_source_set_mask(xd, mask: true);
686
687 /*
688 * Mask the interrupt in HW in the IVT/EAS and set the number
689 * to be the "bad" IRQ number
690 */
691 xive_ops->configure_irq(hw_irq,
692 get_hard_smp_processor_id(xd->target),
693 0xff, XIVE_BAD_IRQ);
694
695 xive_dec_target_count(cpu: xd->target);
696 xd->target = XIVE_INVALID_TARGET;
697}
698
699static void xive_irq_unmask(struct irq_data *d)
700{
701 struct xive_irq_data *xd = irq_data_get_irq_chip_data(d);
702
703 pr_debug("%s: irq %d data @%p\n", __func__, d->irq, xd);
704
705 xive_do_source_set_mask(xd, mask: false);
706}
707
708static void xive_irq_mask(struct irq_data *d)
709{
710 struct xive_irq_data *xd = irq_data_get_irq_chip_data(d);
711
712 pr_debug("%s: irq %d data @%p\n", __func__, d->irq, xd);
713
714 xive_do_source_set_mask(xd, mask: true);
715}
716
717static int xive_irq_set_affinity(struct irq_data *d,
718 const struct cpumask *cpumask,
719 bool force)
720{
721 struct xive_irq_data *xd = irq_data_get_irq_chip_data(d);
722 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
723 u32 target, old_target;
724 int rc = 0;
725
726 pr_debug("%s: irq %d/0x%x\n", __func__, d->irq, hw_irq);
727
728 /* Is this valid ? */
729 if (!cpumask_intersects(src1p: cpumask, cpu_online_mask))
730 return -EINVAL;
731
732 /*
733 * If existing target is already in the new mask, and is
734 * online then do nothing.
735 */
736 if (xd->target != XIVE_INVALID_TARGET &&
737 cpu_online(cpu: xd->target) &&
738 cpumask_test_cpu(cpu: xd->target, cpumask))
739 return IRQ_SET_MASK_OK;
740
741 /* Pick a new target */
742 target = xive_pick_irq_target(d, affinity: cpumask);
743
744 /* No target found */
745 if (target == XIVE_INVALID_TARGET)
746 return -ENXIO;
747
748 /* Sanity check */
749 if (WARN_ON(target >= nr_cpu_ids))
750 target = smp_processor_id();
751
752 old_target = xd->target;
753
754 /*
755 * Only configure the irq if it's not currently passed-through to
756 * a KVM guest
757 */
758 if (!irqd_is_forwarded_to_vcpu(d))
759 rc = xive_ops->configure_irq(hw_irq,
760 get_hard_smp_processor_id(target),
761 xive_irq_priority, d->irq);
762 if (rc < 0) {
763 pr_err("Error %d reconfiguring irq %d\n", rc, d->irq);
764 return rc;
765 }
766
767 pr_debug(" target: 0x%x\n", target);
768 xd->target = target;
769
770 /* Give up previous target */
771 if (old_target != XIVE_INVALID_TARGET)
772 xive_dec_target_count(cpu: old_target);
773
774 return IRQ_SET_MASK_OK;
775}
776
777static int xive_irq_set_type(struct irq_data *d, unsigned int flow_type)
778{
779 struct xive_irq_data *xd = irq_data_get_irq_chip_data(d);
780
781 /*
782 * We only support these. This has really no effect other than setting
783 * the corresponding descriptor bits mind you but those will in turn
784 * affect the resend function when re-enabling an edge interrupt.
785 *
786 * Set the default to edge as explained in map().
787 */
788 if (flow_type == IRQ_TYPE_DEFAULT || flow_type == IRQ_TYPE_NONE)
789 flow_type = IRQ_TYPE_EDGE_RISING;
790
791 if (flow_type != IRQ_TYPE_EDGE_RISING &&
792 flow_type != IRQ_TYPE_LEVEL_LOW)
793 return -EINVAL;
794
795 irqd_set_trigger_type(d, type: flow_type);
796
797 /*
798 * Double check it matches what the FW thinks
799 *
800 * NOTE: We don't know yet if the PAPR interface will provide
801 * the LSI vs MSI information apart from the device-tree so
802 * this check might have to move into an optional backend call
803 * that is specific to the native backend
804 */
805 if ((flow_type == IRQ_TYPE_LEVEL_LOW) !=
806 !!(xd->flags & XIVE_IRQ_FLAG_LSI)) {
807 pr_warn("Interrupt %d (HW 0x%x) type mismatch, Linux says %s, FW says %s\n",
808 d->irq, (u32)irqd_to_hwirq(d),
809 (flow_type == IRQ_TYPE_LEVEL_LOW) ? "Level" : "Edge",
810 (xd->flags & XIVE_IRQ_FLAG_LSI) ? "Level" : "Edge");
811 }
812
813 return IRQ_SET_MASK_OK_NOCOPY;
814}
815
816static int xive_irq_retrigger(struct irq_data *d)
817{
818 struct xive_irq_data *xd = irq_data_get_irq_chip_data(d);
819
820 /* This should be only for MSIs */
821 if (WARN_ON(xd->flags & XIVE_IRQ_FLAG_LSI))
822 return 0;
823
824 /*
825 * To perform a retrigger, we first set the PQ bits to
826 * 11, then perform an EOI.
827 */
828 xive_esb_read(xd, offset: XIVE_ESB_SET_PQ_11);
829 xive_do_source_eoi(xd);
830
831 return 1;
832}
833
834/*
835 * Caller holds the irq descriptor lock, so this won't be called
836 * concurrently with xive_get_irqchip_state on the same interrupt.
837 */
838static int xive_irq_set_vcpu_affinity(struct irq_data *d, void *state)
839{
840 struct xive_irq_data *xd = irq_data_get_irq_chip_data(d);
841 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
842 int rc;
843 u8 pq;
844
845 /*
846 * This is called by KVM with state non-NULL for enabling
847 * pass-through or NULL for disabling it
848 */
849 if (state) {
850 irqd_set_forwarded_to_vcpu(d);
851
852 /* Set it to PQ=10 state to prevent further sends */
853 pq = xive_esb_read(xd, offset: XIVE_ESB_SET_PQ_10);
854 if (!xd->stale_p) {
855 xd->saved_p = !!(pq & XIVE_ESB_VAL_P);
856 xd->stale_p = !xd->saved_p;
857 }
858
859 /* No target ? nothing to do */
860 if (xd->target == XIVE_INVALID_TARGET) {
861 /*
862 * An untargetted interrupt should have been
863 * also masked at the source
864 */
865 WARN_ON(xd->saved_p);
866
867 return 0;
868 }
869
870 /*
871 * If P was set, adjust state to PQ=11 to indicate
872 * that a resend is needed for the interrupt to reach
873 * the guest. Also remember the value of P.
874 *
875 * This also tells us that it's in flight to a host queue
876 * or has already been fetched but hasn't been EOIed yet
877 * by the host. Thus it's potentially using up a host
878 * queue slot. This is important to know because as long
879 * as this is the case, we must not hard-unmask it when
880 * "returning" that interrupt to the host.
881 *
882 * This saved_p is cleared by the host EOI, when we know
883 * for sure the queue slot is no longer in use.
884 */
885 if (xd->saved_p) {
886 xive_esb_read(xd, offset: XIVE_ESB_SET_PQ_11);
887
888 /*
889 * Sync the XIVE source HW to ensure the interrupt
890 * has gone through the EAS before we change its
891 * target to the guest. That should guarantee us
892 * that we *will* eventually get an EOI for it on
893 * the host. Otherwise there would be a small window
894 * for P to be seen here but the interrupt going
895 * to the guest queue.
896 */
897 if (xive_ops->sync_source)
898 xive_ops->sync_source(hw_irq);
899 }
900 } else {
901 irqd_clr_forwarded_to_vcpu(d);
902
903 /* No host target ? hard mask and return */
904 if (xd->target == XIVE_INVALID_TARGET) {
905 xive_do_source_set_mask(xd, mask: true);
906 return 0;
907 }
908
909 /*
910 * Sync the XIVE source HW to ensure the interrupt
911 * has gone through the EAS before we change its
912 * target to the host.
913 */
914 if (xive_ops->sync_source)
915 xive_ops->sync_source(hw_irq);
916
917 /*
918 * By convention we are called with the interrupt in
919 * a PQ=10 or PQ=11 state, ie, it won't fire and will
920 * have latched in Q whether there's a pending HW
921 * interrupt or not.
922 *
923 * First reconfigure the target.
924 */
925 rc = xive_ops->configure_irq(hw_irq,
926 get_hard_smp_processor_id(xd->target),
927 xive_irq_priority, d->irq);
928 if (rc)
929 return rc;
930
931 /*
932 * Then if saved_p is not set, effectively re-enable the
933 * interrupt with an EOI. If it is set, we know there is
934 * still a message in a host queue somewhere that will be
935 * EOId eventually.
936 *
937 * Note: We don't check irqd_irq_disabled(). Effectively,
938 * we *will* let the irq get through even if masked if the
939 * HW is still firing it in order to deal with the whole
940 * saved_p business properly. If the interrupt triggers
941 * while masked, the generic code will re-mask it anyway.
942 */
943 if (!xd->saved_p)
944 xive_do_source_eoi(xd);
945
946 }
947 return 0;
948}
949
950/* Called with irq descriptor lock held. */
951static int xive_get_irqchip_state(struct irq_data *data,
952 enum irqchip_irq_state which, bool *state)
953{
954 struct xive_irq_data *xd = irq_data_get_irq_chip_data(d: data);
955 u8 pq;
956
957 switch (which) {
958 case IRQCHIP_STATE_ACTIVE:
959 pq = xive_esb_read(xd, offset: XIVE_ESB_GET);
960
961 /*
962 * The esb value being all 1's means we couldn't get
963 * the PQ state of the interrupt through mmio. It may
964 * happen, for example when querying a PHB interrupt
965 * while the PHB is in an error state. We consider the
966 * interrupt to be inactive in that case.
967 */
968 *state = (pq != XIVE_ESB_INVALID) && !xd->stale_p &&
969 (xd->saved_p || (!!(pq & XIVE_ESB_VAL_P) &&
970 !irqd_irq_disabled(data)));
971 return 0;
972 default:
973 return -EINVAL;
974 }
975}
976
977static struct irq_chip xive_irq_chip = {
978 .name = "XIVE-IRQ",
979 .irq_startup = xive_irq_startup,
980 .irq_shutdown = xive_irq_shutdown,
981 .irq_eoi = xive_irq_eoi,
982 .irq_mask = xive_irq_mask,
983 .irq_unmask = xive_irq_unmask,
984 .irq_set_affinity = xive_irq_set_affinity,
985 .irq_set_type = xive_irq_set_type,
986 .irq_retrigger = xive_irq_retrigger,
987 .irq_set_vcpu_affinity = xive_irq_set_vcpu_affinity,
988 .irq_get_irqchip_state = xive_get_irqchip_state,
989};
990
991bool is_xive_irq(struct irq_chip *chip)
992{
993 return chip == &xive_irq_chip;
994}
995EXPORT_SYMBOL_GPL(is_xive_irq);
996
997void xive_cleanup_irq_data(struct xive_irq_data *xd)
998{
999 pr_debug("%s for HW 0x%x\n", __func__, xd->hw_irq);
1000
1001 if (xd->eoi_mmio) {
1002 iounmap(addr: xd->eoi_mmio);
1003 if (xd->eoi_mmio == xd->trig_mmio)
1004 xd->trig_mmio = NULL;
1005 xd->eoi_mmio = NULL;
1006 }
1007 if (xd->trig_mmio) {
1008 iounmap(addr: xd->trig_mmio);
1009 xd->trig_mmio = NULL;
1010 }
1011}
1012EXPORT_SYMBOL_GPL(xive_cleanup_irq_data);
1013
1014static struct xive_irq_data *xive_irq_alloc_data(unsigned int virq, irq_hw_number_t hw)
1015{
1016 struct xive_irq_data *xd;
1017 int rc;
1018
1019 xd = kzalloc(sizeof(struct xive_irq_data), GFP_KERNEL);
1020 if (!xd)
1021 return ERR_PTR(error: -ENOMEM);
1022 rc = xive_ops->populate_irq_data(hw, xd);
1023 if (rc) {
1024 kfree(objp: xd);
1025 return ERR_PTR(error: rc);
1026 }
1027 xd->target = XIVE_INVALID_TARGET;
1028
1029 /*
1030 * Turn OFF by default the interrupt being mapped. A side
1031 * effect of this check is the mapping the ESB page of the
1032 * interrupt in the Linux address space. This prevents page
1033 * fault issues in the crash handler which masks all
1034 * interrupts.
1035 */
1036 xive_esb_read(xd, offset: XIVE_ESB_SET_PQ_01);
1037
1038 return xd;
1039}
1040
1041static void xive_irq_free_data(unsigned int virq)
1042{
1043 struct xive_irq_data *xd = irq_get_chip_data(irq: virq);
1044
1045 if (!xd)
1046 return;
1047 irq_set_chip_data(irq: virq, NULL);
1048 xive_cleanup_irq_data(xd);
1049 kfree(objp: xd);
1050}
1051
1052#ifdef CONFIG_SMP
1053
1054static void xive_cause_ipi(int cpu)
1055{
1056 struct xive_cpu *xc;
1057 struct xive_irq_data *xd;
1058
1059 xc = per_cpu(xive_cpu, cpu);
1060
1061 DBG_VERBOSE("IPI CPU %d -> %d (HW IRQ 0x%x)\n",
1062 smp_processor_id(), cpu, xc->hw_ipi);
1063
1064 xd = &xc->ipi_data;
1065 if (WARN_ON(!xd->trig_mmio))
1066 return;
1067 out_be64(xd->trig_mmio, 0);
1068}
1069
1070static irqreturn_t xive_muxed_ipi_action(int irq, void *dev_id)
1071{
1072 return smp_ipi_demux();
1073}
1074
1075static void xive_ipi_eoi(struct irq_data *d)
1076{
1077 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1078
1079 /* Handle possible race with unplug and drop stale IPIs */
1080 if (!xc)
1081 return;
1082
1083 DBG_VERBOSE("IPI eoi: irq=%d [0x%lx] (HW IRQ 0x%x) pending=%02x\n",
1084 d->irq, irqd_to_hwirq(d), xc->hw_ipi, xc->pending_prio);
1085
1086 xive_do_source_eoi(xd: &xc->ipi_data);
1087 xive_do_queue_eoi(xc);
1088}
1089
1090static void xive_ipi_do_nothing(struct irq_data *d)
1091{
1092 /*
1093 * Nothing to do, we never mask/unmask IPIs, but the callback
1094 * has to exist for the struct irq_chip.
1095 */
1096}
1097
1098static struct irq_chip xive_ipi_chip = {
1099 .name = "XIVE-IPI",
1100 .irq_eoi = xive_ipi_eoi,
1101 .irq_mask = xive_ipi_do_nothing,
1102 .irq_unmask = xive_ipi_do_nothing,
1103};
1104
1105/*
1106 * IPIs are marked per-cpu. We use separate HW interrupts under the
1107 * hood but associated with the same "linux" interrupt
1108 */
1109struct xive_ipi_alloc_info {
1110 irq_hw_number_t hwirq;
1111};
1112
1113static int xive_ipi_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1114 unsigned int nr_irqs, void *arg)
1115{
1116 struct xive_ipi_alloc_info *info = arg;
1117 int i;
1118
1119 for (i = 0; i < nr_irqs; i++) {
1120 irq_domain_set_info(domain, virq: virq + i, hwirq: info->hwirq + i, chip: &xive_ipi_chip,
1121 chip_data: domain->host_data, handler: handle_percpu_irq,
1122 NULL, NULL);
1123 }
1124 return 0;
1125}
1126
1127static const struct irq_domain_ops xive_ipi_irq_domain_ops = {
1128 .alloc = xive_ipi_irq_domain_alloc,
1129};
1130
1131static int __init xive_init_ipis(void)
1132{
1133 struct fwnode_handle *fwnode;
1134 struct irq_domain *ipi_domain;
1135 unsigned int node;
1136 int ret = -ENOMEM;
1137
1138 fwnode = irq_domain_alloc_named_fwnode(name: "XIVE-IPI");
1139 if (!fwnode)
1140 goto out;
1141
1142 ipi_domain = irq_domain_create_linear(fwnode, size: nr_node_ids,
1143 ops: &xive_ipi_irq_domain_ops, NULL);
1144 if (!ipi_domain)
1145 goto out_free_fwnode;
1146
1147 xive_ipis = kcalloc(nr_node_ids, sizeof(*xive_ipis), GFP_KERNEL | __GFP_NOFAIL);
1148 if (!xive_ipis)
1149 goto out_free_domain;
1150
1151 for_each_node(node) {
1152 struct xive_ipi_desc *xid = &xive_ipis[node];
1153 struct xive_ipi_alloc_info info = { node };
1154
1155 /*
1156 * Map one IPI interrupt per node for all cpus of that node.
1157 * Since the HW interrupt number doesn't have any meaning,
1158 * simply use the node number.
1159 */
1160 ret = irq_domain_alloc_irqs(domain: ipi_domain, nr_irqs: 1, node, arg: &info);
1161 if (ret < 0)
1162 goto out_free_xive_ipis;
1163 xid->irq = ret;
1164
1165 snprintf(buf: xid->name, size: sizeof(xid->name), fmt: "IPI-%d", node);
1166 }
1167
1168 return ret;
1169
1170out_free_xive_ipis:
1171 kfree(objp: xive_ipis);
1172out_free_domain:
1173 irq_domain_remove(domain: ipi_domain);
1174out_free_fwnode:
1175 irq_domain_free_fwnode(fwnode);
1176out:
1177 return ret;
1178}
1179
1180static int xive_request_ipi(unsigned int cpu)
1181{
1182 struct xive_ipi_desc *xid = &xive_ipis[early_cpu_to_node(cpu)];
1183 int ret;
1184
1185 if (atomic_inc_return(v: &xid->started) > 1)
1186 return 0;
1187
1188 ret = request_irq(irq: xid->irq, handler: xive_muxed_ipi_action,
1189 IRQF_NO_DEBUG | IRQF_PERCPU | IRQF_NO_THREAD,
1190 name: xid->name, NULL);
1191
1192 WARN(ret < 0, "Failed to request IPI %d: %d\n", xid->irq, ret);
1193 return ret;
1194}
1195
1196static int xive_setup_cpu_ipi(unsigned int cpu)
1197{
1198 unsigned int xive_ipi_irq = xive_ipi_cpu_to_irq(cpu);
1199 struct xive_cpu *xc;
1200 int rc;
1201
1202 pr_debug("Setting up IPI for CPU %d\n", cpu);
1203
1204 xc = per_cpu(xive_cpu, cpu);
1205
1206 /* Check if we are already setup */
1207 if (xc->hw_ipi != XIVE_BAD_IRQ)
1208 return 0;
1209
1210 /* Register the IPI */
1211 xive_request_ipi(cpu);
1212
1213 /* Grab an IPI from the backend, this will populate xc->hw_ipi */
1214 if (xive_ops->get_ipi(cpu, xc))
1215 return -EIO;
1216
1217 /*
1218 * Populate the IRQ data in the xive_cpu structure and
1219 * configure the HW / enable the IPIs.
1220 */
1221 rc = xive_ops->populate_irq_data(xc->hw_ipi, &xc->ipi_data);
1222 if (rc) {
1223 pr_err("Failed to populate IPI data on CPU %d\n", cpu);
1224 return -EIO;
1225 }
1226 rc = xive_ops->configure_irq(xc->hw_ipi,
1227 get_hard_smp_processor_id(cpu),
1228 xive_irq_priority, xive_ipi_irq);
1229 if (rc) {
1230 pr_err("Failed to map IPI CPU %d\n", cpu);
1231 return -EIO;
1232 }
1233 pr_debug("CPU %d HW IPI 0x%x, virq %d, trig_mmio=%p\n", cpu,
1234 xc->hw_ipi, xive_ipi_irq, xc->ipi_data.trig_mmio);
1235
1236 /* Unmask it */
1237 xive_do_source_set_mask(xd: &xc->ipi_data, mask: false);
1238
1239 return 0;
1240}
1241
1242noinstr static void xive_cleanup_cpu_ipi(unsigned int cpu, struct xive_cpu *xc)
1243{
1244 unsigned int xive_ipi_irq = xive_ipi_cpu_to_irq(cpu);
1245
1246 /* Disable the IPI and free the IRQ data */
1247
1248 /* Already cleaned up ? */
1249 if (xc->hw_ipi == XIVE_BAD_IRQ)
1250 return;
1251
1252 /* TODO: clear IPI mapping */
1253
1254 /* Mask the IPI */
1255 xive_do_source_set_mask(xd: &xc->ipi_data, mask: true);
1256
1257 /*
1258 * Note: We don't call xive_cleanup_irq_data() to free
1259 * the mappings as this is called from an IPI on kexec
1260 * which is not a safe environment to call iounmap()
1261 */
1262
1263 /* Deconfigure/mask in the backend */
1264 xive_ops->configure_irq(xc->hw_ipi, hard_smp_processor_id(),
1265 0xff, xive_ipi_irq);
1266
1267 /* Free the IPIs in the backend */
1268 xive_ops->put_ipi(cpu, xc);
1269}
1270
1271void __init xive_smp_probe(void)
1272{
1273 smp_ops->cause_ipi = xive_cause_ipi;
1274
1275 /* Register the IPI */
1276 xive_init_ipis();
1277
1278 /* Allocate and setup IPI for the boot CPU */
1279 xive_setup_cpu_ipi(smp_processor_id());
1280}
1281
1282#endif /* CONFIG_SMP */
1283
1284static int xive_irq_domain_map(struct irq_domain *h, unsigned int virq,
1285 irq_hw_number_t hw)
1286{
1287 struct xive_irq_data *xd;
1288
1289 /*
1290 * Mark interrupts as edge sensitive by default so that resend
1291 * actually works. Will fix that up below if needed.
1292 */
1293 irq_clear_status_flags(irq: virq, clr: IRQ_LEVEL);
1294
1295 xd = xive_irq_alloc_data(virq, hw);
1296 if (IS_ERR(ptr: xd))
1297 return PTR_ERR(ptr: xd);
1298
1299 irq_set_chip_and_handler(irq: virq, chip: &xive_irq_chip, handle: handle_fasteoi_irq);
1300 irq_set_chip_data(irq: virq, data: xd);
1301
1302 return 0;
1303}
1304
1305static void xive_irq_domain_unmap(struct irq_domain *d, unsigned int virq)
1306{
1307 xive_irq_free_data(virq);
1308}
1309
1310static int xive_irq_domain_xlate(struct irq_domain *h, struct device_node *ct,
1311 const u32 *intspec, unsigned int intsize,
1312 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1313
1314{
1315 *out_hwirq = intspec[0];
1316
1317 /*
1318 * If intsize is at least 2, we look for the type in the second cell,
1319 * we assume the LSB indicates a level interrupt.
1320 */
1321 if (intsize > 1) {
1322 if (intspec[1] & 1)
1323 *out_flags = IRQ_TYPE_LEVEL_LOW;
1324 else
1325 *out_flags = IRQ_TYPE_EDGE_RISING;
1326 } else
1327 *out_flags = IRQ_TYPE_LEVEL_LOW;
1328
1329 return 0;
1330}
1331
1332static int xive_irq_domain_match(struct irq_domain *h, struct device_node *node,
1333 enum irq_domain_bus_token bus_token)
1334{
1335 return xive_ops->match(node);
1336}
1337
1338#ifdef CONFIG_GENERIC_IRQ_DEBUGFS
1339static const char * const esb_names[] = { "RESET", "OFF", "PENDING", "QUEUED" };
1340
1341static const struct {
1342 u64 mask;
1343 char *name;
1344} xive_irq_flags[] = {
1345 { XIVE_IRQ_FLAG_STORE_EOI, "STORE_EOI" },
1346 { XIVE_IRQ_FLAG_LSI, "LSI" },
1347 { XIVE_IRQ_FLAG_H_INT_ESB, "H_INT_ESB" },
1348 { XIVE_IRQ_FLAG_NO_EOI, "NO_EOI" },
1349};
1350
1351static void xive_irq_domain_debug_show(struct seq_file *m, struct irq_domain *d,
1352 struct irq_data *irqd, int ind)
1353{
1354 struct xive_irq_data *xd;
1355 u64 val;
1356 int i;
1357
1358 /* No IRQ domain level information. To be done */
1359 if (!irqd)
1360 return;
1361
1362 if (!is_xive_irq(irq_data_get_irq_chip(d: irqd)))
1363 return;
1364
1365 seq_printf(m, fmt: "%*sXIVE:\n", ind, "");
1366 ind++;
1367
1368 xd = irq_data_get_irq_chip_data(d: irqd);
1369 if (!xd) {
1370 seq_printf(m, fmt: "%*snot assigned\n", ind, "");
1371 return;
1372 }
1373
1374 val = xive_esb_read(xd, XIVE_ESB_GET);
1375 seq_printf(m, fmt: "%*sESB: %s\n", ind, "", esb_names[val & 0x3]);
1376 seq_printf(m, fmt: "%*sPstate: %s %s\n", ind, "", xd->stale_p ? "stale" : "",
1377 xd->saved_p ? "saved" : "");
1378 seq_printf(m, fmt: "%*sTarget: %d\n", ind, "", xd->target);
1379 seq_printf(m, fmt: "%*sChip: %d\n", ind, "", xd->src_chip);
1380 seq_printf(m, fmt: "%*sTrigger: 0x%016llx\n", ind, "", xd->trig_page);
1381 seq_printf(m, fmt: "%*sEOI: 0x%016llx\n", ind, "", xd->eoi_page);
1382 seq_printf(m, fmt: "%*sFlags: 0x%llx\n", ind, "", xd->flags);
1383 for (i = 0; i < ARRAY_SIZE(xive_irq_flags); i++) {
1384 if (xd->flags & xive_irq_flags[i].mask)
1385 seq_printf(m, "%*s%s\n", ind + 12, "", xive_irq_flags[i].name);
1386 }
1387}
1388#endif
1389
1390#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
1391static int xive_irq_domain_translate(struct irq_domain *d,
1392 struct irq_fwspec *fwspec,
1393 unsigned long *hwirq,
1394 unsigned int *type)
1395{
1396 return xive_irq_domain_xlate(h: d, to_of_node(fwspec->fwnode),
1397 intspec: fwspec->param, intsize: fwspec->param_count,
1398 out_hwirq: hwirq, out_flags: type);
1399}
1400
1401static int xive_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1402 unsigned int nr_irqs, void *arg)
1403{
1404 struct irq_fwspec *fwspec = arg;
1405 struct xive_irq_data *xd;
1406 irq_hw_number_t hwirq;
1407 unsigned int type = IRQ_TYPE_NONE;
1408 int i, rc;
1409
1410 rc = xive_irq_domain_translate(d: domain, fwspec, hwirq: &hwirq, type: &type);
1411 if (rc)
1412 return rc;
1413
1414 pr_debug("%s %d/0x%lx #%d\n", __func__, virq, hwirq, nr_irqs);
1415
1416 for (i = 0; i < nr_irqs; i++) {
1417 /* TODO: call xive_irq_domain_map() */
1418
1419 /*
1420 * Mark interrupts as edge sensitive by default so that resend
1421 * actually works. Will fix that up below if needed.
1422 */
1423 irq_clear_status_flags(irq: virq, clr: IRQ_LEVEL);
1424
1425 /* allocates and sets handler data */
1426 xd = xive_irq_alloc_data(virq: virq + i, hw: hwirq + i);
1427 if (IS_ERR(ptr: xd))
1428 return PTR_ERR(ptr: xd);
1429
1430 irq_domain_set_hwirq_and_chip(domain, virq: virq + i, hwirq: hwirq + i, chip: &xive_irq_chip, chip_data: xd);
1431 irq_set_handler(irq: virq + i, handle: handle_fasteoi_irq);
1432 }
1433
1434 return 0;
1435}
1436
1437static void xive_irq_domain_free(struct irq_domain *domain,
1438 unsigned int virq, unsigned int nr_irqs)
1439{
1440 int i;
1441
1442 pr_debug("%s %d #%d\n", __func__, virq, nr_irqs);
1443
1444 for (i = 0; i < nr_irqs; i++)
1445 xive_irq_free_data(virq: virq + i);
1446}
1447#endif
1448
1449static const struct irq_domain_ops xive_irq_domain_ops = {
1450#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
1451 .alloc = xive_irq_domain_alloc,
1452 .free = xive_irq_domain_free,
1453 .translate = xive_irq_domain_translate,
1454#endif
1455 .match = xive_irq_domain_match,
1456 .map = xive_irq_domain_map,
1457 .unmap = xive_irq_domain_unmap,
1458 .xlate = xive_irq_domain_xlate,
1459#ifdef CONFIG_GENERIC_IRQ_DEBUGFS
1460 .debug_show = xive_irq_domain_debug_show,
1461#endif
1462};
1463
1464static void __init xive_init_host(struct device_node *np)
1465{
1466 xive_irq_domain = irq_domain_create_tree(of_fwnode_handle(np), ops: &xive_irq_domain_ops, NULL);
1467 if (WARN_ON(xive_irq_domain == NULL))
1468 return;
1469 irq_set_default_domain(domain: xive_irq_domain);
1470}
1471
1472static void xive_cleanup_cpu_queues(unsigned int cpu, struct xive_cpu *xc)
1473{
1474 if (xc->queue[xive_irq_priority].qpage)
1475 xive_ops->cleanup_queue(cpu, xc, xive_irq_priority);
1476}
1477
1478static int xive_setup_cpu_queues(unsigned int cpu, struct xive_cpu *xc)
1479{
1480 int rc = 0;
1481
1482 /* We setup 1 queues for now with a 64k page */
1483 if (!xc->queue[xive_irq_priority].qpage)
1484 rc = xive_ops->setup_queue(cpu, xc, xive_irq_priority);
1485
1486 return rc;
1487}
1488
1489static int xive_prepare_cpu(unsigned int cpu)
1490{
1491 struct xive_cpu *xc;
1492
1493 xc = per_cpu(xive_cpu, cpu);
1494 if (!xc) {
1495 xc = kzalloc_node(sizeof(struct xive_cpu),
1496 GFP_KERNEL, cpu_to_node(cpu));
1497 if (!xc)
1498 return -ENOMEM;
1499 xc->hw_ipi = XIVE_BAD_IRQ;
1500 xc->chip_id = XIVE_INVALID_CHIP_ID;
1501 if (xive_ops->prepare_cpu)
1502 xive_ops->prepare_cpu(cpu, xc);
1503
1504 per_cpu(xive_cpu, cpu) = xc;
1505 }
1506
1507 /* Setup EQs if not already */
1508 return xive_setup_cpu_queues(cpu, xc);
1509}
1510
1511static void xive_setup_cpu(void)
1512{
1513 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1514
1515 /* The backend might have additional things to do */
1516 if (xive_ops->setup_cpu)
1517 xive_ops->setup_cpu(smp_processor_id(), xc);
1518
1519 /* Set CPPR to 0xff to enable flow of interrupts */
1520 xc->cppr = 0xff;
1521 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff);
1522}
1523
1524#ifdef CONFIG_SMP
1525void xive_smp_setup_cpu(void)
1526{
1527 pr_debug("SMP setup CPU %d\n", smp_processor_id());
1528
1529 /* This will have already been done on the boot CPU */
1530 if (smp_processor_id() != boot_cpuid)
1531 xive_setup_cpu();
1532
1533}
1534
1535int xive_smp_prepare_cpu(unsigned int cpu)
1536{
1537 int rc;
1538
1539 /* Allocate per-CPU data and queues */
1540 rc = xive_prepare_cpu(cpu);
1541 if (rc)
1542 return rc;
1543
1544 /* Allocate and setup IPI for the new CPU */
1545 return xive_setup_cpu_ipi(cpu);
1546}
1547
1548#ifdef CONFIG_HOTPLUG_CPU
1549static void xive_flush_cpu_queue(unsigned int cpu, struct xive_cpu *xc)
1550{
1551 u32 irq;
1552
1553 /* We assume local irqs are disabled */
1554 WARN_ON(!irqs_disabled());
1555
1556 /* Check what's already in the CPU queue */
1557 while ((irq = xive_scan_interrupts(xc, just_peek: false)) != 0) {
1558 /*
1559 * We need to re-route that interrupt to its new destination.
1560 * First get and lock the descriptor
1561 */
1562 struct irq_desc *desc = irq_to_desc(irq);
1563 struct irq_data *d = irq_desc_get_irq_data(desc);
1564 struct xive_irq_data *xd;
1565
1566 /*
1567 * Ignore anything that isn't a XIVE irq and ignore
1568 * IPIs, so can just be dropped.
1569 */
1570 if (d->domain != xive_irq_domain)
1571 continue;
1572
1573 /*
1574 * The IRQ should have already been re-routed, it's just a
1575 * stale in the old queue, so re-trigger it in order to make
1576 * it reach is new destination.
1577 */
1578#ifdef DEBUG_FLUSH
1579 pr_info("CPU %d: Got irq %d while offline, re-sending...\n",
1580 cpu, irq);
1581#endif
1582 raw_spin_lock(&desc->lock);
1583 xd = irq_desc_get_chip_data(desc);
1584
1585 /*
1586 * Clear saved_p to indicate that it's no longer pending
1587 */
1588 xd->saved_p = false;
1589
1590 /*
1591 * For LSIs, we EOI, this will cause a resend if it's
1592 * still asserted. Otherwise do an MSI retrigger.
1593 */
1594 if (xd->flags & XIVE_IRQ_FLAG_LSI)
1595 xive_do_source_eoi(xd);
1596 else
1597 xive_irq_retrigger(d);
1598
1599 raw_spin_unlock(&desc->lock);
1600 }
1601}
1602
1603void xive_smp_disable_cpu(void)
1604{
1605 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1606 unsigned int cpu = smp_processor_id();
1607
1608 /* Migrate interrupts away from the CPU */
1609 irq_migrate_all_off_this_cpu();
1610
1611 /* Set CPPR to 0 to disable flow of interrupts */
1612 xc->cppr = 0;
1613 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0);
1614
1615 /* Flush everything still in the queue */
1616 xive_flush_cpu_queue(cpu, xc);
1617
1618 /* Re-enable CPPR */
1619 xc->cppr = 0xff;
1620 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff);
1621}
1622
1623void xive_flush_interrupt(void)
1624{
1625 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1626 unsigned int cpu = smp_processor_id();
1627
1628 /* Called if an interrupt occurs while the CPU is hot unplugged */
1629 xive_flush_cpu_queue(cpu, xc);
1630}
1631
1632#endif /* CONFIG_HOTPLUG_CPU */
1633
1634#endif /* CONFIG_SMP */
1635
1636noinstr void xive_teardown_cpu(void)
1637{
1638 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1639 unsigned int cpu = smp_processor_id();
1640
1641 /* Set CPPR to 0 to disable flow of interrupts */
1642 xc->cppr = 0;
1643 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0);
1644
1645 if (xive_ops->teardown_cpu)
1646 xive_ops->teardown_cpu(cpu, xc);
1647
1648#ifdef CONFIG_SMP
1649 /* Get rid of IPI */
1650 xive_cleanup_cpu_ipi(cpu, xc);
1651#endif
1652
1653 /* Disable and free the queues */
1654 xive_cleanup_cpu_queues(cpu, xc);
1655}
1656
1657void xive_shutdown(void)
1658{
1659 xive_ops->shutdown();
1660}
1661
1662bool __init xive_core_init(struct device_node *np, const struct xive_ops *ops,
1663 void __iomem *area, u32 offset, u8 max_prio)
1664{
1665 xive_tima = area;
1666 xive_tima_offset = offset;
1667 xive_ops = ops;
1668 xive_irq_priority = max_prio;
1669
1670 ppc_md.get_irq = xive_get_irq;
1671 __xive_enabled = true;
1672
1673 pr_debug("Initializing host..\n");
1674 xive_init_host(np);
1675
1676 pr_debug("Initializing boot CPU..\n");
1677
1678 /* Allocate per-CPU data and queues */
1679 xive_prepare_cpu(smp_processor_id());
1680
1681 /* Get ready for interrupts */
1682 xive_setup_cpu();
1683
1684 pr_info("Interrupt handling initialized with %s backend\n",
1685 xive_ops->name);
1686 pr_info("Using priority %d for all interrupts\n", max_prio);
1687
1688 return true;
1689}
1690
1691__be32 *xive_queue_page_alloc(unsigned int cpu, u32 queue_shift)
1692{
1693 unsigned int alloc_order;
1694 struct page *pages;
1695 __be32 *qpage;
1696
1697 alloc_order = xive_alloc_order(queue_shift);
1698 pages = alloc_pages_node(cpu_to_node(cpu), GFP_KERNEL, alloc_order);
1699 if (!pages)
1700 return ERR_PTR(error: -ENOMEM);
1701 qpage = (__be32 *)page_address(pages);
1702 memset(qpage, 0, 1 << queue_shift);
1703
1704 return qpage;
1705}
1706
1707static int __init xive_off(char *arg)
1708{
1709 xive_cmdline_disabled = true;
1710 return 1;
1711}
1712__setup("xive=off", xive_off);
1713
1714static int __init xive_store_eoi_cmdline(char *arg)
1715{
1716 if (!arg)
1717 return 1;
1718
1719 if (strncmp(arg, "off", 3) == 0) {
1720 pr_info("StoreEOI disabled on kernel command line\n");
1721 xive_store_eoi = false;
1722 }
1723 return 1;
1724}
1725__setup("xive.store-eoi=", xive_store_eoi_cmdline);
1726
1727#ifdef CONFIG_DEBUG_FS
1728static void xive_debug_show_ipi(struct seq_file *m, int cpu)
1729{
1730 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
1731
1732 seq_printf(m, fmt: "CPU %d: ", cpu);
1733 if (xc) {
1734 seq_printf(m, fmt: "pp=%02x CPPR=%02x ", xc->pending_prio, xc->cppr);
1735
1736#ifdef CONFIG_SMP
1737 {
1738 char buffer[128];
1739
1740 xive_irq_data_dump(xd: &xc->ipi_data, buffer, size: sizeof(buffer));
1741 seq_printf(m, fmt: "IPI=0x%08x %s", xc->hw_ipi, buffer);
1742 }
1743#endif
1744 }
1745 seq_puts(m, s: "\n");
1746}
1747
1748static void xive_debug_show_irq(struct seq_file *m, struct irq_data *d)
1749{
1750 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
1751 int rc;
1752 u32 target;
1753 u8 prio;
1754 u32 lirq;
1755 char buffer[128];
1756
1757 rc = xive_ops->get_irq_config(hw_irq, &target, &prio, &lirq);
1758 if (rc) {
1759 seq_printf(m, fmt: "IRQ 0x%08x : no config rc=%d\n", hw_irq, rc);
1760 return;
1761 }
1762
1763 seq_printf(m, fmt: "IRQ 0x%08x : target=0x%x prio=%02x lirq=0x%x ",
1764 hw_irq, target, prio, lirq);
1765
1766 xive_irq_data_dump(xd: irq_data_get_irq_chip_data(d), buffer, size: sizeof(buffer));
1767 seq_puts(m, s: buffer);
1768 seq_puts(m, s: "\n");
1769}
1770
1771static int xive_irq_debug_show(struct seq_file *m, void *private)
1772{
1773 unsigned int i;
1774 struct irq_desc *desc;
1775
1776 for_each_irq_desc(i, desc) {
1777 struct irq_data *d = irq_domain_get_irq_data(domain: xive_irq_domain, virq: i);
1778
1779 if (d)
1780 xive_debug_show_irq(m, d);
1781 }
1782 return 0;
1783}
1784DEFINE_SHOW_ATTRIBUTE(xive_irq_debug);
1785
1786static int xive_ipi_debug_show(struct seq_file *m, void *private)
1787{
1788 int cpu;
1789
1790 if (xive_ops->debug_show)
1791 xive_ops->debug_show(m, private);
1792
1793 for_each_online_cpu(cpu)
1794 xive_debug_show_ipi(m, cpu);
1795 return 0;
1796}
1797DEFINE_SHOW_ATTRIBUTE(xive_ipi_debug);
1798
1799static void xive_eq_debug_show_one(struct seq_file *m, struct xive_q *q, u8 prio)
1800{
1801 int i;
1802
1803 seq_printf(m, fmt: "EQ%d idx=%d T=%d\n", prio, q->idx, q->toggle);
1804 if (q->qpage) {
1805 for (i = 0; i < q->msk + 1; i++) {
1806 if (!(i % 8))
1807 seq_printf(m, fmt: "%05d ", i);
1808 seq_printf(m, fmt: "%08x%s", be32_to_cpup(p: q->qpage + i),
1809 (i + 1) % 8 ? " " : "\n");
1810 }
1811 }
1812 seq_puts(m, s: "\n");
1813}
1814
1815static int xive_eq_debug_show(struct seq_file *m, void *private)
1816{
1817 int cpu = (long)m->private;
1818 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
1819
1820 if (xc)
1821 xive_eq_debug_show_one(m, q: &xc->queue[xive_irq_priority],
1822 prio: xive_irq_priority);
1823 return 0;
1824}
1825DEFINE_SHOW_ATTRIBUTE(xive_eq_debug);
1826
1827static void xive_core_debugfs_create(void)
1828{
1829 struct dentry *xive_dir;
1830 struct dentry *xive_eq_dir;
1831 long cpu;
1832 char name[16];
1833
1834 xive_dir = debugfs_create_dir(name: "xive", parent: arch_debugfs_dir);
1835 if (IS_ERR(ptr: xive_dir))
1836 return;
1837
1838 debugfs_create_file("ipis", 0400, xive_dir,
1839 NULL, &xive_ipi_debug_fops);
1840 debugfs_create_file("interrupts", 0400, xive_dir,
1841 NULL, &xive_irq_debug_fops);
1842 xive_eq_dir = debugfs_create_dir(name: "eqs", parent: xive_dir);
1843 for_each_possible_cpu(cpu) {
1844 snprintf(buf: name, size: sizeof(name), fmt: "cpu%ld", cpu);
1845 debugfs_create_file(name, 0400, xive_eq_dir, (void *)cpu,
1846 &xive_eq_debug_fops);
1847 }
1848 debugfs_create_bool(name: "store-eoi", mode: 0600, parent: xive_dir, value: &xive_store_eoi);
1849
1850 if (xive_ops->debug_create)
1851 xive_ops->debug_create(xive_dir);
1852}
1853#else
1854static inline void xive_core_debugfs_create(void) { }
1855#endif /* CONFIG_DEBUG_FS */
1856
1857int xive_core_debug_init(void)
1858{
1859 if (xive_enabled() && IS_ENABLED(CONFIG_DEBUG_FS))
1860 xive_core_debugfs_create();
1861
1862 return 0;
1863}
1864

source code of linux/arch/powerpc/sysdev/xive/common.c